CN114977757A - Control circuit with soft start and soft turn-off functions - Google Patents

Control circuit with soft start and soft turn-off functions Download PDF

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Publication number
CN114977757A
CN114977757A CN202210421770.8A CN202210421770A CN114977757A CN 114977757 A CN114977757 A CN 114977757A CN 202210421770 A CN202210421770 A CN 202210421770A CN 114977757 A CN114977757 A CN 114977757A
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node
soft
voltage
switch
current source
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李现坤
邓文涛
吕笑天
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a control circuit with soft start and soft turn-off functions, which belongs to the field of power management and comprises a charge-discharge module, a voltage clamping module and a buffer module; the charging and discharging module charges and discharges a capacitor on a soft start and soft turn-off configuration SS port, and controls the voltage of the capacitor to slowly rise or fall; when the control circuit enters a turn-off state, the voltage clamping module rapidly carries out voltage clamping on a capacitor on a soft start and soft turn-off configuration SS port and the output voltage of the buffer module, and clamps the capacitor voltage and the output voltage of the buffer to be fixed voltage values; the buffer module is used for buffering and outputting the voltage of the capacitor on the SS port, so that an output signal S _ CTR of the soft start and soft shutdown function control circuit follows the voltage change of the capacitor on the SS port. The invention not only has the soft start control function, but also has the soft turn-off control function.

Description

Control circuit with soft start and soft turn-off functions
Technical Field
The invention relates to the technical field of power management, in particular to a control circuit with soft start and soft shutdown functions.
Background
When the power conversion circuit is powered on and started, in order to avoid surge current at an input power port and require monotonous and smooth rise of output voltage waveform, a soft start circuit is often required to be designed to control the power on and starting of the circuit. When the power conversion circuit outputs power-off, for some special memories such as an EEPROM and the like, in order to ensure that the storage circuit can normally store the power, the power-off requirement of a power supply has a soft-off function, namely the power supply needs to be maintained for a period of time in a certain voltage range and meet a certain time sequence when the power supply is powered off.
The invention provides a control circuit with soft start and soft shut-off functions, aiming at solving the problems of power-on start and power-off shut-off of the output of a power conversion circuit.
Disclosure of Invention
The present invention is directed to a control circuit with soft-start and soft-off functions to solve the problems of the prior art.
In order to solve the above technical problems, the present invention provides a control circuit with soft start and soft shutdown functions, which includes a charge-discharge module, a voltage clamping module and a buffer module;
the charging and discharging module charges and discharges a capacitor on a soft start and soft turn-off configuration SS port, and controls the voltage of the capacitor to slowly rise or fall;
when the control circuit enters a turn-off state, the voltage clamping module rapidly carries out voltage clamping on a capacitor on a soft start and soft turn-off configuration SS port and the output voltage of the buffer module, and clamps the capacitor voltage and the output voltage of the buffer to be fixed voltage values;
the buffer module is used for buffering and outputting the voltage of the capacitor on the SS port, so that an output signal S _ CTR of the soft start and soft shutdown function control circuit follows the voltage change of the capacitor on the SS port.
Optionally, the charging and discharging module includes a current source I 1 ～I 2 Switches S1-S2; the current source I 1 Is connected to the power supply, and the second node is connected to the first node of the switch S1; the second node of the switch S1 is connected with the current source I 2 A first node of (1), a current source I 2 The second node of (a) is grounded;
the second node of the switch S1 and the first node of the switch S2 are connected to an external SS port through a capacitor C SS And (4) grounding.
Optionally, the voltage clamping module includes switches S3 to S6 and a current source I 3 The first node of the switch S3, the first node of the switch S4 and the first node of the switch S5 are all connected to the external SS port, and the second node of the switch S5 and the first node of the switch S6 are all connected to the current source I 3 Second node of (1), current source I 3 The first node of the voltage regulator is connected with a clamping reference voltage VREF; the second node of switch S3, the second node of switch S4, and the second node of switch S6 are all connected to the buffer module.
Optionally, the buffer module includes a unity gain buffer a1, an input terminal of the unity gain buffer a1 is connected to the second node of the switch S3 and the second node of the switch S4, and an output terminal is connected to the second node of the switch S6.
Optionally, the charging and discharging module includes a current source I 1 ～I 2 PMOS tube MP1, NMOS tube MN 1-MN 3; current source I 1 The first node of the PMOS transistor MP1 is connected with a power supply, the second node of the PMOS transistor MP1 is connected with the source end of a PMOS transistor MP1, and the drain end of the PMOS transistor MP1 is connected with the drain end and the gate end of an NMOS transistor MN 1; the source end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN 2; the source end of the NMOS transistor MN2 passes through a current source I 2 Grounding; the gate end of the PMOS transistor MP1 and the gate end of the NMOS transistor MN2 are both connected with SD 1;
the drain end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN2, the source end of the NMOS tube is grounded, and the grid end of the NMOS tube MN is connected with a RESET signal RESET;
the drain terminal of the NMOS tube MN2 and the drain terminal of the NMOS tube MN3 are simultaneously connected with an external SS port, and the external SS port is connected with an external SS port through a capacitor C SS And (4) grounding.
Optionally, the voltage clamping module comprises a current source I 3 The NMOS transistor MN4, the unit gain buffer A2 and the transmission gates TG 1-TG 3; current source I 3 The first node of the second node is connected with a power supply, and the second node is simultaneously connected with a first input end of a transmission gate TG2, a gate end and a drain end of an NMOS tube MN 4; the source end of the NMOS tube MN4 is connected with the output end of the unit gain buffer A2;
a first input end of the transmission gate TG1 is connected with a gate end and a drain end of an NMOS tube MN1, a second input end is connected with SD1, and a third input end is connected with a source end of an NMOS tube MN2 and a source end of an NMOS tube MN 1;
a first input terminal of the transmission gate TG2 is connected with a current source I 3 First section ofThe point, the drain end and the gate end of an NMOS tube MN4, the second input end is connected with an SD2, and the third input end is connected with the drain end of an NMOS tube MN2 and the source end of an NMOS tube MN 1;
the first input end of the transmission gate TG3 is connected to the source end of the NMOS transistor MN4 and the output end of the unity gain buffer a2, and the second input end is connected to the SD 2.
Optionally, the buffer module includes an NMOS transistor MN5 and a current source I 4 (ii) a The drain terminal of the NMOS tube MN5 is connected with a power supply, and the source terminal is connected with a current source I 4 A first node of (1), a current source I 4 The second node of (a) is grounded; a third input end of the transmission gate TG3 is connected with the source end of the NMOS tube MN5 and the current source I 4 Between the first nodes.
When the circuit is powered on and started, the capacitor is discharged and reset, then the charging current source charges the capacitor, the voltage on the capacitor slowly rises from zero, the output of the buffer module is increased along with the voltage of the capacitor, the output of the power conversion circuit is controlled to be increased along with the voltage of the capacitor, when the voltage of an SS port is higher than an internal reference voltage VREF, a branch controlled by an S _ CTR input in an error amplifier is switched off, and the output voltage of the power conversion circuit is started to a normal output value; when the circuit is switched off, the switching gating switch enters a clamping state, the voltage clamping module clamps the SS port voltage and the output of the buffer module to an internal reference voltage VREF, then the switching gating switch is switched again to enter a soft switching-off state, a discharging current source discharges the capacitor, the voltage on the capacitor begins to slowly drop from the VREF, the output of the buffer module drops along with the voltage of the capacitor, the output of the power conversion circuit is controlled to drop along with the output of the power conversion circuit until the output of the buffer module drops to zero, and the output of the power conversion circuit also drops to zero.
Drawings
FIG. 1 is a schematic diagram of a control circuit with soft start and soft shutdown functions according to the present invention;
FIG. 2 is a schematic diagram of an implementation and improvement of a control circuit having soft-start and soft-off functions in FIG. 1;
fig. 3 is a timing waveform based on the soft-start and soft-off control functions of fig. 2.
Detailed Description
The following describes a control circuit with soft-start and soft-off functions according to the present invention in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the present invention, the terms "connected", "connecting", and the like mean electrically connected, and mean directly or indirectly electrically connected unless otherwise specified.
The invention provides a control circuit with soft start and soft shutdown functions, which is shown as 1 and mainly comprises a charge-discharge module 1, a voltage clamping module 2 and a buffer module 3. In the charge-discharge module 1, a current source I 1 Is connected to the power supply, the second node is connected to the first node of the switch S1, the second node of the switch S1 and the first node of the switch S2 are simultaneously connected to the external SS port, the second node of the switch S2 is connected to the current source I 2 Is connected to a current source I 2 Is connected to ground. In the voltage clamping module 2, a first node of the switch S3, a first node of the switch S4, and a first node of the switch S5 are all connected to an external SS port, a second node of the switch S3 and a second node of the switch S4 are connected to a first node of the buffer module 3 (i.e., an input terminal of the unity gain buffer a 1), and a current source I 3 Is connected to a clamping reference voltage VREF, a current source I 3 Is connected to both the second node of the switch S5 and the first node of the switch S6, and the second node of the switch S6 is connected to the second node (i.e., the output terminal of the unity gain buffer a 1) SS _ CTR of the buffer module 3; external SS port pass through capacitor C SS And (4) grounding.
The circuit of the invention has the following specific working principle:
when the circuit is powered on and started, the switches S1 and S3 are closed, the switches S2 and S4-S6 are opened, and the current source I 1 To the capacitorC SS Charging, capacitance C SS The voltage on the buffer rises from zero, and the unit gain buffer A1 outputs a voltage V S_CTR Following capacitor C SS Voltage V above SS ：
Figure BDA0003608128190000041
When the voltage of the external SS port is higher than the internal reference voltage VREF, a branch controlled by S _ CTR in the power conversion circuit is turned off, the output of the power conversion circuit is started to a normal output value, and the soft start time t is SS Comprises the following steps:
Figure BDA0003608128190000042
Figure BDA0003608128190000043
when the circuit is turned off, the circuit firstly inputs a clamping state, the switches S2 and S4-S6 are closed, the switches S1 and S3 are opened, and the voltage clamping module 2 enables the capacitor C to be connected with the capacitor C SS Voltage V above SS The output V of the unity gain buffer A1 S_CTR Clamping to V REF 。
V SS ＝V S_CTR ＝V REF
Then the gating switch is switched, the switches S2 and S4 are closed, the switches S1, S3, S5 and S6 are opened, the circuit enters a soft off state, and the current source I is discharged 2 To the capacitor C SS Discharging is carried out, the capacitor C SS Voltage V on SS Starting from VREF, the unit gain buffer A1 outputs V S_CTR Following capacitor C SS Voltage V SS And (4) reducing, controlling the output of the power conversion circuit to follow the reduction until the output of the unit gain buffer A1 is reduced to zero, and reducing the output of the power conversion circuit to zero. Soft off time t SS Comprises the following steps:
Figure BDA0003608128190000051
Figure BDA0003608128190000052
fig. 2 is an implementation and improvement of a control circuit with soft start and soft shutdown functions based on fig. 1. In fig. 2, PMOS transistor MP1 and NMOS transistor MN2 realize switches S1 and S2 in fig. 2, transmission gates TG1 and TG3 realize switches S5 and S6 in fig. 1, and NMOS transistor MN5 realizes a source follower buffer. In order to compensate the gate-source voltage (V) of the source follower buffer of the NMOS transistor MN4 GS ) In the circuit implementation of the branch in which the switches S3 and S5 shown in fig. 1 are located, NMOS transistors of gate-drain connection are respectively inserted, the switch S3 in fig. 1 is implemented by the NMOS transistor MN1 in fig. 2, and the switch S5 in fig. 1 is implemented by the NMOS transistor MN3 and the transmission gate TG 2.
FIG. 3 is a verified simulated timing waveform of the embodiment of FIG. 2. When the circuit is powered on and started (V1 moment), the RESET signal controls the NMOS tube MN3 to be conducted, and the capacitor C is connected SS Reset by discharging, then charge current source I 1 To the capacitor C SS Charging (time V2), capacitor C SS Voltage V on SS Slowly rising from zero, source follower buffer output V S_CTR Following capacitor C SS When the voltage of the SS port voltage V rises, the output voltage of the power supply conversion circuit is controlled to rise along with the rise SS Above the internal reference voltage VREF (at time V3), the output signal V of the unity gain buffer A1 S_CTR The controlled branch is switched off, and the output of the power supply conversion circuit is started to a normal output value; when the circuit is switched off (at the moment of V4), the switching gating switch enters a clamping state, the voltage clamping module 2 clamps the SS port voltage and the source follower buffer output to the internal reference voltage VREF, then the switching gating switch is switched again to enter a soft off state, and the discharging current source I discharges 2 To the capacitor C SS Discharging is carried out, the capacitor C SS The voltage on the capacitor gradually drops from VREF, and the output of the source following buffer follows the capacitor C SS To control the output V of the power conversion circuit OUT Follows the fall until the capacitance C SS OnVoltage V SS Falls to zero and the power conversion circuit output also falls to zero (at time V5).
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (7)

1. A control circuit with soft start and soft shut-off functions is characterized by comprising a charge-discharge module, a voltage clamping module and a buffer module;
the charging and discharging module charges and discharges a capacitor on a soft start and soft turn-off configuration SS port, and controls the voltage of the capacitor to slowly rise or fall;
when the control circuit enters a turn-off state, the voltage clamping module rapidly carries out voltage clamping on a capacitor on a soft start and soft turn-off configuration SS port and the output voltage of the buffer module, and clamps the capacitor voltage and the output voltage of the buffer to be fixed voltage values;
the buffer module is used for buffering and outputting the voltage of the capacitor on the SS port, so that an output signal S _ CTR of the soft start and soft shutdown function control circuit follows the voltage change of the capacitor on the SS port.
2. The control circuit with soft-start and soft-off functions as claimed in claim 1, wherein the charge-discharge module comprises a current source I 1 ～I 2 Switches S1-S2; the current source I 1 Is connected to the power supply, and the second node is connected to the first node of the switch S1; the second node of the switch S1 is connected with the current source I 2 A first node of (1), a current source I 2 The second node of (a) is grounded;
the second node of the switch S1 and the first node of the switch S2 are connected to an external SS port through a capacitor C SS And (4) grounding.
3. The control circuit with soft start and soft shutdown functions as claimed in claim 2,wherein the voltage clamping module comprises switches S3-S6 and a current source I 3 The first node of the switch S3, the first node of the switch S4 and the first node of the switch S5 are all connected to the external SS port, and the second node of the switch S5 and the first node of the switch S6 are all connected to the current source I 3 Second node of (1), current source I 3 The first node of the voltage regulator is connected with a clamping reference voltage VREF; the second node of switch S3, the second node of switch S4, and the second node of switch S6 are all connected to the buffer module.
4. The control circuit with soft-start and soft-off function as claimed in claim 3, wherein the buffer module comprises a unity gain buffer A1, the input terminal of the unity gain buffer A1 is connected to the second node of the switch S3 and the second node of the switch S4 at the same time, and the output terminal is connected to the second node of the switch S6.
5. The control circuit with soft-start and soft-off functions as claimed in claim 1, wherein the charge-discharge module comprises a current source I 1 ～I 2 PMOS tube MP1, NMOS tube MN 1-MN 3; current source I 1 The first node of the PMOS transistor MP1 is connected with a power supply, the second node of the PMOS transistor MP1 is connected with the source end of a PMOS transistor MP1, and the drain end of the PMOS transistor MP1 is connected with the drain end and the gate end of an NMOS transistor MN 1; the source end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN 2; the source end of the NMOS transistor MN2 passes through a current source I 2 Grounding; the gate end of the PMOS transistor MP1 and the gate end of the NMOS transistor MN2 are both connected with SD 1;
the drain end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN2, the source end is grounded, and the gate end is connected with a RESET signal RESET;
the drain terminal of the NMOS tube MN2 and the drain terminal of the NMOS tube MN3 are simultaneously connected with an external SS port, and the external SS port is connected with an external SS port through a capacitor C SS And (4) grounding.
6. The control circuit with soft-start and soft-off of claim 5, wherein the voltage clamping module comprises a current source I 3 The NMOS transistor MN4, the unit gain buffer A2 and the transmission gates TG 1-TG 3; current source I 3 The first node of the second node is connected with a power supply, and the second node is simultaneously connected with a first input end of a transmission gate TG2, a gate end and a drain end of an NMOS tube MN 4; the source end of the NMOS tube MN4 is connected with the output end of the unit gain buffer A2;
a first input end of the transmission gate TG1 is connected with a gate end and a drain end of an NMOS tube MN1, a second input end is connected with SD1, and a third input end is connected with a source end of an NMOS tube MN2 and a source end of an NMOS tube MN 1;
a first input terminal of the transmission gate TG2 is connected with a current source I 3 The second input end is connected with the SD2, and the third input end is connected with the drain end of the NMOS tube MN2 and the source end of the NMOS tube MN 1;
the first input end of the transmission gate TG3 is connected to the source end of the NMOS transistor MN4 and the output end of the unity gain buffer a2, and the second input end is connected to the SD 2.
7. The control circuit with soft-start and soft-off function as claimed in claim 6, wherein said buffer module comprises an NMOS transistor MN5 and a current source I 4 (ii) a The drain terminal of the NMOS tube MN5 is connected with a power supply, and the source terminal is connected with a current source I 4 First node of (2), current source I 4 The second node of (a) is grounded; a third input end of the transmission gate TG3 is connected with the source end of the NMOS tube MN5 and the current source I 4 Between the first nodes.
CN202210421770.8A 2022-04-21 2022-04-21 Control circuit with soft start and soft turn-off functions Pending CN114977757A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116526820A (en) * 2023-01-10 2023-08-01 深圳市思远半导体有限公司 Chip, direct current-direct current circuit and control method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116526820A (en) * 2023-01-10 2023-08-01 深圳市思远半导体有限公司 Chip, direct current-direct current circuit and control method thereof
CN116526821A (en) * 2023-01-10 2023-08-01 深圳市思远半导体有限公司 Chip, direct current-direct current circuit and control method thereof
CN116526820B (en) * 2023-01-10 2023-11-28 深圳市思远半导体有限公司 Chip, direct current-direct current circuit and control method thereof
CN116526821B (en) * 2023-01-10 2024-03-19 深圳市思远半导体有限公司 Chip, direct current-direct current circuit and control method thereof

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