CN112713858A

CN112713858A - Oscillator

Info

Publication number: CN112713858A
Application number: CN202011528074.4A
Authority: CN
Inventors: 雷宇超; 张旭; 陈光胜
Original assignee: Shanghai Eastsoft Microelectronics Co ltd
Current assignee: Shanghai Eastsoft Microelectronics Co ltd
Priority date: 2020-12-22
Filing date: 2020-12-22
Publication date: 2021-04-27

Abstract

An oscillator, comprising: the chopper voltage average value feedback circuit has one input end for inputting temperature drift calibration reference voltage and the other input end coupled to one voltage output end of the RC charge-discharge circuit; the input end of the threshold voltage detection circuit is respectively coupled with the chopping voltage average value feedback circuit and the RC charge-discharge circuit; the other two voltage output ends of the RC charge-discharge circuit are coupled with the two input ends of the threshold voltage detection circuit; two output ends of the threshold voltage detection circuit are coupled with two input ends of the ESR trigger control circuit; two input ends of the stable clock output circuit are coupled with two output ends of the ESR trigger control circuit, the two output ends respectively output two paths of clock signals, and the other output end outputs a clock stability indicating signal; and two signal input ends of the chopping clock bootstrap circuit are respectively coupled with the second output end and the third output end of the stable clock output circuit. The oscillator output clock frequency is independent of temperature and voltage.

Description

Oscillator

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an oscillator.

Background

An oscillator is an energy conversion device that can generate an ac signal with a certain frequency, a certain amplitude, and a certain waveform. Due to the requirement for integration level, a high-precision oscillator needs to be integrated inside a Micro Controller Unit (MCU) chip.

In a chip, a traditional RC oscillator adopts a comparator to control RC charge and discharge; the traditional current source type sawtooth wave oscillator adopts a current source and a current trap to charge and discharge a capacitor respectively, then sets a charge and discharge voltage threshold through two comparators, and realizes charge and discharge switching through an SR trigger.

However, the existing oscillator structures all use a comparator, and because the comparator has a delay, when the output frequency is low (for example, less than 1MHz), the error is small, but when the output frequency exceeds 10MHz, the delay of the comparator changes with temperature and voltage, and the error of the output clock frequency is large.

Disclosure of Invention

The embodiment of the invention solves the technical problem of larger error caused by the change of the output clock frequency along with the change of temperature and voltage.

To solve the above technical problem, an embodiment of the present invention provides an oscillator, including: chopper voltage average value feedback circuit, RC charge-discharge circuit, threshold voltage detection circuit, ESR trigger control circuit, stable clock output circuit and chopper clock bootstrap circuit, wherein: a first input end of the chopping voltage average value feedback circuit inputs a temperature drift calibration reference voltage, a second input end of the chopping voltage average value feedback circuit is coupled with a first voltage output end of the RC charge-discharge circuit, a clock signal input end of the chopping voltage average value feedback circuit is coupled with a clock signal output end of the chopping clock bootstrap circuit, and an enable signal input end of the chopping voltage average value feedback circuit is coupled with an enable signal output end of the chopping clock bootstrap circuit; a first input end and a second input end of the threshold voltage detection circuit are both coupled with an output end of the chopping voltage average value feedback circuit, a third input end of the threshold voltage detection circuit is coupled with a second voltage output end of the RC charge-discharge circuit, and a fourth input end of the threshold voltage detection circuit is coupled with a third voltage output end of the RC charge-discharge circuit; the first input end of the RC charge-discharge circuit is coupled with the first output end of the ESR trigger control circuit, and the second input end of the RC charge-discharge circuit is coupled with the second output end of the ESR trigger control circuit; the first input end of the ESR trigger control circuit is coupled with the first output end of the threshold voltage detection circuit, the second input end of the ESR trigger control circuit is coupled with the second output end of the threshold voltage detection circuit, and the third input end of the ESR trigger control circuit inputs an enabling signal; the first input end of the stable clock output circuit is coupled with the second output end of the ESR trigger control circuit, the second input end of the stable clock output circuit is coupled with the first output end of the ESR trigger control circuit, the first output end of the stable clock output circuit outputs a first output clock signal, the second output end of the stable clock output circuit outputs a second output clock signal, and the third output end of the stable clock output circuit outputs a clock stability indicating signal; and the chopping clock bootstrap circuit is provided with a clock signal input end coupled with the second output end of the stable clock output circuit, and an enable signal input end coupled with the third output end of the stable clock output circuit.

Optionally, the chopper voltage average value feedback circuit includes: a chopping operational amplifier COA and an integrating loop, wherein: the first input end of the chopping operational amplifier COA inputs the temperature drift calibration reference voltage, the second input end of the chopping operational amplifier COA is coupled with the input end of the integrating circuit, and the output end of the chopping operational amplifier COA is coupled with the output end of the integrating circuit, the first input end of the threshold voltage detection circuit and the second input end of the threshold voltage detection circuit; and the input end of the integration loop is coupled with the first voltage output end of the RC charge-discharge circuit.

Optionally, the integration loop includes an integration resistor Rx and an integration capacitor Cx, wherein: the first end of the integrating resistor Rx is coupled with the first voltage output end of the RC charge-discharge circuit, and the second end of the integrating resistor Rx is coupled with the first end of the integrating capacitor Cx and the second input end of the chopping operational amplifier COA; and a second end of the integrating capacitor Cx is coupled to the output end of the chopping operational amplifier COA.

Optionally, the chopping operational amplifier COA includes: first chopper circuit, second chopper circuit, third chopper circuit, first operational amplifier, second operational amplifier, third operational amplifier, fourth operational amplifier, noise band elimination filter and output filter capacitance, wherein: the first operational amplifier, the second operational amplifier, and the third operational amplifier are rail-to-rail differential input rail-to-rail differential output operational amplifiers, and the fourth operational amplifier is a rail-to-rail differential input rail-to-rail single-ended output operational amplifier, wherein: the first input end of the first chopper circuit is the first input end of the chopping operational amplifier COA, and the second input end of the first chopper circuit is the second input end of the chopping operational amplifier COA; the first operational amplifier has a first input terminal coupled to the first output terminal of the first chopper circuit and the first output terminal of the third operational amplifier, and has a second input terminal coupled to the second output terminal of the first chopper circuit and the second output terminal of the third operational amplifier; the first input end of the second chopper circuit is coupled with the first output end of the first operational amplifier, and the second input end of the second chopper circuit is coupled with the second output end of the first operational amplifier; the first input end of the second operational amplifier is coupled with the first output end of the second chopper circuit, and the second input end of the second operational amplifier is coupled with the second output end of the second chopper circuit; a first input terminal of the third chopper circuit is coupled to the first output terminal of the second operational amplifier, and a second input terminal of the third chopper circuit is coupled to the second output terminal of the second operational amplifier; the noise band elimination filter is coupled with a first input end and a second input end of the noise band elimination filter, and the first input end and the second input end of the noise band elimination filter are coupled with a first output end and a second output end of the third chopping circuit; the first input end of the third operational amplifier is coupled with the first output end of the noise band elimination filter, and the second input end of the third operational amplifier is coupled with the second output end of the noise band elimination filter; a first input end of the fourth operational amplifier is coupled to the first output end of the second chopper circuit, a second input end of the fourth operational amplifier is coupled to the second output end of the second chopper circuit, and an output end of the fourth operational amplifier is an output end of the chopper operational amplifier COA; the output filter capacitor is coupled between the second input end of the fourth operational amplifier and the output end of the fourth operational amplifier; the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter respectively comprise an enabling signal input end and a clock signal input end, the enabling signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter are coupled with the enabling signal input end of the chopping voltage average value feedback circuit, and the clock signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter are coupled with the clock signal input end of the chopping voltage average value feedback circuit.

Optionally, the chopping clock bootstrap circuit includes: a first programmable counter, a first D flip-flop, a second D flip-flop, and a first inverter, wherein: the first programmable counter has a clock signal input terminal coupled to the second output terminal of the stable clock output circuit, an enable signal input terminal coupled to the third output terminal of the stable clock output circuit, a control terminal to which a first control signal is input, and an output terminal coupled to the clock signal input terminal of the first D flip-flop; the data terminal of the first D flip-flop is coupled with the output terminal of the first inverter, the output terminal of the first D flip-flop is coupled with the input terminal of the first inverter, the clock signal input terminal of the second D flip-flop and the clock signal input terminal of the chopping voltage average value feedback circuit, and the enable terminal of the first D flip-flop is coupled with the third output terminal of the stable clock output circuit; and the data end of the second D trigger inputs preset power supply voltage, the output end of the second D trigger is coupled with the enabling signal input end of the chopping voltage average value feedback circuit, and the enabling end of the second D trigger is coupled with the third output end of the stable clock output circuit.

Optionally, the threshold voltage detection circuit includes: a first comparator and a second comparator, wherein: the first input end of the first comparator is coupled with the output end of the chopping voltage average value feedback circuit, the second input end of the first comparator is coupled with the second voltage output end of the RC charge-discharge circuit, and the output end of the first comparator is coupled with the first input end of the ESR trigger control circuit; and a first input end of the second comparator is coupled with the output end of the chopping voltage average value feedback circuit, a second input end of the second comparator is coupled with the third voltage output end of the RC charge-discharge circuit, and an output end of the second comparator is coupled with a second input end of the ESR trigger control circuit.

Optionally, the ESR trigger control circuit includes: first NAND gate, second NAND gate and buffer, wherein: a first input end of the first nand gate is coupled to the first output end of the threshold voltage detection circuit, an enable end of the first nand gate is coupled to the output end of the buffer, a second input end of the first nand gate is coupled to the output end of the second nand gate, and an output end of the first nand gate is a second output end of the ESR trigger control circuit; a first input end of the second nand gate is coupled to the second output end of the threshold voltage detection circuit, an enable end of the second nand gate is coupled to the input end of the buffer, a second input end of the second nand gate is coupled to the output end of the first nand gate, and an output end of the second nand gate is a first output end of the ESR trigger control circuit; the input end of the buffer inputs an enable signal, and the output end of the buffer is also coupled with the enable signal input end of the chopping clock bootstrap circuit.

Optionally, the stable clock output circuit includes: frequency stabilization indicating circuit, first AND gate and second AND gate, wherein: the input end of the frequency stability indicating circuit is coupled with the second output end of the ESR trigger control circuit, and the output end of the frequency stability indicating circuit is coupled with the first input end of the first AND gate, the first input end of the second AND gate and the enable signal input end of the chopper clock bootstrap circuit; a second input end of the first and gate is coupled to a second output end of the ESR trigger control circuit, and an output end of the first and gate outputs the first output clock signal; and a second input end of the second and gate is coupled to the first output end of the ESR trigger control circuit, and an output end of the second and gate outputs the second output clock signal.

Optionally, the frequency stabilization indicating circuit includes: a second programmable counter, a third D flip-flop, a fourth D flip-flop, and a second inverter, wherein: the enable signal input end of the second programmable counter inputs an enable signal, the clock signal input end of the second programmable counter is the input end of the frequency stabilization indicating circuit, the control end of the second programmable counter inputs a second control signal, and the output end of the second programmable counter is coupled with the clock signal input end of the third D flip-flop; the data terminal of the third D flip-flop is coupled with the output terminal of the second inverter, the output terminal of the third D flip-flop is coupled with the input terminal of the second inverter and the clock signal input terminal of the fourth D flip-flop, and the enable terminal of the third D flip-flop inputs the enable signal; the data end of the fourth D flip-flop inputs a preset power voltage, the output end of the fourth D flip-flop is the output end of the frequency stabilization indicating circuit, and the enable end of the fourth D flip-flop inputs the enable signal.

Optionally, the RC charging and discharging circuit includes: first adjustable resistance, second adjustable resistance, first adjustable electric capacity, second adjustable electric capacity and first switching circuit, second switching circuit, third switching circuit, fourth switching circuit, fifth switching circuit and sixth switching circuit, wherein: the first switch circuit has a moving end to which a power supply voltage is input, a fixed end coupled to the first end of the first adjustable resistor, and a control end coupled to the second output end of the ESR trigger control circuit; a second end of the first adjustable resistor is coupled to the moving end of the fifth switch circuit, the fixed end of the second switch circuit, and the first end of the first adjustable capacitor, and a second end of the first adjustable resistor is further coupled to a third input end of the threshold voltage detection circuit; the fixed end of the fifth switch circuit is coupled with the second end of the first adjustable capacitor, and the control end of the fifth switch circuit is coupled with the first output end of the ESR trigger control circuit; the second end of the first adjustable capacitor is coupled with the ground; the moving end of the second switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the second switch circuit is coupled with the second output end of the ESR trigger control circuit; the moving end of the third switch circuit is input with the power supply voltage, the fixed end of the third switch circuit is coupled with the first end of the second adjustable resistor, and the control end of the third switch circuit is coupled with the first output end of the ESR trigger control circuit; a second end of the second adjustable resistor is coupled to the moving end of the sixth switching circuit, the fixed end of the fourth switching circuit, and the first end of the second adjustable capacitor, and a second end of the second adjustable resistor is further coupled to a fourth input end of the threshold voltage detection circuit; the fixed end of the sixth switching circuit is coupled to the second end of the second tunable capacitor, and the control end of the sixth switching circuit is coupled to the second output end of the ESR trigger control circuit; the second end of the second adjustable capacitor is coupled with the ground; and the moving end of the fourth switching circuit is coupled with the first voltage output end of the RC charging and discharging circuit, and the control end of the fourth switching circuit is coupled with the first output end of the ESR trigger control circuit.

Optionally, the temperature drift calibration reference voltage is generated by a temperature drift calibration reference voltage generation circuit and is output via an output end of the temperature drift calibration reference voltage generation circuit.

Optionally, the temperature drift calibration reference voltage generating circuit includes: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance, fourth adjustable resistance, fifth adjustable resistance and the sixth adjustable resistance that establishes ties in proper order, wherein: a first output end of the PMOS current source is coupled to a second end of the fifth adjustable resistor and a first end of the sixth adjustable resistor; the input end of the first NMOS current source is coupled with the second output end of the PMOS current source, and the output end of the first NMOS current source is coupled with the input end of the PMOS current source; an input end of the second NMOS current source is coupled to a third output end of the PMOS current source, and an output end of the second NMOS current source is coupled to a first end of the fourth adjustable resistor and a second end of the third adjustable resistor; the first end of the third adjustable resistor is input with a power supply voltage, and the second end of the third adjustable resistor is coupled with the first end of the fourth adjustable resistor; a second end of the fourth adjustable resistor is coupled to the first end of the fifth adjustable resistor and the output end of the NMOS current source, and is coupled to the output end of the temperature drift calibration reference voltage generation circuit; a first end of the fifth adjustable resistor is coupled to the output end of the temperature drift calibration reference voltage generation circuit, and a second end of the fifth adjustable resistor is coupled to the first end of the sixth adjustable resistor and the output end of the PMOS current source; and the second end of the sixth adjustable resistor is grounded.

Optionally, the PMOS current source includes: first PMOS pipe, second PMOS pipe, third PMOS pipe and fourth PMOS pipe, wherein: the source electrode of the first PMOS tube is input with power supply voltage, the grid electrode of the first PMOS tube is coupled with the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is coupled with the input end of the first NMOS current source; the source electrode of the second PMOS tube is input with the power supply voltage, and the drain electrode and the grid electrode of the second PMOS tube are coupled with the output end of the first NMOS current source; the source electrode of the third PMOS tube inputs the power supply voltage, the grid electrode of the third PMOS tube is coupled with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the input end of the second NMOS current source; the source electrode of the fourth PMOS tube inputs the power supply voltage, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is a first output end of the PMOS current source.

Optionally, the first NMOS current source includes: first NMOS pipe, second NMOS pipe, first PNP triode, second PNP triode and current resistor, wherein: the grid electrode of the first NMOS tube is coupled with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is coupled with the emitting electrode of the first PNP triode, and the drain electrode of the first NMOS tube is the input end of the first NMOS current source; the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube is the output connection of the first NMOS current source, and the source electrode of the second NMOS tube is coupled with the first end of the current resistor; the second end of the current resistor is coupled with the emitter of the second PNP triode; the base electrode of the first PNP triode is coupled with the collector electrode of the first PNP triode and is grounded; and the base electrode of the second PNP triode is coupled with the collector electrode of the second PNP triode and is grounded.

Optionally, the second NMOS current source includes: third NMOS pipe and fourth NMOS pipe, wherein: the grid electrode of the third NMOS tube is coupled with the drain electrode of the third NMOS tube, the third NMOS tube is an input end of the second NMOS current source, and the source electrode of the third NMOS tube is grounded; and the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube is the output end of the second NMOS current source, and the source electrode of the fourth NMOS tube is grounded.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the temperature drift calibration reference voltage with a specific temperature coefficient is generated by the temperature drift calibration reference voltage generating circuit, and the frequency of the output clock is independent of the temperature and the voltage by matching with a chopping voltage average value feedback circuit with a self-calibration feedback loop.

Further, the integration loop in the chopping voltage average value feedback circuit can eliminate high-frequency noise, and the delay time of the comparator in the chopping operational amplifier can be eliminated through the integration loop. The chopping operational amplifier is provided with a self-calibration feedback loop, so that chopping noise can be suppressed while offset voltage and flicker noise are reduced, high-frequency phase noise of the oscillator can be suppressed by the negative feedback structure, and the sensitivity to high-frequency power supply noise is low.

In addition, the chopping clock bootstrap circuit realizes the clock bootstrap of the chopping operational amplifier, and can provide a clock signal with stable frequency.

Drawings

Fig. 1 is a schematic structural diagram of an oscillator in an embodiment of the present invention;

FIG. 2 is a schematic diagram of a chopper operational amplifier according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a frequency stability indicator circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure of a chopper clock bootstrap circuit in an embodiment of the present invention;

FIG. 5 is a schematic diagram of a temperature drift calibration reference voltage generating circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the transfer characteristics of the output noise of an integration loop in an embodiment of the present invention;

FIG. 7 is a schematic diagram of the transmission characteristics of an integral loop phase noise in an embodiment of the invention;

FIG. 8 is a diagram illustrating the output noise of a conventional operational amplifier according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of the output noise of a conventional chopping operational amplifier in an embodiment of the present invention;

FIG. 10 is a schematic diagram of the output noise of a chopper operational amplifier including a self-calibration feedback loop in an embodiment of the present invention;

fig. 11 is a schematic diagram of the output noise of a chopper mean value feedback circuit in the embodiment of the present invention.

Detailed Description

As can be seen from the above, the existing oscillator structures all use a comparator, and because the comparator has a delay, the error is small when the output frequency is low (for example, less than 1MHz), but when the output frequency exceeds 10MHz, the delay of the comparator changes with temperature and voltage, and the error of the output clock frequency is large.

In the embodiment of the invention, the temperature drift calibration reference voltage with a specific temperature coefficient is generated through the temperature drift calibration reference voltage, and the frequency of the output clock is independent of the temperature and the voltage by matching with a chopping voltage average value feedback circuit with a self-calibration feedback loop.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, an embodiment of the present invention provides an oscillator, including: the circuit comprises a chopping voltage average value feedback circuit 11, an RC charging and discharging circuit 12, a threshold voltage detection circuit 13, an ESR trigger control circuit 14, a stable clock output circuit 15, a chopping clock bootstrap circuit 16 and a temperature drift calibration reference voltage generation circuit 17.

In specific implementation, a temperature drift calibration reference voltage is input to a first input end of the chopping voltage average value feedback circuit 11, a second input end of the chopping voltage average value feedback circuit 11 is coupled to a first voltage output end of the RC charge-discharge circuit 12, a clock signal input end of the chopping voltage average value feedback circuit 11 is coupled to a clock signal output end of the chopping clock bootstrap circuit 16, and an enable signal input end of the chopping voltage average value feedback circuit 11 is coupled to an enable signal output end of the chopping clock bootstrap circuit 16;

a first input end and a second input end of the threshold voltage detection circuit 13 are both coupled with an output end of the chopper voltage average value feedback circuit 11, a third input end of the threshold voltage detection circuit 13 is coupled with a second voltage output end of the RC charge-discharge circuit 12, and a fourth input end of the threshold voltage detection circuit 13 is coupled with a third voltage output end of the RC charge-discharge circuit 12;

a first input terminal of the RC charging and discharging circuit 12 is coupled to a first output terminal of the ESR trigger control circuit 14, and a second input terminal of the RC charging and discharging circuit 12 is coupled to a second output terminal of the ESR trigger control circuit 14;

a first input terminal of the ESR trigger control circuit 14 is coupled to a first output terminal of the threshold voltage detection circuit 13, and a second input terminal of the ESR trigger control circuit 14 is coupled to a second output terminal of the threshold voltage detection circuit 13; the input end EN is input enable of the whole circuit and controls the opening and closing of the whole circuit.

A first input terminal of the stable clock output circuit 15 is coupled to a second output terminal of the ESR trigger control circuit 14, a second input terminal of the stable clock output circuit 15 is coupled to a first output terminal of the ESR trigger control circuit 14, a first output terminal of the stable clock output circuit 15 outputs a first output clock signal CLKOUTP, a second output terminal of the stable clock output circuit 15 outputs a second output clock signal CLKOUTN, and a third output terminal of the stable clock output circuit 15 outputs a clock stabilization indication signal CLKOK.

A clock signal input terminal of the chopping clock bootstrap circuit 16 is coupled to the second output terminal of the stable clock output circuit 15, and an enable signal input terminal of the chopping clock bootstrap circuit 16 is coupled to the third output terminal of the stable clock output circuit 15.

The specific structure of the oscillator described above will be described in detail below.

In a specific implementation, the chopping voltage average value feedback circuit 11 may include a chopping operational amplifier COA and an integration loop.

In the embodiment of the present invention, a temperature drift calibration reference voltage is input to a first input terminal of the chopping operational amplifier COA, a second input terminal of the chopping operational amplifier COA is coupled to an input terminal of the integrating circuit, and an output terminal of the chopping operational amplifier COA is coupled to an output terminal of the integrating circuit, a first input terminal of the threshold voltage detection circuit 13, and a second input terminal of the threshold voltage detection circuit 13.

The input of the integration circuit may also be coupled to a first voltage output of the RC charging and discharging circuit 12.

In a specific implementation, the integration loop may include an integration resistor Rx and an integration capacitor Cx, wherein:

a first end of the integrating resistor Rx is coupled with a first voltage output end of the RC charge-discharge circuit 12, and a second end of the integrating circuit is coupled with a first end of the integrating capacitor Cx and a second input end of the chopper operational amplifier COA; the second terminal of the integrating capacitor Cx is coupled to the output terminal of the chopping operational amplifier COA.

In a specific application, the first end of the integrating resistor Rx may be an input end of the integrating loop, and the second end of the integrating capacitor Cx may be an output end of the integrating loop.

In a specific implementation, the first input of the chopping operational amplifier COA may be its corresponding "+" input, and the second input of the chopping operational amplifier COA may be its corresponding "-" input.

It will be appreciated that in practical applications the structure of the integration loop is not limited to the above examples.

The chopping operational amplifier COA provided in the embodiment of the present invention is explained in detail below. Referring to fig. 2, a schematic structural diagram of a chopping operational amplifier COA in an embodiment of the present invention is shown.

In an embodiment of the present invention, the chopping operational amplifier COA may include a first chopper circuit CP1, a second chopper circuit CP2, a third chopper circuit CP3, a first operational amplifier a1, a second operational amplifier a2, a third operational amplifier A3, a fourth operational amplifier a4, a noise rejection filter NF, and an output filter capacitor Cc, wherein:

a first chopper circuit CP1, a first input end of which is a first input end of the chopper operational amplifier COA, and a second input end of which is a second input end of the chopper operational amplifier COA;

the first operational amplifier a1 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input terminal of the first operational amplifier a1 is coupled to a first output terminal of the first chopper circuit CP1 and a first output terminal of the third operational amplifier A3, a second input terminal of the first operational amplifier a1 is coupled to a second output terminal of the first chopper circuit CP1 and a second output terminal of the third operational amplifier A3;

a first input of a second chopper circuit CP2 is coupled to a first output of the first operational amplifier a1, and a second input of a second chopper circuit CP2 is coupled to a second output of the first operational amplifier a 1;

the second operational amplifier A2 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input terminal of the second operational amplifier A2 is coupled with a first output terminal of the second chopper circuit CP2, and a second input terminal of the second operational amplifier A2 is coupled with a second output terminal of the second chopper circuit CP 2;

a first input of a third chopper circuit CP3 is coupled to a first output of the second operational amplifier a2, and a second input of the third chopper circuit CP3 is coupled to a second output of the second operational amplifier a 2;

a first input end of the noise band elimination filter NF is coupled with a first output end of the third chopper circuit CP3, and a second input end of the noise band elimination filter NF is coupled with a second output end of the third chopper circuit CP 3;

the third operational amplifier A3 is a rail-to-rail differential input rail-to-rail differential output operational amplifier, a first input end of the third operational amplifier A3 is coupled with a first output end of the noise band elimination filter NF, and a second input end of the third operational amplifier A3 is coupled with a second output end of the noise band elimination filter NF;

a first input terminal of the fourth operational amplifier a4 is coupled to a first output terminal of the second chopper circuit CP2, a second input terminal of the fourth operational amplifier a4 is coupled to a second input terminal of the second chopper circuit CP2, and an output terminal of the fourth operational amplifier a4 is an output terminal of the chopper operational amplifier COA;

the output filter capacitor Cc is coupled between the second input terminal of the fourth operational amplifier a4 and the output terminal of the fourth operational amplifier a 4.

In the embodiment of the present invention, the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise rejection filter NF each include an enable signal input terminal and a clock signal input terminal, and: the enabling signal input ends of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3 and the noise band elimination filter NF are coupled with the enabling signal input end of the chopper voltage average value feedback circuit 11; clock signal input ends of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3 and the noise rejection filter NF are coupled to a clock signal input end of the chopper voltage average value feedback circuit 11.

In other words, the enable signals input to the enable signal input terminals of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise rejection filter NF are the enable signal a output from the enable signal output terminal of the chopper clock bootstrap circuit 16_en(ii) a The clock signals input to the clock signal input terminals of the first chopper circuit CP1, the second chopper circuit CP2, the third chopper circuit CP3, and the noise rejection filter NF are the clock signal A output from the clock signal output terminal of the chopper clock bootstrap circuit 16_clk。

In the embodiment of the present invention, the first input terminal of the first operational amplifier A1 is its "+" input terminal, the second input terminal of the first operational amplifier A1 is its "-" input terminal, the first output terminal of the first operational amplifier A1 is its "+" output terminal, and the second output terminal of the first operational amplifier A1 is its "-" output terminal.

Accordingly, for the second operational amplifier a2 and the third operational amplifier A3, the corresponding first input terminal is the "+" input terminal, the corresponding second input terminal is the "-" input terminal, the corresponding first output terminal is the "+" output terminal, and the corresponding second output terminal is the "-" output terminal.

For the fourth operational amplifier A4, its first input is its "+" input and its second input is its "-" input.

In fig. 2, the first input terminal of the chopping operational amplifier COA is INP, the second input terminal of the chopping operational amplifier COA is INN, and the output terminal of the chopping operational amplifier COA is Vout. In essence, when the chopping operational amplifier COA in FIG. 2 is applied to FIG. 1, the INP port is the "+" input terminal of the chopping operational amplifier COA, and the INN port isIs the input end of a chopping operational amplifier COA, wherein the voltage output by a Vout port is V_Y。

The chopping operational amplifier COA with the structure internally comprises a self-calibration feedback loop, so that chopping ripples can be filtered. At low frequency, flicker noise and offset voltage can be removed, and high frequency noise can be filtered by a coupled integrating loop, so that the jitter of the output clock signal is small.

Referring to fig. 1, in the embodiment of the present invention, the RC charging and discharging circuit 12 may include a first adjustable resistor R1, a second adjustable resistor R2, a first adjustable capacitor C1, a second adjustable capacitor C2, a first switch circuit K1, a second switch circuit K2, a third switch circuit K3, a fourth switch circuit K4, a fifth switch circuit K5, and a sixth switch circuit K6, wherein:

the moving end of the first switch circuit K1 inputs the power voltage VDD, the fixed end of the first switch circuit K1 is coupled to the first end of the first adjustable resistor R1, and the control end of the first switch circuit K1 is coupled to the second output end of the ESR trigger control circuit 14;

a second end of the first adjustable resistor R1 is coupled to the moving end of the fifth switch circuit K5, the fixed end of the second switch circuit K2, and the first end of the first adjustable capacitor C1, and a second end of the first adjustable resistor R1 is further coupled to the third input terminal of the threshold voltage detection circuit 13; in other words, the second terminal of the first adjustable resistor R1 may be a second voltage output terminal of the RC charging and discharging circuit 12;

a fixed terminal of the fifth switch circuit K5 is coupled to the second terminal of the first adjustable capacitor C1, and a control terminal of the fifth switch circuit K5 is coupled to the first output terminal of the ESR trigger control circuit 14;

the second end of the first adjustable capacitor C1 is grounded, and the fixed end of the fifth switch circuit K5 is also grounded;

the moving terminal of the second switch circuit K2 is coupled to the first voltage output terminal of the RC charging and discharging circuit 12, and the control terminal of the second switch circuit K2 is coupled to the second output terminal of the ESR trigger control circuit 14;

the movable end of the third switch circuit K3 inputs the power voltage VDD, the fixed end of the third switch circuit K3 is coupled to the first end of the second adjustable resistor R2, and the control end of the third switch circuit K3 is coupled to the first output end of the ESR trigger control circuit 14;

a second end of the second adjustable resistor R2 is coupled to the moving end of the sixth switch circuit K6, the fixed end of the fourth switch circuit K4, and the first end of the second adjustable capacitor C2, and a second end of the second adjustable resistor R2 is further coupled to the fourth input end of the threshold voltage detection circuit 13; in other words, the second end of the second adjustable resistor R2 may be the third voltage output end of the RC charging and discharging circuit 12;

a fixed terminal of the sixth switching circuit K6 may be coupled to the second terminal of the second adjustable capacitor C2, and a control terminal of the sixth switching circuit K6 is coupled to the second output terminal of the ESR trigger control circuit 14;

a second terminal of the second adjustable capacitor C2 is coupled to ground, and a second terminal of the sixth switching circuit K6 is also coupled to ground;

the moving terminal of the fourth switching circuit K4 is coupled to the first voltage output terminal of the RC charging/discharging circuit 12, and the control terminal of the fourth switching circuit K4 is coupled to the first output terminal of the ESR trigger control circuit 14.

In the embodiment of the present invention, the RC charging and discharging circuit 12 may be equivalent to a voltage-controlled oscillator using the output voltage of the chopper voltage average value feedback circuit 11 as a control signal. The voltage of the fixed terminal of the second switch circuit K2 and the voltage of the fixed terminal of the fourth switch circuit K4 are combined into a voltage output via the first voltage output terminal of the RC charging and discharging circuit 12, and input to the chopper voltage average value feedback circuit 11. Due to the virtual short and virtual break characteristics, the voltage output from the first voltage output terminal of the RC charging/discharging circuit 12 is maintained at the temperature drift calibration reference voltage V_REFNearby.

Referring to fig. 1, the output V from the chopper voltage average value feedback circuit 11_YThe RC charging and discharging circuit 12 is indirectly controlled as a control signal. Voltage V at fixed end of second switch circuit K2_O1And the voltage V of the fixed end of the fourth switching circuit K4_O2Synthesis into V_XAnd input to the second input terminal of the chopper operational amplifier COA via the integrating resistor Rx. Due to the virtual short-break characteristic, V_XIs maintained at V_REFNearby.

Referring to fig. 1, in a specific implementation, the threshold voltage detection circuit 13 may include: a first comparator RCP1 and a second comparator RCP2, wherein:

a first input terminal of the first comparator RCP1 is coupled to the output terminal of the chopping voltage average value feedback circuit 11, a second input terminal of the first comparator RCP1 is coupled to the second voltage output terminal of the RC charging and discharging circuit 12, and an output terminal of the first comparator RCP1 is coupled to the first input terminal of the ESR trigger control circuit 14;

a first input of a second comparator RCP2 is coupled to the output of the chopping voltage average feedback circuit 11, a second input of the second comparator RCP2 is coupled to the third voltage output of the RC charging and discharging circuit 12, and an output of the second comparator RCP2 is coupled to a second input of the ESR trigger control circuit 14.

In an embodiment of the present invention, the first input terminal of the first comparator RCP1 may be a first input terminal of the threshold voltage detection circuit 13, the second input terminal of the first comparator RCP1 may be a second input terminal of the threshold voltage detection circuit 13, and the output terminal of the first comparator RCP1 may be a first output terminal of the threshold voltage detection circuit 13.

The first input terminal of the second comparator RCP2 may be a third input terminal of the threshold voltage detection circuit 13, the second input terminal of the second comparator RCP2 may be a fourth input terminal of the threshold voltage detection circuit 13, and the output terminal of the second comparator RCP2 may be a second output terminal of the threshold voltage detection circuit 13.

In a specific implementation, the first comparator RCP1 and the second comparator RCP2 are complementary rail-to-rail input comparators.

In a specific implementation, the ESR trigger control circuit 14 comprises: a first NAND gate NAND1, a second NAND gate NAND2, and a buffer BUF, wherein:

a first input terminal of the first NAND gate NAND1 is coupled to the first output terminal of the threshold voltage detection circuit 13, an enable terminal of the first NAND gate NAND1 is coupled to the output terminal of the buffer BUF, and a second input terminal of the first NAND gate NAND1 is coupled to the output terminal of the second NAND gate NAND 2; the output of the first NAND gate NAND1 is a second output CLKN of the ESR trigger control circuit 14;

a first input terminal of the second NAND gate NAND2 is coupled to the second output terminal of the threshold voltage detection circuit 13, an enable terminal of the second NAND gate NAND2 is coupled to the input terminal of the buffer BUF, a second input terminal of the second NAND gate NAND2 is coupled to the output terminal of the first NAND gate NAND1, and the output terminal of the second NAND gate NAND2 is the first output terminal CLKP of the ESR trigger control circuit 14.

The buffer BUF realizes a delay of ns level when EN is enabled, thereby ensuring that the ESR trigger control circuit enters a normal working state.

In a specific implementation, the stable clock output circuit 15 may include: frequency stability indicating circuit 151, first AND gate AND1, AND second AND gate AND2, wherein:

an input terminal of the frequency stability indicating circuit 151 is coupled to the second output terminal of the ESR trigger control circuit 14, AND an output terminal of the frequency stability indicating circuit 151 is coupled to a first input terminal of a first AND gate AND1, a first input terminal of a second AND gate AND2, AND an enable signal input terminal of the chopper clock bootstrap circuit 16;

a second input terminal of the first AND gate AND1 is coupled to a second output terminal of the ESR trigger control circuit 14, AND an output terminal of the first AND gate AND1 outputs the first output clock signal CLKOUTP;

a second input terminal of the second AND gate AND2 is coupled to a first output terminal of the ESR trigger control circuit 14, AND an output terminal of the second AND gate AND2 outputs the second output clock signal CLKOUTN.

In the embodiment of the present invention, the input terminal of the frequency stability indicating circuit 151 may be a first input terminal CLKN of the stability clock output circuit 15; a second input terminal of the second AND gate AND2 may be a second input terminal CLKP of the stabilization clock output circuit 15; the output terminal of the frequency stability indicating circuit 151 may be a third output terminal of the stability clock output circuit 15, and is configured to output a clock stability indicating signal CLKOK;

the output terminal of the first AND gate AND1 may be a first output terminal of the stable clock output circuit 15 for outputting the first output clock signal CLKOUTP;

the output terminal of the second AND gate AND2 may be a second output terminal of the stable clock output circuit 15 for outputting the second output clock signal CLKOUTN.

Referring to fig. 3, a schematic diagram of a frequency stability indicator 151 according to an embodiment of the present invention is shown.

In a specific implementation, the frequency stability indication circuit 151 may include: a second programmable counter, a third D flip-flop D3, a fourth D flip-flop D4, and a second inverter INV2, wherein:

the enable signal EN is input to the enable signal input terminal of the second programmable counter, the clock signal input terminal of the second programmable counter is the input terminal of the frequency stabilization indicating circuit 151, and the control terminal of the second programmable counter inputs the second control signal F < 15: 0>, the output of the second programmable counter is coupled to the clock signal input of the third D flip-flop D3;

a data terminal D of the third D flip-flop D3 is coupled to an output terminal of the second inverter INV2, an output terminal Q of the third D flip-flop D3 is coupled to an input terminal of the second inverter INV2 and a clock signal input terminal of the fourth D flip-flop D4, and a reset terminal of the third D flip-flop D3 receives an enable signal EN;

the data terminal D of the fourth D flip-flop D4 inputs the preset power voltage VDD, the output terminal Q of the fourth D flip-flop D4 is the output terminal of the frequency stabilization indicating circuit 151, and the reset terminal input of the fourth D flip-flop D4 is the enable signal EN.

In the embodiment of the present invention, the second programmable counter may be a 16-bit programmable counter, in which the second control signal F is inputted<15:0>The number of clock cycles of the clock stabilization indication signal CLKOK is output for delay. For 16 programmable counters, the corresponding delay time ranges from 0 to 2¹⁶-1 cycle.

For example, if the second control signal is 0x0003, the clock stabilization indication signal CLKOK is output to the chopper clock bootstrap circuit 16 after delaying for 3 cycles.

Referring to fig. 4, a schematic diagram of a structure of the chopper clock bootstrap circuit 16 in the embodiment of the present invention is shown.

In a specific implementation, the chopping clock bootstrap circuit 16 may include a first programmable counter, a first D flip-flop D1, a second D flip-flop, and a first inverter INV1, wherein:

the first clock signal input end of the first programmable counter is a second output clock signal CLKOTN, the enable signal input end of the first programmable counter is a clock stabilization indicating signal CLKOK, the control end of the first programmable counter inputs a first control signal, and the output end of the first programmable counter is coupled with the clock signal input end of a first D flip-flop D1;

a data end D of the first D flip-flop D1 is coupled to an output end of the first inverter INV1, an output end Q of the first D flip-flop D1 is coupled to an input end of the first inverter INV1, a clock signal input end of the second D flip-flop D2 and a clock signal input end of the chopper voltage average value feedback circuit 11, and a reset end of the first D flip-flop inputs the clock stabilization indication signal CLKOK;

the data terminal D of the second D flip-flop D2 inputs a preset power voltage VDD, the output terminal Q of the second D flip-flop D2 is coupled to the enable signal input terminal of the chopper voltage average value feedback circuit 11, and the reset terminal of the second D flip-flop D2 inputs a clock stabilization indication signal CLKOK.

In this embodiment of the present invention, the first clock signal input terminal of the first programmable counter may be a clock signal input terminal of the chopper clock bootstrap circuit 16, the enable signal input terminal of the first programmable counter may be an enable signal input terminal of the chopper clock bootstrap circuit 16, the output terminal Q of the first D flip-flop D1 may be a clock signal output terminal of the chopper clock bootstrap circuit 16, and the output clock signal a is output_clk(ii) a The output end Q of the second D flip-flop D2 may be an enable signal output end of the chopping clock bootstrap circuit 16, and outputs an enable signal a_en。

In one embodiment, the first programmable counter may be a 64-bit programmable counter, wherein the input first control signal (C <63:0>) is a frequency dividing ratio for dividing the input second output clock signal CLKOUTN.

In a specific implementation, the temperature drift calibration reference voltage may be generated by the temperature drift calibration reference voltage generation circuit 17.

Referring to fig. 5, a schematic structural diagram of a temperature drift calibration reference voltage generating circuit 17 in the embodiment of the present invention is shown.

In the embodiment of the present invention, the temperature drift calibration reference voltage generation circuit 17 may include: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance R3, fourth adjustable resistance R4, fifth adjustable resistance R5 and sixth adjustable resistance R6 that series connection in proper order, wherein:

a first output terminal of the PMOS current source is coupled to a second terminal of the fifth adjustable resistor R5 and a first terminal of the sixth adjustable resistor R6;

the input end of the first NMOS current source is coupled with the second output end of the PMOS current source, and the output end of the first NMOS current source is coupled with the input end of the PMOS current source;

an output end of the second NMOS current source is coupled to a first end of the fourth adjustable resistor R4 and a second end of the third adjustable resistor R3;

a third adjustable resistor R3, a first terminal of which is inputted with the power voltage, and a second terminal of which is coupled with the first terminal of the fourth adjustable resistor R4;

a second end of the fourth adjustable resistor R4 is coupled to the first end of the fifth adjustable resistor R5 and the output end of the NMOS current source, and is coupled to the output end of the temperature drift calibration reference voltage generation circuit;

a first end of the fifth adjustable resistor R5 is coupled to the output end of the temperature drift calibration reference voltage generation circuit, and a second end of the fifth adjustable resistor R5 is coupled to the first end of the sixth adjustable resistor R6 and the output end of the PMOS current source;

and a second end of the sixth adjustable resistor R6 is grounded.

In a specific implementation, the PMOS current source may include: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, wherein:

a first PMOS transistor MP1, having a source to which a power voltage is input, a gate coupled to the gate of the second PMOS transistor MP2 and the drain of the second PMOS transistor MP2, and a drain coupled to the input of the first NMOS current source;

a second PMOS transistor MP2, having a source to which a power voltage is input, and a drain and a gate coupled to an output of the first NMOS current source;

a third PMOS transistor MP3, having a source to which a power voltage is input, a gate coupled to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2, and a drain coupled to the input of the second NMOS current source;

the source of the fourth PMOS transistor MP4 receives the power voltage, the gate thereof is coupled to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the gate of the third PMOS transistor MP3, and the drain thereof is the first output terminal of the PMOS current source.

In a specific implementation, the first NMOS current source may include: a first NMOS transistor MN1, a second NMOS transistor MN2, a first PNP triode Q1, a second PNP triode Q2 and a current resistor R_PTATWherein:

a first NMOS transistor MN1, having a gate coupled to a drain thereof, a source coupled to an emitter of the first PNP transistor Q1, and a drain of the first NMOS transistor MN1 serving as an input of the first NMOS current source;

a second NMOS transistor MN2 having a gate coupled to the gate of the first NMOS transistor MN1, a drain connected to the output of the first NMOS current source, a source connected to the current resistor R_PTATIs coupled with the first end of the first switch;

current resistor R_PTATA second terminal of the second PNP transistor Q2 is coupled to the emitter thereof;

a first PNP transistor Q1 having its base coupled to its collector and both grounded;

a second PNP transistor Q2 has its base coupled to its collector and both grounded.

In a specific implementation, the second NMOS current source may include: a third NMOS transistor MN3 and a fourth NMOS transistor MN4, wherein:

a third NMOS transistor MN3, having a gate coupled to a drain thereof, serving as an input terminal of the second NMOS current source, and a source grounded; a gate of the fourth NMOS transistor MN4 is coupled to the gate of the third NMOS transistor MN3, a drain of the fourth NMOS transistor MN4 is the output terminal of the second NMOS current source, and a source of the fourth NMOS transistor MN4 is grounded.

It is to be understood that the specific structure of the PMOS current source may not be limited to the above example, and the specific structure of the NMOS current source may not be limited to the above example.

In the embodiment of the present invention, the temperature drift coefficient of the temperature drift calibration reference voltage output by the temperature drift calibration reference voltage generation circuit 17 can be adjusted by adjusting the resistance values of the third to sixth adjustable resistors and the number ratio of the first PNP transistor to the second PNP transistor, so that the output frequency of the temperature drift calibration reference voltage is adjusted to be independent of the temperature.

The operation of the oscillator provided in the above-described embodiment of the present invention will be described in detail.

Temperature drift calibration reference voltage V_REFThe voltage division ratio is alpha, alpha is VDD/V_REF。V_REFThe voltage division ratio and the first adjustable resistor, the second adjustable resistor, the first adjustable capacitor and the second adjustable capacitor in the RC charging and discharging circuit 12 determine the frequency of the output clock signal. In the chopper voltage average value feedback circuit 11, the integration capacitance Cx and the integration resistance Rx of the integration loop determine the noise performance of the output clock signal.

The RC charge and discharge circuit 12 may be equivalently composed of V_YA voltage controlled oscillator as a control signal.

According to the virtual short and the virtual break of the chopping operational amplifier COA, the integral loop is solved to obtain:

the integration on both sides of the above equation (2.1) can be obtained:

the above formula (2.2) is simplified to obtain:

v in the above equation (2.3) when the oscillator is in a steady state_Y(0) The steady-state dc component of the output is determined, and the ac component is 0, so:

the above formula (2.4) is simplified to obtain:

when there is a periodic steady state with a period of T,

thus, a relationship between the steady state integration period and the temperature drift calibration reference voltage is established. As can be seen from the above equation (2.6), the steady-state integration period of the integration loop is independent of the electrical parameters of the integration resistor Rx and the electrical parameters of the integration capacitor Cx.

Because the first adjustable resistor and the second adjustable resistor in the RC charging and discharging circuit 12 directly input the power voltage, the first adjustable capacitor and the second adjustable capacitor are grounded, and then:

V_O1,2(t)＝Vdd(1-e^-t/RC) (2.7) in the chopper voltage average value feedback circuit 11, there are

Substituting the above formula (2.7) into the above formula (2.8), and simplifying to obtain:

r in the above equation (2.9) refers to resistance values of the first adjustable resistor and the second adjustable resistor in the RC charging and discharging circuit 12, and C refers to capacitance values of the first adjustable capacitor and the second adjustable capacitor in the RC charging and discharging circuit 12.

The chopper voltage average value feedback circuit 11 realizes the condition in the above expression (2.9), and mayTo automatically adjust V_YTo maintain a stable frequency output and thus insensitive to the supply voltage VDD and propagation delay. After the voltage division ratio is set, the electrical parameters of the first adjustable resistor, the first adjustable capacitor, the second adjustable resistor and the second adjustable capacitor can be adjusted to obtain a specific output frequency.

As mentioned above, RC charge/discharge circuit 12 can be equivalent to a voltage controlled oscillator, which is defined by a frequency gain K_VCOVn represents the noise spectrum contributed by the chopping operational amplifier COA and other devices, and the period integral of Vx is equal to the input voltage Vx multiplied by the process-related proportionality coefficient beta of the chopping operational amplifier COA. Since the chopping characteristic of the chopping operational amplifier COA is in the loop, its noise is filtered out by its self-calibration feedback loop.

The output noise of the integration loop is:

the phase noise of the integrating loop is:

where A is the gain of the chopper operational amplifier COA and s is the Laplacian coefficient, (. phi.) in (2.11)_nIs the system phase noise spectrum.

The pole zero is as follows:

wherein f is_zIs the first zero point, f_p1Is the first pole, f_p2The second pole.

The transmission characteristics of the integration loop output noise are shown in fig. 6, and the transmission characteristics of the phase noise are shown in fig. 7. In fig. 6, the abscissa is logarithmic frequency log (freq), and the ordinate is output noise transmission characteristic Φ_outand/Vn. In FIG. 7, the abscissaLog (freq) of logarithmic frequency, and ordinate of transmission characteristic phi of phase noise_out/φ_n. The output noise is small at high frequencies.

As can be seen from fig. 6, the output noise of the integration loop drops sharply after the frequency exceeds the second pole. As can be seen from fig. 7, the phase noise increases with frequency when the frequency is between the first zero and the second pole. At frequencies less than the second pole, the phase noise is stable and less at low frequencies.

Referring to fig. 8, an output noise diagram of a general operational amplifier is shown. Referring to fig. 9, an output noise diagram of a common chopping operational amplifier COA is given. Referring to fig. 10, an output noise schematic of a chopping operational amplifier COA including a self-calibration feedback loop is presented. Referring to fig. 11, an output noise diagram of the chopper voltage average value feedback circuit 11 in the embodiment of the present invention is shown.

In fig. 8 to 11, the abscissa represents logarithmic frequency log (freq), and the ordinate represents noise coefficient NF, f_cThe chopping frequency of the circuit is fed back to the average value of the chopping voltage.

As can be seen from fig. 8 to 11, the output noise of the chopper voltage average value feedback circuit provided in the embodiment of the present invention is free from flicker noise and includes only the cutoff frequency f_p2Low pass thermal noise.

Therefore, the chopper voltage average value feedback circuit provided in the embodiment of the present invention can suppress phase noise at a low frequency in the RC charging/discharging circuit 12, and can use small-sized transistors in the first comparator and the second comparator to reduce power consumption. In the chopping voltage average value feedback circuit, the flicker noise of the chopping operational amplifier COA can be filtered by the feedback loop, so that the chopping operational amplifier COA with a small size can be selected to reduce the circuit area. High frequency noise is eliminated and thus sensitivity to high frequency noise is low.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An oscillator, comprising: chopper voltage average value feedback circuit, RC charge-discharge circuit, threshold voltage detection circuit, ESR trigger control circuit, stable clock output circuit and chopper clock bootstrap circuit, wherein:

a first input end of the chopping voltage average value feedback circuit inputs a temperature drift calibration reference voltage, a second input end of the chopping voltage average value feedback circuit is coupled with a first voltage output end of the RC charge-discharge circuit, a clock signal input end of the chopping voltage average value feedback circuit is coupled with a clock signal output end of the chopping clock bootstrap circuit, and an enable signal input end of the chopping voltage average value feedback circuit is coupled with an enable signal output end of the chopping clock bootstrap circuit;

a first input end and a second input end of the threshold voltage detection circuit are both coupled with an output end of the chopping voltage average value feedback circuit, a third input end of the threshold voltage detection circuit is coupled with a second voltage output end of the RC charge-discharge circuit, and a fourth input end of the threshold voltage detection circuit is coupled with a third voltage output end of the RC charge-discharge circuit;

the first input end of the RC charge-discharge circuit is coupled with the first output end of the ESR trigger control circuit, and the second input end of the RC charge-discharge circuit is coupled with the second output end of the ESR trigger control circuit;

the first input end of the ESR trigger control circuit is coupled with the first output end of the threshold voltage detection circuit, the second input end of the ESR trigger control circuit is coupled with the second output end of the threshold voltage detection circuit, and the third input end of the ESR trigger control circuit inputs an enabling signal;

the first input end of the stable clock output circuit is coupled with the second output end of the ESR trigger control circuit, the second input end of the stable clock output circuit is coupled with the first output end of the ESR trigger control circuit, the first output end of the stable clock output circuit outputs a first output clock signal, the second output end of the stable clock output circuit outputs a second output clock signal, and the third output end of the stable clock output circuit outputs a clock stability indicating signal;

and the chopping clock bootstrap circuit is provided with a clock signal input end coupled with the second output end of the stable clock output circuit, and an enable signal input end coupled with the third output end of the stable clock output circuit.

2. The oscillator of claim 1, wherein the chopped voltage average feedback circuit comprises: a chopping operational amplifier COA and an integrating loop, wherein:

the first input end of the chopping operational amplifier COA inputs the temperature drift calibration reference voltage, the second input end of the chopping operational amplifier COA is coupled with the input end of the integrating circuit, and the output end of the chopping operational amplifier COA is coupled with the output end of the integrating circuit, the first input end of the threshold voltage detection circuit and the second input end of the threshold voltage detection circuit;

and the input end of the integration loop is coupled with the first voltage output end of the RC charge-discharge circuit.

3. The oscillator of claim 2, wherein the integration loop comprises an integration resistor Rx and an integration capacitor Cx, wherein:

the first end of the integrating resistor Rx is coupled with the first voltage output end of the RC charge-discharge circuit, and the second end of the integrating resistor Rx is coupled with the first end of the integrating capacitor Cx and the second input end of the chopping operational amplifier COA;

and a second end of the integrating capacitor Cx is coupled to the output end of the chopping operational amplifier COA.

4. The oscillator according to claim 2, characterized in that the chopping operational amplifier COA comprises: first chopper circuit, second chopper circuit, third chopper circuit, first operational amplifier, second operational amplifier, third operational amplifier, fourth operational amplifier, noise band elimination filter and output filter capacitance, wherein: the first operational amplifier, the second operational amplifier, and the third operational amplifier are rail-to-rail differential input rail-to-rail differential output operational amplifiers, and the fourth operational amplifier is a rail-to-rail differential input rail-to-rail single-ended output operational amplifier, wherein:

the first input end of the first chopper circuit is the first input end of the chopping operational amplifier COA, and the second input end of the first chopper circuit is the second input end of the chopping operational amplifier COA;

the first operational amplifier has a first input terminal coupled to the first output terminal of the first chopper circuit and the first output terminal of the third operational amplifier, and has a second input terminal coupled to the second output terminal of the first chopper circuit and the second output terminal of the third operational amplifier;

the first input end of the second chopper circuit is coupled with the first output end of the first operational amplifier, and the second input end of the second chopper circuit is coupled with the second output end of the first operational amplifier;

the first input end of the second operational amplifier is coupled with the first output end of the second chopper circuit, and the second input end of the second operational amplifier is coupled with the second output end of the second chopper circuit;

a first input terminal of the third chopper circuit is coupled to the first output terminal of the second operational amplifier, and a second input terminal of the third chopper circuit is coupled to the second output terminal of the second operational amplifier;

the noise band elimination filter is coupled with a first input end and a second input end of the noise band elimination filter, and the first input end and the second input end of the noise band elimination filter are coupled with a first output end and a second output end of the third chopping circuit;

the first input end of the third operational amplifier is coupled with the first output end of the noise band elimination filter, and the second input end of the third operational amplifier is coupled with the second output end of the noise band elimination filter;

a first input end of the fourth operational amplifier is coupled to the first output end of the second chopper circuit, a second input end of the fourth operational amplifier is coupled to the second output end of the second chopper circuit, and an output end of the fourth operational amplifier is an output end of the chopper operational amplifier COA;

the output filter capacitor is coupled between the second input end of the fourth operational amplifier and the output end of the fourth operational amplifier;

the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter respectively comprise an enabling signal input end and a clock signal input end, the enabling signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter are coupled with the enabling signal input end of the chopping voltage average value feedback circuit, and the clock signal input ends of the first chopper circuit, the second chopper circuit, the third chopper circuit and the noise band elimination filter are coupled with the clock signal input end of the chopping voltage average value feedback circuit.

5. The oscillator of claim 1, wherein the chopping clock bootstrap circuit comprises: a first programmable counter, a first D flip-flop, a second D flip-flop, and a first inverter, wherein: the first programmable counter has a clock signal input terminal coupled to the second output terminal of the stable clock output circuit, an enable signal input terminal coupled to the third output terminal of the stable clock output circuit, a control terminal to which a first control signal is input, and an output terminal coupled to the clock signal input terminal of the first D flip-flop;

the data terminal of the first D flip-flop is coupled with the output terminal of the first inverter, the output terminal of the first D flip-flop is coupled with the input terminal of the first inverter, the clock signal input terminal of the second D flip-flop and the clock signal input terminal of the chopping voltage average value feedback circuit, and the enable terminal of the first D flip-flop is coupled with the third output terminal of the stable clock output circuit;

and the data end of the second D trigger inputs preset power supply voltage, the output end of the second D trigger is coupled with the enabling signal input end of the chopping voltage average value feedback circuit, and the enabling end of the second D trigger is coupled with the third output end of the stable clock output circuit.

6. The oscillator of claim 1, wherein the threshold voltage detection circuit comprises: a first comparator and a second comparator, wherein:

the first input end of the first comparator is coupled with the output end of the chopping voltage average value feedback circuit, the second input end of the first comparator is coupled with the second voltage output end of the RC charge-discharge circuit, and the output end of the first comparator is coupled with the first input end of the ESR trigger control circuit;

and a first input end of the second comparator is coupled with the output end of the chopping voltage average value feedback circuit, a second input end of the second comparator is coupled with the third voltage output end of the RC charge-discharge circuit, and an output end of the second comparator is coupled with a second input end of the ESR trigger control circuit.

7. The oscillator of claim 1, wherein the ESR trigger control circuit comprises: first NAND gate, second NAND gate and buffer, wherein:

a first input end of the first nand gate is coupled to the first output end of the threshold voltage detection circuit, an enable end of the first nand gate is coupled to the output end of the buffer, a second input end of the first nand gate is coupled to the output end of the second nand gate, and an output end of the first nand gate is a second output end of the ESR trigger control circuit;

a first input end of the second nand gate is coupled to the second output end of the threshold voltage detection circuit, an enable end of the second nand gate is coupled to the input end of the buffer, a second input end of the second nand gate is coupled to the output end of the first nand gate, and an output end of the second nand gate is a first output end of the ESR trigger control circuit;

the input end of the buffer inputs an enable signal, and the output end of the buffer is also coupled with the enable signal input end of the chopping clock bootstrap circuit.

8. The oscillator of claim 1, wherein the stable clock output circuit comprises: frequency stabilization indicating circuit, first AND gate and second AND gate, wherein:

the input end of the frequency stability indicating circuit is coupled with the second output end of the ESR trigger control circuit, and the output end of the frequency stability indicating circuit is coupled with the first input end of the first AND gate, the first input end of the second AND gate and the enable signal input end of the chopper clock bootstrap circuit;

a second input end of the first and gate is coupled to a second output end of the ESR trigger control circuit, and an output end of the first and gate outputs the first output clock signal;

and a second input end of the second and gate is coupled to the first output end of the ESR trigger control circuit, and an output end of the second and gate outputs the second output clock signal.

9. The oscillator of claim 8, wherein the frequency stability indication circuit comprises: a second programmable counter, a third D flip-flop, a fourth D flip-flop, and a second inverter, wherein: the enable signal input end of the second programmable counter inputs an enable signal, the clock signal input end of the second programmable counter is the input end of the frequency stabilization indicating circuit, the control end of the second programmable counter inputs a second control signal, and the output end of the second programmable counter is coupled with the clock signal input end of the third D flip-flop;

the data terminal of the third D flip-flop is coupled with the output terminal of the second inverter, the output terminal of the third D flip-flop is coupled with the input terminal of the second inverter and the clock signal input terminal of the fourth D flip-flop, and the enable terminal of the third D flip-flop inputs the enable signal;

the data end of the fourth D flip-flop inputs a preset power voltage, the output end of the fourth D flip-flop is the output end of the frequency stabilization indicating circuit, and the enable end of the fourth D flip-flop inputs the enable signal.

10. The oscillator of claim 1, wherein the RC charging and discharging circuit comprises: first adjustable resistance, second adjustable resistance, first adjustable electric capacity, second adjustable electric capacity and first switching circuit, second switching circuit, third switching circuit, fourth switching circuit, fifth switching circuit and sixth switching circuit, wherein:

the first switch circuit has a moving end to which a power supply voltage is input, a fixed end coupled to the first end of the first adjustable resistor, and a control end coupled to the second output end of the ESR trigger control circuit;

a second end of the first adjustable resistor is coupled to the moving end of the fifth switch circuit, the fixed end of the second switch circuit, and the first end of the first adjustable capacitor, and a second end of the first adjustable resistor is further coupled to a third input end of the threshold voltage detection circuit;

the fixed end of the fifth switch circuit is coupled with the second end of the first adjustable capacitor, and the control end of the fifth switch circuit is coupled with the first output end of the ESR trigger control circuit;

the second end of the first adjustable capacitor is coupled with the ground;

the moving end of the second switch circuit is coupled with the first voltage output end of the RC charge-discharge circuit, and the control end of the second switch circuit is coupled with the second output end of the ESR trigger control circuit;

the moving end of the third switch circuit is input with the power supply voltage, the fixed end of the third switch circuit is coupled with the first end of the second adjustable resistor, and the control end of the third switch circuit is coupled with the first output end of the ESR trigger control circuit;

a second end of the second adjustable resistor is coupled to the moving end of the sixth switching circuit, the fixed end of the fourth switching circuit, and the first end of the second adjustable capacitor, and a second end of the second adjustable resistor is further coupled to a fourth input end of the threshold voltage detection circuit;

the fixed end of the sixth switching circuit is coupled to the second end of the second tunable capacitor, and the control end of the sixth switching circuit is coupled to the second output end of the ESR trigger control circuit;

the second end of the second adjustable capacitor is coupled with the ground;

and the moving end of the fourth switching circuit is coupled with the first voltage output end of the RC charging and discharging circuit, and the control end of the fourth switching circuit is coupled with the first output end of the ESR trigger control circuit.

11. The oscillator according to claim 1, wherein the temperature drift calibration reference voltage is generated by a temperature drift calibration reference voltage generation circuit and output via an output terminal of the temperature drift calibration reference voltage generation circuit.

12. The oscillator of claim 11, wherein the temperature drift calibration reference voltage generation circuit comprises: PMOS current source, first NMOS current source, second NMOS current source to and third adjustable resistance, fourth adjustable resistance, fifth adjustable resistance and the sixth adjustable resistance that establishes ties in proper order, wherein:

a first output end of the PMOS current source is coupled to a second end of the fifth adjustable resistor and a first end of the sixth adjustable resistor;

an output end of the second NMOS current source is coupled to a first end of the fourth adjustable resistor and a second end of the third adjustable resistor;

the first end of the third adjustable resistor is input with a power supply voltage, and the second end of the third adjustable resistor is coupled with the first end of the fourth adjustable resistor;

a second end of the fourth adjustable resistor is coupled to the first end of the fifth adjustable resistor and the output end of the NMOS current source, and is coupled to the output end of the temperature drift calibration reference voltage generation circuit;

a first end of the fifth adjustable resistor is coupled to the output end of the temperature drift calibration reference voltage generation circuit, and a second end of the fifth adjustable resistor is coupled to the first end of the sixth adjustable resistor and the output end of the PMOS current source;

and the second end of the sixth adjustable resistor is grounded.

13. The oscillator of claim 12, wherein the PMOS current source comprises: first PMOS pipe, second PMOS pipe, third PMOS pipe and fourth PMOS pipe, wherein:

the source electrode of the first PMOS tube is input with power supply voltage, the grid electrode of the first PMOS tube is coupled with the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is coupled with the input end of the first NMOS current source;

the source electrode of the second PMOS tube is input with the power supply voltage, and the drain electrode and the grid electrode of the second PMOS tube are coupled with the output end of the first NMOS current source;

the source electrode of the third PMOS tube inputs the power supply voltage, the grid electrode of the third PMOS tube is coupled with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the input end of the second NMOS current source;

the source electrode of the fourth PMOS tube inputs the power supply voltage, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is a first output end of the PMOS current source.

14. The oscillator of claim 12, wherein the first NMOS current source comprises: first NMOS pipe, second NMOS pipe, first PNP triode, second PNP triode and current resistor, wherein:

the grid electrode of the first NMOS tube is coupled with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is coupled with the emitting electrode of the first PNP triode, and the drain electrode of the first NMOS tube is the input end of the first NMOS current source;

the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube is the output connection of the first NMOS current source, and the source electrode of the second NMOS tube is coupled with the first end of the current resistor;

the second end of the current resistor is coupled with the emitter of the second PNP triode;

the base electrode of the first PNP triode is coupled with the collector electrode of the first PNP triode and is grounded;

and the base electrode of the second PNP triode is coupled with the collector electrode of the second PNP triode and is grounded.

15. The oscillator of claim 12, wherein the second NMOS current source comprises: third NMOS pipe and fourth NMOS pipe, wherein:

the grid electrode of the third NMOS tube is coupled with the drain electrode of the third NMOS tube, the third NMOS tube is an input end of the second NMOS current source, and the source electrode of the third NMOS tube is grounded;

and the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube is the output end of the second NMOS current source, and the source electrode of the fourth NMOS tube is grounded.