CN103475189A - Oscillator of PWM (pulse-width modulation) controller - Google Patents

Abstract

The invention discloses an oscillator of a PWM (pulse-width modulation) controller, which comprises three branch circuits connected in parallel with an input voltage source and an operational amplifier, wherein a first branch circuit is provided with a resistor R1 and a resistor R2; a second branch circuit is provided with a resistor R3, a triode N1 and a resistor R4; a third branch circuit is provided with a resistor R5; the resistor R5 is respectively connected with a capacitor C1 and a resistor R6 which are connected in parallel and the anode of a diode D2; and the reverse input end of the operational amplifier is connected between the resistor R6 and a capacitor C2, the non-reverse input end is connected with the collector electrode of the triode N1 and connected with a resistor R7 which is connected in series with the anode of a diode D3, the output end is connected with cathodes of the diode D2 and the diode D3, and the first signal output end and the second signal output end are connected between the resistor R7 and the diode D3. The provided oscillator of a PWM controller has favorable frequency consistency, low rate of change with temperature and wide external synchronization clock frequency range; and synchronization can be realized above and below the natural vibration frequency of the oscillator.

Description

A kind of oscillator of PWM controller

Technical field

The invention belongs to pulse width modulation control technology field, relate to a kind of oscillator of PWM controller.

Background technology

The stability of oscillator directly determines the stability of DC/DC converter frequency, the stability of switching frequency is the important indicator of DC/DC converter, and the stability of switching frequency can have influence on the aspects such as the stability, efficiency, electromagnetic radiation, reliability of DC/DC converter.

At present, DC/DC converter PWM(pulse width modulation used) as shown in Figure 1, the high low temperature of (as UC1843, UCC1802 etc.) oscillator frequency (55 ℃～+ 125 ℃) rate of change is greatly about 20%～30% left and right for the oscillator circuit of controller.

In a lot of noise-sensitive application, usually the DC/DC converter by outer synchronizing function by Frequency Locking to external system clock, at present, the outer synchronizing function circuit of PWM controller (as UC1843, UCC1802 etc.) as shown in Figure 2, for positive lock, the oscillator natural frequency of vibration should, than low 10% left and right of clock frequency, limit DC/DC converter applications occasion.

Summary of the invention

The problem that the present invention solves is to provide a kind of oscillator of PWM controller, has solved the larger problem of high low temperature oscilator drift, and outer synchronizing function signal is provided simultaneously.

The present invention is achieved through the following technical solutions:

A kind of oscillator of PWM controller, comprise three branch roads and the operational amplifier that are in parallel with input voltage source;

The first branch road is provided with resistance R 1 and resistance R 2, and the base stage of triode N1 is connected between resistance R 1 and resistance R 2, and resistance R 2 is also by diode D1 ground connection;

The second branch road is provided with resistance R 3, triode N1 and resistance R 4, the collector electrode of resistance R 3 connecting triode N1, the emission collection contact resistance R4 of triode N1, resistance R 4 ground connection;

The 3rd branch road is provided with resistance R 5, and resistance R 5 connects respectively the anode of the capacitor C 1, resistance R 6 and the diode D2 that are in parallel, capacitor C 1 ground connection wherein, and resistance R 6 connects the capacitor C 2 of ground connection;

The reverse input end of operational amplifier is connected between resistance R 6 and capacitor C 2, non-inverting input connects the collector electrode of triode N1, and the resistance R 7 that is in series of the anode of connection and diode D3, output connects negative electrode and the first signal output of diode D2, diode D3, and the secondary signal output is connected between resistance R 7 and diode D3.

Described first signal output is the adjustable low level narrow pulse signal end for magnetic feedback carrier drive circuit, and the secondary signal output is to form the adjustable low level narrow pulse signal end of circuit for sawtooth waveforms.

Described triode N1 is the NPN triode.

The base stage that the dividing potential drop of described the first branch road by resistance R 1, resistance R 2 is triode N1 provides bias voltage; Input voltage source provides voltage for the operational amplifier non-inverting input after by resistance R 3 step-downs; Resistance R 6, resistance R 5, capacitor C 1 and capacitor C 2 form second order and discharge and recharge network.

After input voltage source starts power supply, the current potential V-of the reverse input end of operational amplifier is 0V, non-inverting input current potential V+ provides bias voltage V+H by the collector electrode of triode N1, operational amplifier output high level, diode D2 turn-offs, second order discharges and recharges network and starts charging, and the reverse input end voltage of operational amplifier starts to rise; When reverse input end voltage rises to V+H, the output switching activity of operational amplifier, the first output end signal step-down, diode D2 drags down the current potential Vc1 of capacitor C 1, resistance R 6, capacitor C 2 start the single order electric discharge simultaneously, and reverse input end current potential V-is pulled low to V+L by diode D3, resistance R 7 by non-inverting input current potential V+; When reverse input end current potential V-equals V+L, the output of operational amplifier is overturn again, and diode D2 turn-offs, and second order discharges and recharges network and again starts charging.

Described input voltage source is by 1 charging of 5 pairs of capacitor C of resistance R, and the secondary signal output to capacitor C 1 electric discharge, forms the sawtooth signal with feed forward function by diode D2.

The base stage of triode N1, as synchronous input end, by resistance R 8 and capacitor C 3, connects input signal Sync_in, is only worked in the height edge of input signal.

Described input signal Sync_in is outer synchronizing clock signals, be injected into the base stage of triode N1 by capacitor C 3 and resistance R 8, to change the threshold values of operational amplifier non-inverting input current potential V+, make the frequency of the first output signal consistent with the frequency of outer synchronizing clock signals.

Compared with prior art, the present invention has following useful technique effect:

The oscillator of PWM controller provided by the invention, form basic structure by the operational amplifier that is connected into the positive feedback form (high-speed comparator), the second order resistance-capacitance network that adopts R6, R5, C1, C2 to form is controlled and is discharged and recharged the time, and the turn threshold of positive feedback control algorithm amplifier produces oscillator signal.

Oscillator utilizes the different threshold values of operational amplifier when discharging and recharging, and has realized continuously discharging and recharging between 2 level; The frequency of oscillator depends primarily on RC charge/discharge time, operational amplifier delay/output low level, diode turn-on voltage and operational amplifier turn threshold voltage.Wherein, high threshold V+H changes very little; V+L resistance temperature is floated irrelevant, affected by operational amplifier VOL and D2 diode drop, therefore can solve the larger problem of high low temperature oscilator drift.

Further, although the high temperature of R5 resistance floats and causes on reverse input end V-turn threshold and move and (move many on high threshold, on low threshold value, move few), and VOL+VD can cause moving down of reverse input end V-threshold value, if therefore R5 and R6 resistance adopt the temperature complementary process, the drift bearing of VB also can be reverse, and V-high temperature drifts about downwards, can cause moving down of V-lower threshold value to offset VOL+VD, thereby oscillator frequency is had to stabilization.

The oscillator of PWM controller provided by the invention, be injected into the b utmost point of oscillator triode N1 by C3 and R8, thereby changed non-inverting input current potential V+ threshold values, made the frequency of oscillator output signal OSC_out consistent with outer synchronizing clock signals Sync_in frequency.

The oscillator frequency high conformity of PWM controller provided by the invention, the variation with temperature rate is little, outer synchronised clock wide frequency range, and all can realize up and down synchronously in the oscillator natural frequency of vibration.

The accompanying drawing explanation

The schematic diagram of the oscillator that Fig. 1 is the UCC1802PWM controller;

Fig. 2 is the outer synchronizing function conspectus of UCC1802PWM controller;

The conspectus that Fig. 3 is oscillator of the present invention;

The connection diagram that Fig. 4 is oscillator of the present invention;

Fig. 5 is oscillator simulation waveform schematic diagram;

Fig. 6 is outer synchronization module simulation waveform schematic diagram.

Embodiment

Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.

Referring to Fig. 3, a kind of oscillator of PWM controller, comprise three branch roads and the operational amplifier IC1a that are in parallel with input voltage source;

The first branch road is provided with resistance R 1 and resistance R 2, and the base stage of triode N1 is connected between resistance R 1 and resistance R 2, and resistance R 2 is also by diode D1 ground connection;

The second branch road is provided with resistance R 3, triode N1 and resistance R 4, the collector electrode of resistance R 3 connecting triode N1, the emission collection contact resistance R4 of triode N1, resistance R 4 ground connection;

The 3rd branch road is provided with resistance R 5, and resistance R 5 connects respectively the anode of the capacitor C 1, resistance R 6 and the diode D2 that are in parallel, capacitor C 1 ground connection wherein, and resistance R 6 connects the capacitor C 2 of ground connection;

The reverse input end of operational amplifier IC1a is connected between resistance R 6 and capacitor C 2, non-inverting input connects the collector electrode of triode N1, and the resistance R 7 that is in series of the anode of connection and diode D3, output connects negative electrode and the first signal output OSC_out of diode D2, diode D3, and secondary signal output OSC_out1 is connected between resistance R 7 and diode D3.

Wherein, the base stage that the dividing potential drop of the first branch road by resistance R 1, resistance R 2 is triode N1 provides a bias voltage VB, connects R3 between Vcc and N1 collector electrode, by after resistance R 3 step-downs, for operational amplifier IC1a non-inverting input, providing voltage; Resistance R 6, resistance R 5, capacitor C 1 and capacitor C 2 form second order and discharge and recharge network RC.

Concrete, described first signal output OSC_out is the adjustable low level narrow pulse signal end for magnetic feedback carrier drive circuit, secondary signal output OSC_out1 can be used for the adjustable low level burst pulse that sawtooth waveforms forms circuit.Triode N1 is the NPN triode.

After input voltage source starts power supply (circuit powers on rear), the current potential V-of the reverse input end of operational amplifier IC1a is 0V, non-inverting input current potential V+ provides a bias voltage V+H by the collector electrode of triode N1, operational amplifier IC1a exports high level, trombone slide under diode D2() turn-off, the second order that R5C1R6C2 forms discharges and recharges network and starts charging, the reverse input end voltage of operational amplifier IC1a starts to rise, and the non-inverting input current potential V+ that triode N1 provides is the V+H(set point);

When reverse input end voltage rises to V+H, the output switching activity of operational amplifier IC1a, the first output OSC_out signal step-down, the diode D2 of conducting drags down the current potential Vc1 of capacitor C 1 rapidly, resistance R 6, capacitor C 2 start the single order electric discharge simultaneously, and reverse input end current potential V-is pulled low to the V+L(set point by diode D3, resistance R 7 by non-inverting input current potential V+); When the R6C2 electric discharge makes reverse input end current potential V-equal V+L (threshold value is hanged down in the upset set), the output of operational amplifier IC1a is overturn again, and diode D2 turn-offs, and second order discharges and recharges network and again starts charging, starts next circulation.

The sawtooth waveform of described secondary signal output OSC_out1 becomes:

Input voltage source is by 1 charging of 5 pairs of capacitor C of resistance R, and secondary signal output OSC_out1 discharges to capacitor C 1 by diode D2, thereby forms the sawtooth signal with feed forward function.

Referring to Fig. 4, while using in to the DC/DC converter, the base stage of triode N1, as synchronous input end, by resistance R 8 and capacitor C 3, connects input signal Sync_in, is only worked in the height edge of input signal;

When being outer synchronizing clock signals, input signal (is generally Transistor-Transistor Logic level), be injected into the b utmost point of oscillator triode N1 by C3 and R8, thereby changed non-inverting input current potential V+ threshold values, made the frequency of oscillator output signal OSC_out consistent with outer synchronizing clock signals Sync_in frequency.

Synchronous input end, at when normal operation external capacitor C3 and resistance R 8, only is generally Transistor-Transistor Logic level to input signal Sync_in() height along working.In the oscillator rising edge stage, when synchronous input adds low level 0.8V, the base potential VB of triode N1 is pulled to 1.52V by moment, and non-inverting input current potential V+ current potential becomes 9.27V; When synchronous input adds high level 4.5V, the base potential VB current potential of triode N1 is raised to 3.5V by moment, and non-inverting input current potential V+ current potential becomes 6.3V.

Oscillator frequency temperature provided by the invention is floated to analysis:

As shown in Figure 3, Figure 4, the frequency of oscillator depends primarily on charge/discharge time, operational amplifier delay/output low level, diode turn-on voltage and the operational amplifier turn threshold voltage that second order discharges and recharges network RC.

Threshold value when 1. the upset of non-inverting input initial potential V+H(oscillator is set high)

During without external synchronization signal, triode N1 is by divider resistance R1, resistance R 2 and diode D1 automatic biasing, output potential: V+H=V _cC-R3 * I _c;

And $I_C=(V_{\mathrm{CC}}-V_{\mathrm{BE}})\&times;\frac{\mathrm{<figure-callout\; id="2R"\; label="R"\; filenames="HDA0000373464100000012.png"\; state="\{\{state\}\}">R</figure-callout>}2}{R1+\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">R</figure-callout>}2}\&times;\frac{1}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000373464100000011.png,HDA0000373464100000013.png"\; state="\{\{state\}\}">R</figure-callout>}4}$

In circuit, diode is identical with the triode area, and electric current is also basic identical, therefore VBE is equal, substitution obtains: $V+H=V_{\mathrm{CC}}-(V_{\mathrm{CC}}-V_{\mathrm{BE}})\&times;\frac{\mathrm{<figure-callout\; id="2R"\; label="R"\; filenames="HDA0000373464100000012.png"\; state="\{\{state\}\}">R</figure-callout>}2}{R1\&times;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">R</figure-callout>}2}\&times;\frac{R3}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000373464100000011.png,HDA0000373464100000013.png"\; state="\{\{state\}\}">R</figure-callout>}4}$

R1=10k Ω, R2=2k Ω, R3=3.3k Ω, R4=2.2k Ω, VCC=11V are set, that is:

$V+H=\frac{3}{4}{V}_{\mathrm{CC}}-\frac{1}{4}{V}_{\mathrm{BE}}$

Following actual measurement and emulation are arranged:

Output potential V+H=8.05V(sim8.1V under normal temperature);

Output potential V+H=8V(sim8.1V under high temperature);

Output potential V+H=8.1V(sim8.1V under low temperature).

Actual measurement shows with emulation: under three kinds of temperature, the high threshold V+H of non-inverting input current potential V+ changes very little.

2. operational amplifier is output as the V+L current potential (threshold value when the oscillator upset is low) while hanging down

Suppose that the R7 electric current is i mA, R7=3.3k Ω be set, have:

Vcc-3.3（i+0.45）=VOL+0.7+3.3×i

Solve: i=1.2mA

: V+L=4.5V(sim4.45V)

During high temperature: Vcc-R3 * i-2.5=VOL+0.5+R7 * i

During low temperature: Vcc-R3 * i-2.5=VOL+0.9+R7 * i

Three warm lower threshold values:

$V+L=V_{\mathrm{CC}}-R3\&times;i-2.5=4+\frac{V_{\mathrm{BE}}+{\mathrm{<figure-callout\; id="2"\; label="V\; OL"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{OL}}}{2}$

In above formula, V+L resistance temperature is floated irrelevantly, affected by operational amplifier and D2 diode drop.

3. second order R5C1R6C2 network charging process

Row KCL equation: Vcc=10.5V=R5 (ic1+ic2)+Vc1

Wherein: Vc1=R6*ic2+Vc2, $\mathrm{ic}1=C1\&times;\frac{\mathrm{dVc}1}{\mathrm{dt}},$ $\mathrm{<figure-callout\; id="2"\; label="ic"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">ic</figure-callout>}2=\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2\&times;\frac{\mathrm{<figure-callout\; id="2"\; label="dVc"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">dVc</figure-callout>}2}{\mathrm{dt}}$

Substitution can obtain: $R5C1R6\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2\&times;\frac{{\mathrm{<figure-callout\; id="2"\; label="d"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">d</figure-callout>}}^2\mathrm{<figure-callout\; id="2"\; label="Vc"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">Vc</figure-callout>}2}{{\mathrm{<figure-callout\; id="2"\; label="dt"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">dt</figure-callout>}}^2}+(R5C1+R6\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2+R6C2)\frac{\mathrm{<figure-callout\; id="2"\; label="dVc"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">dVc</figure-callout>}2}{\mathrm{dt}}+\mathrm{Vc}2-10.5=0$

If general solution Vc2=A1eP1t+A2eP2t+C

Can obtain: C=10.5

$P1.2=\frac{-(R5C1+R5\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2+R6C2)\&PlusMinus;\sqrt{{(R5C1+R5\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2+R6C2)}^2-4\left(R5C1R6C2\right)}}{2R5C1R6\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2}$

Substitution condition Vc2(t=0)=0V obtains A1+A2=-10.5V

Vc1(t=0)=0V obtains A1*P1+A2*P2=0

Charging interval, Tr had formula: Vc2(t=Tr)=V+=8V(sim8.1V)

The actual charging interval of circuit should be Tr and operational amplifier upset Td sum time of delay.

4. R2C2 discharge process

Vc1=VOL+0.7V=0.9V, V-initial value=V+ turn threshold=9V(sim8.1V, actual in operational amplifier postpones, V-can rise to 8.7V)

$u=-\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}{2}^{\&times;\frac{\mathrm{du}}{\mathrm{dt}}}\&times;R6+\mathrm{VOL}+0.7V$

If general solution u=AePt+C, initial value u(t=0)=8.7V

Solve: C=0.9V a=7.8

That is: $V-=7.8*e^{-\frac{t}{R6\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000373464100000013.png"\; state="\{\{state\}\}">C</figure-callout>}2}}+0.9$

When V-=V+=4.45V, t=0.787*R6C2=0.787*5.1k*30p=120.4ns.

Also comprise that the operational amplifier upset postpones actual discharge time, relatively 1.67us(600kHz) typical cycle of oscillation, discharge process is very of short duration.

3) from above-mentioned analysis, the high temperature of R5 resistance floats and causes on the V-turn threshold to move and (move many on high threshold, on low threshold value, move few), and VOL+VD can cause moving down of V-lower threshold value, if therefore R5 and R6 resistance adopt the temperature complementary process, the drift bearing of VB also can be reverse, and V-high temperature drifts about downwards, can cause moving down of V-lower threshold value to offset VOL+VD, thereby oscillator frequency is had to stabilization.

Oscillator provided by the invention utilizes the setting of the different threshold values of operational amplifier when discharging and recharging, realized continuously discharging and recharging between 2 level, the frequency of oscillation of itself depends on 2 level values and the time constant discharged and recharged, the simulation waveform that is as shown in Figure 5 oscillator (is wherein schemed the waveform of top for inputting waveform, the waveform of below is output waveform), it is the 600kHz left and right that frequency is set.

R5=8.2k Ω, R6=3.3k Ω, C1=68pf, C2=33pf are set, and during VCC=11V, oscillator frequency is 605kHz; With this understanding, when VCC=9V, frequency is 615.2kHz, and during VCC=15V, frequency is 624.2kHz, maximum deviation 3.17%.

Square-wave signal by the certain frequency of synchronous input end Sync_in access outside, can make oscillator output end OSC_out and be consistent with Sync_in end incoming frequency, outer synchronization module simulation waveform (in figure, upper waveform is output waveform, the waveform that lower waveform is input signal) as shown in Figure 6.

And R8=1.3k Ω, C3=0.01uf are set; Can realize that 500kHz～700kHz frequency range output is synchronous; Input high level (Sync_in=5V) electric current 944 μ A, input low level (Sync_in=0V) electric current 890 μ A.

The high base DC/DC of the core of take converter is example, and this DC/DC converter input voltage range is 80V～140V, and power output is 100W, output ± 15V/3.33A.Frequency of oscillation and outer synchronization frequency range to this product are tested, and test data is as shown in table 1, table 2.

The high low temperature test data of table 1 frequency of oscillation

The high low temperature test data of the outer synchronization frequency range of table 2

Analytical table 1, table 2 test data, result shows: oscillator frequency high conformity provided by the invention, the variation with temperature rate is little, outer synchronised clock wide frequency range, and all can realize up and down synchronously in the oscillator natural frequency of vibration.

Claims (8)

1. the oscillator of a PWM controller, is characterized in that, comprises three branch roads and the operational amplifier (IC1a) that are in parallel with input voltage source;

The first branch road is provided with resistance R 1 and resistance R 2, and the base stage of triode N1 is connected between resistance R 1 and resistance R 2, and resistance R 2 is also by diode D1 ground connection;

The second branch road is provided with resistance R 3, triode N1 and resistance R 4, the collector electrode of resistance R 3 connecting triode N1, the emission collection contact resistance R4 of triode N1, resistance R 4 ground connection;

The 3rd branch road is provided with resistance R 5, and resistance R 5 connects respectively the anode of the capacitor C 1, resistance R 6 and the diode D2 that are in parallel, capacitor C 1 ground connection wherein, and resistance R 6 connects the capacitor C 2 of ground connection;

The reverse input end of operational amplifier (IC1a) is connected between resistance R 6 and capacitor C 2, non-inverting input connects the collector electrode of triode N1, and the resistance R 7 that is in series of the anode of connection and diode D3, output connects negative electrode and the first signal output (OSC_out) of diode D2, diode D3, and secondary signal output (OSC_out1) is connected between resistance R 7 and diode D3.

2. the oscillator of PWM controller as claimed in claim 1, it is characterized in that, described first signal output (OSC_out) is the adjustable low level narrow pulse signal end for magnetic feedback carrier drive circuit, and secondary signal output (OSC_out1) is to form the adjustable low level narrow pulse signal end of circuit for sawtooth waveforms.

3. the oscillator of PWM controller as claimed in claim 1, is characterized in that, described triode N1 is the NPN triode.

4. the oscillator of PWM controller as claimed in claim 1, is characterized in that, the base stage that the dividing potential drop of described the first branch road by resistance R 1, resistance R 2 is triode N1 provides bias voltage; Input voltage source provides voltage for operational amplifier (IC1a) non-inverting input after by resistance R 3 step-downs; Resistance R 6, resistance R 5, capacitor C 1 and capacitor C 2 form second order and discharge and recharge network.

5. the oscillator of PWM controller as claimed in claim 4, it is characterized in that, after input voltage source starts power supply, the current potential V-of the reverse input end of operational amplifier (IC1a) is 0V, non-inverting input current potential V+ is that the collector electrode by triode N1 provides bias voltage V+H, operational amplifier (IC1a) output high level, and diode D2 turn-offs, second order discharges and recharges network and starts charging, and the reverse input end voltage of operational amplifier (IC1a) starts to rise; When reverse input end voltage rises to V+H, the output switching activity of operational amplifier (IC1a), the first output (OSC_out) signal step-down, diode D2 drags down the current potential Vc1 of capacitor C 1, resistance R 6, capacitor C 2 start the single order electric discharge simultaneously, and reverse input end current potential V-is pulled low to V+L by diode D3, resistance R 7 by non-inverting input current potential V+; When reverse input end current potential V-equals V+L, the output of operational amplifier (IC1a) is overturn again, and diode D2 turn-offs, and second order discharges and recharges network and again starts charging.

6. the oscillator of PWM controller as claimed in claim 5, it is characterized in that, described input voltage source is by 1 charging of 5 pairs of capacitor C of resistance R, and secondary signal output (OSC_out1) to capacitor C 1 electric discharge, forms the sawtooth signal with feed forward function by diode D2.

7. the oscillator of PWM controller as described as claim 1 or 5, is characterized in that, the base stage of triode N1, as synchronous input end, by resistance R 8 and capacitor C 3, connects input signal Sync_in, only worked in the height edge of input signal.

8. the oscillator of PWM controller as claimed in claim 7, it is characterized in that, described input signal Sync_in is outer synchronizing clock signals, be injected into the base stage of triode N1 by capacitor C 3 and resistance R 8, to change the threshold values of operational amplifier non-inverting input current potential V+, make the frequency of the first output signal (OSC_out) consistent with the frequency of outer synchronizing clock signals.

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