CN102983836B - Active RC filter automatic frequency tuning circuit - Google Patents
Active RC filter automatic frequency tuning circuit Download PDFInfo
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Abstract
The invention discloses active RC filter automatic frequency tuning circuit, comprise comparator, constant-current source, generating circuit from reference voltage, switched-capacitor circuit and Digital Logic control circuit; It is characterized in that: described generating circuit from reference voltage produces the first reference voltage, the second reference voltage and the 3rd reference voltage and inputs the first comparator, operational amplifier and the second comparator respectively; The voltage that described constant-current source produces on described switched-capacitor circuit inputs described operational amplifier; Described Digital Logic control circuit receives the signal of described first comparator and described second comparator output, after carrying out calculation process, exports control code to described switched-capacitor circuit, adjusts the equivalent capacity of described switched-capacitor circuit; Implementation method of the present invention is simple, and cost is low, volume is little, low in energy consumption, tuning precision is high, can be widely used in the field such as electronics, communication, have a good application prospect.
Description
Technical field
The present invention relates to active RC filter, be specifically related to active RC filter automatic frequency tuning circuit.
Background technology
Active RC filter can obtain good noiseproof feature, preferably dynamic range and the good linearity, and its implementation is simple, thus be widely used in the radio-frequency transmitter of zero intermediate frequency or Low Medium Frequency, for the system requirements making the precision and stability of active RC filter frequency characteristic meet receiver, require that the resistance value of this filter of formation and capacitance have enough precision and stabilities, but in ic manufacturing process, tolerance due to technique can cause component parameter off-design value, and it also can change with the change of operational environment simultaneously.Generally, in integrated circuit, the ratio of identical type element can be more accurate and stable, ratio error as resistance can reach 1% or less, the ratio error of electric capacity can reach 0.1% or less, but the absolute value error of resistance and electric capacity is all very large, can up to more than 30%, these errors can cause the skew of filter frequencies, may cause the decay of useful signal and the amplification of interference signal.Therefore, just need to design the change that automatic frequency tuning circuit carrys out the RC network that compensate for process and environment bring, remove the cut-off frequency of stable filter.
Existing technical scheme is adopt frequency tuning circuit as shown in Figure 1, comprises RC oscillator, limiting amplifier, external reference clock, frequency divider and Digital Logical Circuits.Wherein the resistance fixed by some levels of RC oscillator and capacitor array and operational amplifier form, and as shown in Figure 2, resistance and the type of capacitor array and identical in filter, this makes filter and RC oscillator have similar RC time constant.The frequency of oscillation produced by RC oscillator compares with fixing clock reference frequency, in time there is deviation in frequency of oscillation and clock reference frequency, by the computing of Digital Logical Circuits, control capacitance array changes, make frequency of oscillation and clock reference frequency be tending towards equal the most at last, reach tuning effect.
Prior art is equivalent to a digital phase-locked loop, circuit more complicated, and when the frequency of oscillation of RC oscillator is larger, the frequency of oscillation of RC oscillator there will be error, by the precision of very difficult guarantee RC oscillator, the degree of regulation of whole circuit is restricted; When RC oscillator is in order to obtain less frequency of oscillation, resistance or capacitance will be larger, make the area of tuning circuit can become increasing, sometimes even can be suitable with the main part of filter, and its power consumption is also larger.
Summary of the invention
Technical problem to be solved by this invention is to provide active RC filter automatic frequency tuning circuit.
In order to solve the problems of the technologies described above, technical scheme of the present invention is, active RC filter automatic frequency tuning circuit comprises comparator, constant-current source, generating circuit from reference voltage, switched-capacitor circuit and Digital Logic control circuit; It is characterized in that:
Described generating circuit from reference voltage produces the first reference voltage, the second reference voltage and the 3rd reference voltage and inputs the first comparator, operational amplifier and the second comparator respectively;
Described switched-capacitor circuit comprises capacitor array; Described constant-current source is charged to described switched-capacitor circuit by switching tube two, and the break-make of described switching tube two is controlled by clock signal one, and this clock signal one is the inverse delayed signal of clock signal three; The voltage that described constant-current source produces on described switched-capacitor circuit inputs described operational amplifier;
The voltage that described switched-capacitor circuit produces and the second reference voltage are carried out amplification and process by described operational amplifier, the output voltage of described operational amplifier is charged by switching tube three pairs of electric capacity two, the break-make of this switching tube three is controlled by described clock signal three, and the voltage that described electric capacity two produces inputs described first comparator and described second comparator simultaneously;
Voltage on described electric capacity two and described first reference voltage compare by described first comparator, and comparative result is outputted to described Digital Logic control circuit by described first comparator;
Voltage on described electric capacity two and the 3rd reference voltage compare by described second comparator, and comparative result is outputted to described Digital Logic control circuit by described second comparator;
Described Digital Logic control circuit receives the signal of described first comparator and described second comparator output, after carrying out calculation process, exports control code to described switched-capacitor circuit, adjusts the equivalent capacity of described switched-capacitor circuit.
According to a kind of preferred version of active RC filter automatic frequency tuning circuit of the present invention, described switching tube three is metal-oxide-semiconductor, the grid of this metal-oxide-semiconductor receives described clock signal three, the output voltage of described operational amplifier is charged to described electric capacity two by the drain electrode of this metal-oxide-semiconductor and source electrode, and the source electrode of this metal-oxide-semiconductor is connected with the input of described first comparator and described second comparator simultaneously.
According to a kind of preferred version of active RC filter automatic frequency tuning circuit of the present invention, described operational amplifier is made up of amplifier, electric capacity three, MOS switching tube one, wherein: the grid receive clock signal one of described MOS switching tube one, the source electrode of described MOS switching tube one connects the output of amplifier, and the drain electrode of described MOS switching tube one connects the inverting input of amplifier; The in-phase input end of amplifier receives the second reference voltage; Between the drain electrode that described electric capacity three is connected to described MOS switching tube one and source electrode.
According to a kind of preferred version of active RC filter automatic frequency tuning circuit of the present invention, described switched-capacitor circuit is made up of MOS switching tube four, MOS switching tube five and described capacitor array, wherein, the source electrode of described MOS switching tube four is connected with the drain electrode of described MOS switching tube five, the drain electrode of described MOS switching tube four connects the input of described operational amplifier, and the source electrode of described MOS switching tube five is connected with the source electrode of switching tube three by described electric capacity two; The clock signal inputting described MOS switching tube four grid and described MOS switching tube five grid is Non-overlapping clock signal, and this Non-overlapping clock signal refers to that another switching tube just turns off when MOS switching tube four and one of them conducting of MOS switching tube five; Between the drain electrode that capacitor array is connected to MOS switching tube five and source electrode.
According to a kind of preferred version of active RC filter automatic frequency tuning circuit of the present invention, described capacitor array is made up of several electric capacity and switch, between the drain electrode that each electric capacity is all connected to MOS switching tube five by switch and source electrode, the break-make of switch exports control code by described Digital Logic control circuit and controls.
The beneficial effect of active RC filter automatic frequency tuning circuit of the present invention is: the present invention is by detecting the change of RC time constant in tuning circuit, namely by the discharge and recharge of clock signal control switch condenser network, the equivalent capacity of control code adjustment switched-capacitor circuit is exported by Digital Logic control circuit, the RC time constant of tuning circuit is reached or to greatest extent close to desired value, realize controlling the RC time constant in filter, thus achieve the automatic tuning to active RC filter frequency; The present invention can eliminate the impact of technique and environment completely; Compared with prior art, chip area and power consumption is reduced; Further, implementation method of the present invention is simple, and cost is low, volume is little, low in energy consumption, tuning precision is high, makes filter frequencies have high stability, can be widely used in the field such as electronics, communication, have a good application prospect.
Accompanying drawing explanation
Fig. 1 is prior art schematic diagram.
Fig. 2 is existing RC pierce circuit figure
Fig. 3 is the schematic diagram of active RC filter automatic frequency tuning circuit of the present invention.
Fig. 4 be input switch Guan Si, five the oscillogram of clock CLK_P and CLK_N.
The function sequential chart of Fig. 5 Digital Logic control circuit.
Embodiment
See Fig. 3, active RC filter automatic frequency tuning circuit, comprises comparator, constant-current source I1, generating circuit from reference voltage 1, switched-capacitor circuit 2, Digital Logic control circuit 3 and clock generation circuit 4; Wherein:
Described generating circuit from reference voltage 1 produces the first reference voltage, the second reference voltage and the 3rd reference voltage and inputs the first comparator 5, operational amplifier 7 and the second comparator 6 respectively;
Described switched-capacitor circuit 2 comprises capacitor array C1, and capacitor array C1 adopts the capacitor array identical with filter; Described constant-current source I1 is charged to described switched-capacitor circuit 2 by switching tube two, and the break-make of described switching tube two is controlled by clock signal one, and this clock signal one is the inverse delayed signal of clock signal three; The voltage that described constant-current source I1 produces on described switched-capacitor circuit 2 inputs described operational amplifier 7;
The voltage that described switched-capacitor circuit 2 produces and the second reference voltage are carried out amplification and process by described operational amplifier 7, the output voltage of described operational amplifier 7 is charged by switching tube three pairs of electric capacity two, the break-make of this switching tube three is controlled by described clock signal three, and the voltage that described electric capacity two produces inputs described first comparator 5 and described second comparator 6 simultaneously;
Voltage on described electric capacity two and described first reference voltage compare by described first comparator 5, and comparative result is outputted to described Digital Logic control circuit 3 by described first comparator 5;
Voltage on described electric capacity two and the 3rd reference voltage compare by described second comparator 6, and comparative result is outputted to described Digital Logic control circuit 3 by described second comparator 6;
Described Digital Logic control circuit 3 receives the signal of described first comparator 5 and described second comparator 6 output, after carrying out calculation process, exports control code to described switched-capacitor circuit 2, adjusts the equivalent capacity of described switched-capacitor circuit 2;
Clock generation circuit 4 receives external reference clock signal, and after carrying out scaling down processing, clocking is input to switching tube three and switched-capacitor circuit 2.
The present invention, by Digital Logic control circuit adjustment switched-capacitor circuit, by detecting the change of RC time constant in tuning circuit, controls the RC time constant of filter.In order to the validity detected, identical all with filter of resistance in switched-capacitor circuit and capacitor array, and adopt the reference clock identical with designed filter centre frequency to control the discharge and recharge of described switched-capacitor circuit, the equivalent capacity of control code adjustment switched-capacitor circuit is exported by Digital Logic control circuit, when the equivalent capacity of capacitor array is large, its equivalent resistance will diminish, the voltage that switched-capacitor circuit produces reduces, the output voltage of operational amplifier is changed, the voltage on electric capacity two is caused to change, first comparator exports a pulse, make the forward-backward counter subtraction in Digital Logic control circuit, reduce the control code of capacitor array, the equivalent capacity of capacitor array is reduced, its equivalent electric resistive is large, in like manner, when the equivalent capacity hour of capacitor array, its equivalent resistance will become greatly, and the voltage on switched-capacitor circuit raises, and the output voltage of operational amplifier is changed, the voltage on electric capacity two is caused to change, second comparator exports a pulse, makes the forward-backward counter in Digital Logic control circuit do add operation, increases the control code of capacitor array, the equivalent capacity of capacitor array is increased, and its equivalent resistance diminishes, only have when the equivalent capacity of capacitor array is suitable value, voltage on switched-capacitor circuit will no longer reduce, the second reference voltage will be approached, first comparator and the second comparator all can not export pulse again, forward-backward counter will no longer adjust, thus make the equivalent capacity of capacitor array remain in a stationary value, illustrate that the RC time constant of now tuning circuit has reached or to greatest extent close to desired value, the RC time constant namely in tuning circuit equals time constant corresponding to reference clock frequency just.Now, tuning circuit completes calibration.Then Digital Logic control circuit exports control code to filter, and the capacitor array in filter is adjusted to the size the same with tuning circuit, and now, filter centre frequency just equals reference clock frequency.Because tuning circuit is identical with capacitor array with the resistance in filter, suffered technique is also identical with the impact of environment, so tuning circuit can eliminate the impact of technique and environment completely.
In a particular embodiment, described switching tube three is metal-oxide-semiconductor, the grid of this metal-oxide-semiconductor receives described clock signal three, the output voltage of described operational amplifier 7 is charged to described electric capacity two by the drain electrode of this metal-oxide-semiconductor and source electrode, and the source electrode of this metal-oxide-semiconductor is connected with the input of described first comparator 5 and described second comparator 6 simultaneously.
Described operational amplifier 7 is made up of amplifier, electric capacity three, MOS switching tube one, wherein: the grid receive clock signal one of described MOS switching tube one, the source electrode of described MOS switching tube one connects the output of amplifier, and the drain electrode of described MOS switching tube one connects the inverting input of amplifier; The in-phase input end of amplifier receives the second reference voltage; Between the drain electrode that described electric capacity three is connected to described MOS switching tube one and source electrode.
Described switched-capacitor circuit 2 is made up of MOS switching tube four, MOS switching tube five and described capacitor array C1, wherein, the source electrode of described MOS switching tube four is connected with the drain electrode of described MOS switching tube five, the drain electrode of described MOS switching tube four connects the input of described operational amplifier, and the source electrode of described MOS switching tube five is connected with the source electrode of switching tube three by described electric capacity two; The clock signal inputting described MOS switching tube four grid and described MOS switching tube five grid is Non-overlapping clock signal, and this Non-overlapping clock signal refers to that another switching tube just turns off when MOS switching tube four and one of them conducting of MOS switching tube five; Between the drain electrode that capacitor array C1 is connected to MOS switching tube five and source electrode.
Described capacitor array C1 is made up of several electric capacity and switch, and between the drain electrode that each electric capacity is all connected to MOS switching tube five by switch and source electrode, the break-make of switch exports control code by described Digital Logic control circuit 3 and controls.
In a particular embodiment, see Fig. 3, active RC filter automatic frequency tuning electric routing switch pipe M1, M2, M3, electric capacity C2, C3, generating circuit from reference voltage, constant-current source I1, amplifier OPAMP, switched-capacitor circuit, inverter INV, comparator COMP1, COMP2 and Digital Logic control circuit 3 and clock generation circuit 4 are formed.Switched-capacitor circuit is made up of switching tube M4, M5 and capacitor array C1, and switching tube M4, M5 control by Non-overlapping clock signal, and wherein capacitor array C1 adopts the capacitor array identical with filter.Constant-current source I1 produces voltage Va by switching tube M1 on switched-capacitor circuit 2, and the break-make of switching tube M2 is controlled by clock signal one, and this clock signal one is the inverse delayed signal of clock signal three; Generating circuit from reference voltage is made up of constant-current source I2 and resistance R1, R2, R3; Constant-current source I2 flows through resistance R1, R2, R3 and produces the first reference voltage Vref 1, second reference voltage Vref 2 and the 3rd reference voltage Vref 3 respectively; Two inputs of amplifier OPAMP obtain voltage Va and the second reference voltage Vref 2 respectively; Two inputs of comparator COMP1 obtain the charging voltage Vcap of the first reference voltage Vref 1 and electric capacity C2 respectively; Two inputs of comparator COMP2 obtain the charging voltage Vcap of the 3rd reference voltage Vref 3 and electric capacity C2 respectively.Clock generation circuit 4 receives external reference clock signal, after carrying out scaling down processing, export Non-overlapping clock signal to switching tube M4, M5, and clock signal three is to switching tube M3.
When input switch pipe M3 clock CLK_DIS is low level, switching tube M1 conducting, switching tube M3 turns off, and amplifier OPAMP is that follower connects, and makes the output voltage Vo of amplifier OPAMP followed by the second reference voltage Vref 2; When clock CLK_DIS is high level, switching tube M1 turns off, and switching tube M3 conducting, charges to electric capacity C2, and after clock CLK_DIS is low, electric charge will be kept on electric capacity C2.Reference voltage Vref 1 on voltage Vcap on electric capacity C2 and comparator COMP1, COMP2 input, Vref3 compare respectively, and comparative result exports when clock CLK_DIS is low by comparator COMP1, COMP2 simultaneously; When the current potential of the voltage Vcap on electric capacity C2 is higher than reference voltage Vref 1, comparator COMP1 output switching activity, UPout exports a positive pulse, the current potential of the voltage Veap on electric capacity C2 is also higher than reference voltage Vref 3, the output of comparator COMP2 can not overturn, DOWNout will remain electronegative potential, and the forward-backward counter in Digital Logic control circuit is subtracted calculating, and Digital Logic control circuit exports the electric capacity quantity that control code reduces capacitor array; When the voltage Vcap current potential on electric capacity C2 is lower than reference voltage Vref 3, comparator COMP2 output switching activity, DOWNout exports a positive pulse, voltage Vcap current potential on electric capacity C2 is always lower than reference voltage Vref 1, the output of comparator COMP1 can not overturn, UPout will remain electronegative potential, make the forward-backward counter in Digital Logic control circuit make additional calculation, and Digital Logic control circuit exports the electric capacity quantity that control code increases capacitor array.
Figure 4 shows that clock control waveform CLK_P and the CLK_N of switching tube M4, M5.Clock CLK_P and CLK_N is frequency is reference clock frequency f
clknon-overlapping clock, described non-overlapping clock refers to that another switch just turns off as switching tube M4 and one of them conducting of switching tube M5.When the clock control signal CLK_P of switching tube M4 is high level, switching tube M4 conducting, constant-current source I1 charges to capacitor array C1, thereafter, when the clock control signal CLK_N of switching tube M5 is high level, switching tube M5 conducting, capacitor array C1 is discharged by switching tube M5.Suppose that the equivalent capacity of the capacitor array C1 in switched-capacitor circuit is Ce, so, at its duration of work, to its equivalent resistance during capacitor array C1 discharge and recharge be:
Establish constant-current source electric current I here
1=NI
2, N gets the natural number being more than or equal to 1; The resistance of resistance R1, R2 and R3 is equal, and its value is Rref, and constant-current source I2 flows through the voltage V that resistance R1, R2, R3 produce
ref2=2I
2r
ref.
The calibration process of this automatic frequency tuning circuit can be stated with following formula:
The voltage that switched-capacitor circuit produces:
If
wherein, K gets the natural number being more than or equal to 1;
Make K=1, N=2,
And have in active RC filter:
R in formula
filter, C
filterbe respectively the equivalent resistance in filter and equivalent capacity
Because the resistance in both is identical with capacitor array, then f
0=f
clk.
From above-mentioned formula, can draw to draw a conclusion:
When the equivalent capacity Ce of capacitor array is excessive, its equivalent resistance Re will diminish, voltage Va on switched-capacitor circuit reduces, the output voltage Vo of operational amplifier OPAMP is raised, cause the current potential of the voltage Vcap on electric capacity C2 higher than reference voltage V ref1, comparator COMP1 output switching activity, UPout exports a positive pulse, make the forward-backward counter subtraction in Digital Logic control circuit, reduce the control code of capacitor array, the equivalent capacity Ce of capacitor array C1 is reduced, its equivalent resistance Re becomes large, voltage Va on switched-capacitor circuit is raised, the output electricity Vo of operational amplifier OPAMP reduces, voltage Vcap on electric capacity C2 also reduces, only have when capacitor array C1 is suitable value, voltage Va on switched-capacitor circuit will no longer raise, reference voltage V ref2 will be approached, UPout can not export pulse again, forward-backward counter in Digital Logic control circuit will no longer adjust, thus make capacitor array C1 remain in a stationary value, the RC time constant illustrating now has reached or to greatest extent close to desired value.
In like manner, when the equivalent capacity Ce of capacitor array is too small, its equivalent resistance Re will become large, voltage Va on switched-capacitor circuit raises, the output voltage Vo of operational amplifier OPAMP is reduced, cause the current potential of the voltage Vcap on electric capacity C2 lower than reference voltage V ref3, comparator COMP2 output switching activity, DOWNout exports a positive pulse, forward-backward counter is made to do add operation, increase the control code of capacitor array, the equivalent capacity Ce of capacitor array C1 is increased, its equivalent resistance Re diminishes, Va is reduced, Vo raises, Vcap also raises, only have when capacitor array C1 is suitable value, voltage Va on switched-capacitor circuit will no longer reduce, reference voltage V ref2 will be approached, DOWNout can not export pulse again, forward-backward counter will no longer adjust, thus make capacitor array C1 remain in a stationary value, the RC time constant illustrating now has reached or to greatest extent close to desired value.
Fig. 4 is the function sequential chart of Digital Logic control circuit.Digital Logic control circuit determines whether to increase and decrease the control code of charging capacitor array C1 according to UPout or DOWNout signal, after capacitor array C1 remains on some stability number a period of times, illustrate that RC time constant now has reached or to greatest extent close to desired value, just can assert that tuning circuit completes calibration.
Active RC filter automatic frequency tuning circuit of the present invention, reduces its area and power consumption.By detecting the change of RC time constant in tuning system, control the RC time constant in filter, control to carry out discharge and recharge to capacitor array C1 by reference clock, by the control code of Digital Logic control circuit increase and decrease capacitor array C1, make the RC time constant in tuning circuit just equal time constant corresponding to reference clock frequency fclk, RC time constant is reached or to greatest extent close to desired value.Because switched-capacitor circuit is identical with capacitor array with the resistance in filter, suffered technique is also identical with the impact of environment, so this active RC filter automatic frequency tuning circuit can eliminate the impact of technique and environment completely.
The tuning precision of this invention is subject to the quantization error of capacitor array C1 and the input offset voltage impact of comparator, and the larger precision of control code figure place of capacitor array is higher, by effective design, can improve tuning precision to greatest extent.
Above the specific embodiment of the present invention is described, but, the scope being not limited only to embodiment of the present invention's protection.
Claims (2)
1. active RC filter automatic frequency tuning circuit, comprises comparator, constant-current source (I1), generating circuit from reference voltage (1), switched-capacitor circuit (2) and Digital Logic control circuit (3); It is characterized in that:
Described generating circuit from reference voltage (1) produces the first reference voltage, the second reference voltage and the 3rd reference voltage and inputs the first comparator (5), operational amplifier (7) and the second comparator (6) respectively;
Described switched-capacitor circuit (2) comprises capacitor array (C1); Described constant-current source (I1) is by switching tube two to described switched-capacitor circuit (2) charging, and the break-make of described switching tube two is controlled by clock signal one, and this clock signal one is the inverse delayed signal of clock signal three; Described constant-current source (I1) inputs described operational amplifier (7) at the upper voltage produced of described switched-capacitor circuit (2);
The voltage of upper for described switched-capacitor circuit (2) generation and the second reference voltage are carried out amplification and process by described operational amplifier (7), the output voltage of described operational amplifier (7) is charged by switching tube three pairs of electric capacity two, the break-make of this switching tube three is controlled by described clock signal three, and the voltage that described electric capacity two produces inputs described first comparator (5) and described second comparator (6) simultaneously;
Voltage on described electric capacity two and described first reference voltage compare by described first comparator (5), and comparative result is outputted to described Digital Logic control circuit (3) by described first comparator (5);
Voltage on described electric capacity two and the 3rd reference voltage compare by described second comparator (6), and comparative result is outputted to described Digital Logic control circuit (3) by described second comparator (6);
Described Digital Logic control circuit (3) receives the signal that described first comparator (5) and described second comparator (6) export, after carrying out calculation process, export control code to described switched-capacitor circuit (2), adjust the equivalent capacity of described switched-capacitor circuit (2);
Described operational amplifier (7) is made up of amplifier, electric capacity three, MOS switching tube one, wherein: the grid receive clock signal one of described MOS switching tube one, the source electrode of described MOS switching tube one connects the output of amplifier, and the drain electrode of described MOS switching tube one connects the inverting input of amplifier; The in-phase input end of amplifier receives the second reference voltage; Between the drain electrode that described electric capacity three is connected to described MOS switching tube one and source electrode;
Described switched-capacitor circuit (2) is made up of MOS switching tube four, MOS switching tube five and described capacitor array (C1), wherein, the source electrode of described MOS switching tube four is connected with the drain electrode of described MOS switching tube five, the drain electrode of described MOS switching tube four connects the input of described operational amplifier, and the source electrode of described MOS switching tube five is connected with switching tube three by described electric capacity two; The clock signal inputting described MOS switching tube four grid and described MOS switching tube five grid is Non-overlapping clock signal, and this Non-overlapping clock signal refers to that another switching tube just turns off when MOS switching tube four and one of them conducting of MOS switching tube five; Between the drain electrode that capacitor array (C1) is connected to MOS switching tube five and source electrode;
Described capacitor array (C1) is made up of several electric capacity and switch, between the drain electrode that each electric capacity is all connected to MOS switching tube five by switch and source electrode, the break-make of switch exports control code by described Digital Logic control circuit (3) and controls.
2. active RC filter automatic frequency tuning circuit according to claim 1, it is characterized in that: described switching tube three is metal-oxide-semiconductor, the grid of this metal-oxide-semiconductor receives described clock signal three, the output voltage of described operational amplifier (7) is charged to described electric capacity two by the drain electrode of this metal-oxide-semiconductor and source electrode, and the source electrode of this metal-oxide-semiconductor is connected with the input of described first comparator (5) and described second comparator (6) simultaneously.
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| CN103259532A (en) * | 2013-06-04 | 2013-08-21 | 中科院微电子研究所昆山分所 | Resistor-capacitor filter calibrating circuit |
| CN107852141B (en) * | 2015-07-24 | 2021-01-29 | 华为技术有限公司 | Active resistance-capacitance filter, receiver, transmitter and base station |
| CN108134592A (en) * | 2016-12-01 | 2018-06-08 | 弥亚微电子（上海）有限公司 | The RC time constants calibration circuit and method of a kind of active filter |
| CN109302182B (en) * | 2018-08-27 | 2022-07-22 | 上海华虹集成电路有限责任公司 | RC time constant correction circuit and method adopting time-to-digital converter (TDC) |
| CN112825548B (en) * | 2019-11-21 | 2024-03-01 | 格科微电子（上海）有限公司 | Implementation method for reducing crosstalk of image sensor circuit |
| CN111404484B (en) * | 2020-04-26 | 2020-12-08 | 珠海迈巨微电子有限责任公司 | RC oscillator and electric device |
| CN114285392B (en) * | 2020-09-28 | 2023-02-03 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Active filter bandwidth calibration circuit |
| CN112491055A (en) * | 2020-12-25 | 2021-03-12 | 哈尔滨理工大学 | Automatic tuning structure of active filter |
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