CN114285392B

CN114285392B - Active filter bandwidth calibration circuit

Info

Publication number: CN114285392B
Application number: CN202011042974.8A
Authority: CN
Inventors: 李航标; 张凯; 王友华; 张然; 姚明; 赵晓冬; 刘智卿
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2023-02-03
Anticipated expiration: 2040-09-28
Also published as: CN114285392A

Abstract

The invention discloses a bandwidth calibration circuit of an active filter, and aims to provide a calibration circuit capable of flexibly and accurately adjusting the bandwidth of the filter. The invention is realized by the following technical scheme: the clock generating circuit generates a clock as a reference clock of the frequency synthesizer, the frequency synthesizer outputs the clock to the digital algorithm circuit, and a reset signal and an enable signal output by the digital algorithm circuit are output to the time sequence control circuit through NOR gate operation to generate three control signals; the current pulse generating circuit generates two different constant current pulses according to an input control signal and outputs the two different constant current pulses to the differential input end of the bandwidth-adjustable active filter; comparing the response of the time domain sampling filter with a reference voltage, and adjusting the size of a filter capacitor by a digital algorithm circuit according to a comparison result to search for the optimal filter bandwidth; and (3) using calibration clocks with different frequencies to carry out bandwidth calibration twice, and calculating the two calibration results to obtain the bandwidth of the precise filter insensitive to the PVT and chip aging of the circuit.

Description

Active filter bandwidth calibration circuit

Technical Field

The invention belongs to the technical field of filter calibration, and relates to a calibration circuit of an active filter bandwidth, which can be widely applied to a wireless transceiver system.

Background

Pre-filtering and calibration are key links in control system design and engineering implementation. A general high-precision fast control system is generally composed of a sensor, a filter, a correction network, a power stage, an execution unit and a controlled object. The main task of the design of such control systems is to design a filter and calibration network meeting the requirements according to the system performance requirements and mathematical models (transfer functions) of the sensor, the execution unit and the controlled object, and design a circuit for realization. The performance of a continuous control system depends to a large extent on the engineering design of the filtering and calibration loop circuitry, in addition to the analysis and design of the system transfer function. The expected characteristics of the filtering and calibration networks obtained in the system design both require the adoption of a circuit with precise optimization design, the expected network characteristics are realized as closely as possible, and meanwhile, better parameter robustness is required. Tools involved in designing a specific circuit are complex and tedious, the selection of the preferred range and the parameter toughness value has a large influence on the result, the obtained circuit parameter value is not a nominal value, the simplicity and the applicability are lacked in the actual engineering design, and the overall performance of the system is inevitably influenced by the time delay in the system.

Active filters are generally divided into low-pass, high-pass and band-pass and are designed with a bandwidth (or cut-off frequency) within a desired frequency range. The filter circuit realizes the transfer function by a specific circuit, the transfer function can be realized by passive elements such as R, L, C, M (mutual inductance) and the like, and the corresponding realization circuit is called as a passive filter; it can also be realized by a combination of active and passive components such as operational amplifiers, transistors, R, C, etc., and the corresponding circuit is called an active filter. An active filter may pass a desired signal while suppressing undesired passing signals and noise. The operational amplifier is a direct-coupled amplifier having a high gain, and can perform operations such as addition, subtraction, differentiation, integration, and the like on an input signal by using a simple combination of the operational amplifier and other elements, and is called an operational amplifier. The active filter is often composed of an operational amplifier and a complex passive feedback network, and is generally located at a post stage of down-conversion and a pre-stage of a variable gain amplifier, and the characteristics of the active filter directly affect the performance of a transceiver, and the filter structures required by different transceivers are often different.

The bandwidth of the filter is mainly composed of the capacitance C of the filter _f And a resistance value R _f The decision, for example a low pass filter, can be expressed as BW _-3dB ＝1/(2πR _f C _f ). With the continuous reduction of the integrated circuit process line width, the resistance, the capacitance and the active devices forming the filter are easily influenced by process deviation (delta P), power supply voltage fluctuation (delta V) and temperature change (delta T), which are called PVT for short, and chip aging, so that the bandwidth of the filter is influenced; in practical application, if the bandwidth of the filter can be flexible and fineThe accurate adjustment can make the application of the transceiver more flexible and the application range wider.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides the active filter bandwidth calibration circuit which has good engineering practicability, is universal and standardized in circuit design, can flexibly and accurately adjust the bandwidth of a filter, and automatically calibrates the bandwidth (or cut-off frequency) deviation caused by PVT and aging of a chip.

The above object of the present invention can be achieved by an active filter bandwidth calibration circuit comprising: an adjustable bandwidth active filter coupled between a mixer and a sample-and-hold circuit, a sample-and-hold circuit coupled between the adjustable bandwidth active filter and a voltage comparator, a voltage comparator coupled between the sample-and-hold circuit and a D flip-flop, a charge-discharge circuit coupled between the sample-and-hold circuit and a timing control circuit, a D flip-flop coupled between the voltage comparator and a digital algorithm circuit, a frequency synthesizer coupled between the digital algorithm circuit and a clock generation circuit, a digital algorithm circuit coupled between the frequency synthesizer and the timing control circuit, a nor gate G0 coupled between the digital algorithm circuit and the timing control circuit, a timing control circuit coupled between the digital algorithm circuit and a current pulse generation circuit, a current pulse generation circuit coupled between the timing control circuit and the adjustable bandwidth active filter, characterized in that: the clock generation circuit generates a clock signal CLK _ REF as a reference clock of a frequency synthesizer, and the frequency synthesizer generates a clock signal having a period T according to an externally input frequency control signal _CK Frequency of f _CK The clock signal CLK is sent to a digital algorithm circuit, an enable signal CAL _ PD and a reset signal RESETN output by the digital algorithm circuit are sent to a NOR gate G0 for NOR operation, and a signal RST determining the reset of the time sequence control circuit is output and sent to the time sequence control circuit; the time sequence control circuit generates three clock control signals CTL1, CTL2 and CTL3 with the same frequency, the same duty ratio and different phases under the control of an output clock CAL _ CLK of the digital algorithm circuit; charge release circuit on signalUnder the control of CTL3, releasing the capacitance charge of the sampling hold circuit; the current pulse generating circuit generates two constant current pulses with different sizes according to an input clock control signal CTL2 and a control signal MODE _ SEL output by the digital algorithm circuit, and outputs the constant current pulses to the differential input end of the bandwidth-adjustable active filter; calibrating different filter Bandwidths (BW) using CLK signals of different frequencies _-3dB,F ) (ii) a In the process of each calibration, the sampling and holding circuit samples the time domain of the output voltage of the bandwidth-adjustable active filter under the control of a signal CTL1, provides the sampling result to a voltage comparator, and compares the sampling voltage with a reference voltage; the D flip-flop is connected between the voltage comparator and the digital algorithm circuit in series, latches the comparison result CMPOUT under the control of the rising edge of the signal CTL3, and provides a comparison result signal LT latched in the D flip-flop for the digital algorithm circuit; under the action of a clock signal CLK and a trigger output LT, a digital algorithm circuit carries out calibration search twice, each bit of capacitance control code of the bandwidth-adjustable active filter is traversed in each search, and the optimal capacitance control code N is obtained by searching respectively _C1 、N _C2 (ii) a When the calibration is finished, the capacitance control codes obtained twice are operated to obtain a final capacitance control code N _F ＝2·N _C2 -N _C1 (ii) a The digital algorithm circuit outputs a signal ST for turning off a front-stage mixer circuit, and changes the size of current pulses of the current pulse generating circuit in twice calibration together with an output control signal MODE _ SEL, an enable signal CAL _ PD provided for the NOR gate G0 and a clock control signal CTL2 output by the time sequence control circuit; capacitance control code C _ CTL generated in two calibration processes<N:0>The adjustable capacitor CP1 and the adjustable capacitor CM1 are output to the adjustable bandwidth active filter, so that the bandwidth of the adjustable bandwidth active filter is changed; when the digital algorithm circuit algorithm is finished, the obtained capacitance control code C _ CTL is obtained by operation<N:0>I.e. N _F And the bandwidth of the obtained active filter is the optimal filter bandwidth insensitive to chip PVT change and aging.

Compared with the prior art, the invention has the following beneficial effects:

the circuit design is universal and has good engineering practicability. The bandwidth-adjustable active filter, the sampling hold circuit, the charge release circuit, the voltage comparator, the D trigger, the clock generation circuit, the frequency synthesizer, the digital algorithm circuit, the NOR gate G0, the time sequence control circuit and the current pulse generation circuit form the bandwidth calibration circuit of the active filter, the circuit design is universal, and the bandwidth calibration circuit has good engineering practicability.

The invention adopts a clock generation circuit to generate a clock CLK _ REF as a reference clock of a frequency synthesizer, and the frequency synthesizer generates a period T according to a frequency control signal _CK In the process of each calibration, the time sequence control circuit generates three clock signals CTL1, CTL2 and CTL3 with the same frequency, the same duty ratio and different phases under the control of a clock CAL _ CLK; the charge releasing circuit releases the capacitance charge of the sampling circuit under the control of a signal CTL3; the sampling holding circuit samples the output of the filter under the control of a signal CTL 1; the current pulse generating circuit generates two constant current pulses with different sizes according to the input control signal CTL2 and the MODE _ SEL and outputs the two constant current pulses to the differential input end of the filter; the bandwidth (or cut-off frequency) deviation caused by chip PVT and aging can be automatically calibrated, and after calibration, the bandwidth of the filter can not be influenced by the chip PVT and aging.

The invention adopts the output voltage of the time domain sampling filter and provides the output voltage to the voltage comparator to be compared with the reference voltage, the digital algorithm circuit adjusts the capacitance of the filter according to the comparison result, two times of calibration are carried out under the control of the algorithm circuit, one capacitance control code is obtained by each time of calibration, and more accurate filter bandwidth insensitive to chip PVT and aging is obtained by operation. The filter can be calibrated or the bandwidth of the filter can be changed at any time under the control of the upper computer, and the filter is flexible to use and wider in application range.

Drawings

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a general circuit block diagram of the active filter bandwidth calibration circuit of the present invention.

FIG. 2 is a timing diagram of the timing control circuit of FIG. 1.

Fig. 3 is a circuit diagram of the current pulse generating circuit of fig. 1.

Fig. 4 is a circuit diagram of the charge discharging circuit of fig. 1.

Fig. 5 is a circuit diagram of the sample-and-hold circuit of fig. 1.

Fig. 6 is a schematic diagram of the tunable capacitor of the filter of fig. 1.

Fig. 7 is a flow chart of the search algorithm of fig. 1.

Fig. 8 is a timing diagram for the control of the algorithm circuit of fig. 1.

Detailed Description

See fig. 1. In a preferred embodiment described below, an active filter bandwidth calibration circuit includes: an adjustable bandwidth active filter coupled between a mixer and a sample-and-hold circuit, a sample-and-hold circuit coupled between the adjustable bandwidth active filter and a voltage comparator, a voltage comparator coupled between the sample-and-hold circuit and a D flip-flop, a charge-discharge circuit coupled between the sample-and-hold circuit and a timing control circuit, a D flip-flop coupled between the voltage comparator and a digital algorithm circuit, a frequency synthesizer coupled between the digital algorithm circuit and a clock generation circuit, a digital algorithm circuit coupled between the frequency synthesizer and the timing control circuit, a nor gate G0 coupled between the digital algorithm circuit and the timing control circuit, a timing control circuit coupled between the digital algorithm circuit and a current pulse generation circuit, a current pulse generation circuit coupled between the timing control circuit and the adjustable bandwidth active filter, characterized in that: the clock generation circuit generates a clock signal CLK _ REF as a reference clock of a frequency synthesizer, and the frequency synthesizer generates a clock signal having a period T according to an externally input frequency control signal _CK Frequency of f _CK The clock signal CLK is sent to a digital algorithm circuit, an enable signal CAL _ PD and a reset signal RESETN output by the digital algorithm circuit are sent to a NOR gate G0 to carry out NOR operation, a signal RST determining the reset of a time sequence control circuit is output and sent to the time sequence control circuit; the time sequence control circuit generates three clock control signals with the same frequency, the same duty ratio and different phases under the control of the output clock CAL _ CLK of the digital algorithm circuitNumbers CTL1, CTL2, and CTL3; the charge releasing circuit releases the capacitance charge of the sampling holding circuit under the control of a signal CTL3; the current pulse generating circuit generates two constant current pulses with different sizes according to an input clock control signal CTL2 and a control signal MODE _ SEL output by the digital algorithm circuit, and outputs the constant current pulses to the differential input end of the bandwidth-adjustable active filter; calibrating different filter Bandwidths (BW) using CLK signals of different frequencies _-3dB,F ) (ii) a In the process of each calibration, the sampling and holding circuit samples the time domain of the output voltage of the bandwidth-adjustable active filter under the control of a signal CTL1, and provides the sampling result to a voltage comparator, and the sampling voltage is compared with a reference voltage; the D flip-flop is connected between the voltage comparator and the digital algorithm circuit in series, latches a comparison result CMPOUT under the control of the rising edge of the signal CTL3, and provides a comparison result signal LT latched in the D flip-flop for the digital algorithm circuit; under the action of a clock signal CLK and a trigger output LT, the digital algorithm circuit carries out calibration search twice, each search traverses each bit of capacitance control code of the bandwidth-adjustable active filter, and the optimal capacitance control code N is obtained by searching respectively _C1 、N _C2 (ii) a When the calibration is finished, the capacitance control codes obtained twice are operated to obtain the final capacitance control code N _F ＝2·N _C2 -N _C1 (ii) a The digital algorithm circuit outputs a signal ST for turning off a front-stage mixer circuit, and changes the size of current pulses of the current pulse generating circuit in twice calibration together with an output control signal MODE _ SEL, an enable signal CAL _ PD provided for the NOR gate G0 and a clock control signal CTL2 output by the time sequence control circuit; capacitance control code C _ CTL generated in two calibration processes<N:0>The adjustable capacitor CP1 and the adjustable capacitor CM1 are output to the adjustable bandwidth active filter, so that the bandwidth of the adjustable bandwidth active filter is changed; when the digital algorithm circuit algorithm is finished, the obtained capacitance control code C _ CTL is obtained by operation<N:0>I.e. N _F And the bandwidth of the obtained active filter is the optimal filter bandwidth insensitive to chip PVT change and aging.

At time 0, when the bandwidth is adjustable as shown in FIG. 1A current pulse + I is applied to the positive end of the differential input end of the active filter _in The negative terminal applies a current pulse-I _in Time of day, TIA filter output voltage

R _f And C _f For the resistance and capacitance of the filter, the TIA low-pass filter is used as an example for the following filter, and the resistances of the resistors RP1 and RM1 are both R _f The capacitance values of the capacitors CP1 and CM1 are both C _f . Let V _O =0, then

Δt＝R _f C _f ln2＝ln2/(2π·BW _-3dB ) The filter output voltage is sampled at time t = Δ t and compared with 0 to determine whether the filter bandwidth is greater than or less than the desired value.

Due to the circuit response delay, the deviation delta tau exists in delta t, so that calibration deviation is caused, in order to eliminate the influence of the deviation delta tau on the calibration precision, twice calibration is adopted, and a final calibration result is obtained through calculation. In the first calibration, a current pulse + I is applied to the positive terminal of the differential input end of the filter _in The negative terminal applies a current pulse-I _in Elapsed time Δ T = T _CK The output voltage of the filter is then sampled and compared with 0, and due to circuit delay, T is actually passed _CK The + Δ τ sample filter output voltage, so T _CK +Δτ＝R _f C _f1 ln2＝ln2/(2π·BW _-3dB,1 ) (ii) a Second calibration, Δ T =2 · T _CK The positive end of the differential input end of the filter applies a current pulse +0.5I _in The negative terminal applies a current pulse-1.5I _in For the same reason, there is 2T _CK +Δτ＝2R _f C _f2 ln2＝2ln2/(2π·BW _-3dB,2 ) Combining the results of the two calibrations, there are

The final bandwidth of the calibrated filter is BW _-3dB,F The filter capacitance which is not influenced by chip PVT, aging and circuit delay and is obtained through calibration is C _F ＝2·C _f2 -C _f1 ，C _f1 Representing the filter capacitance, C, obtained by the first calibration _f2 And represents the filter capacitance value obtained by the second calibration.

The calibration process for the filter bandwidth comprises a first calibration Z ₁ And a second calibration Z ₂ (or first search and second search), for N +1 bit capacitance control code, each search includes X +1 calibration steps, S is used respectively ₀ 、S ₁ 、S ₂ 、S ₃ 、…S _X And (4) showing. The calibration bandwidths are different, and the number X of calibration steps may also be different in each time, so as to ensure that each bit of the capacitance control code of the filter is traversed, and the optimal filter capacitance value is found.

The clock generation circuit generates a clock CLK _ REF as a reference clock of the frequency synthesizer. The frequency synthesizer generates clock signals with different frequencies according to the frequency control signal, and the period of the clock signals is T _CK Frequency of f _CK And the desired bandwidth BW of the filter _-3dB,F Satisfying the frequency f of the clock CLK _CK ＝(2π·BW _-3dB,F ) And/ln 2. That is, if the desired bandwidth BW is to be calibrated _-3dB,F The frequency of the clock CLK required by the digital algorithm module in the digital algorithm circuit is f _CK 。

In each calibration process, the current pulse generating circuit generates two constant current pulses with different sizes according to input control signals CTL2 and MODE _ SEL and outputs the constant current pulses to the differential input end of the filter, and the positive end node VP of the input end of the filter inputs current 2I in the first calibration ₁ VM input Current-2I, negative terminal node ₁ And the positive end node VP input current I of the input end of the filter is calibrated for the second time ₁ The negative side node VM inputs the current-3I ₁ 。

The sample and hold circuit samples the output voltage of the filter and supplies it to the voltage comparator under control of signal CTL 1. The voltage comparator compares the sampled signal with 0. V _NP And V _NM Respectively representing the sampled voltages of the sample and hold circuit on the filter output nodes VOP and VOM. V _NP ＞V _NM When is, i.e. V _NP -V _NM > 0, i.e. the filter output voltage V _O If the voltage is more than 0, the output of the voltage comparator is high level; v _NP ＜V _NM When is, i.e. V _NP -V _NM <0, i.e. the filter output voltage V _O <0, the voltage comparator output is low.

The digital algorithm circuit respectively searches and obtains an optimal capacitance control code N by traversing each bit of the capacitance control code in the two calibration processes under the control of a clock signal CLK according to an input signal LT _C1 、N _C2 (ii) a When the calibration is finished, the capacitance control codes obtained twice are operated to obtain the final capacitance control code N _F ＝2·N _C2 -N _C1 . The digital algorithm circuit output signal ST is used for turning off a preceding circuit (such as a mixer) and avoiding the calibration process from being interfered by the input signal of the preceding circuit; providing a MODE _ SEL signal, and changing the size of a current pulse in two times of calibration by the current pulse generating circuit together with the CTL2 signal; in the first calibration process, the CLK signal is inverted, namely CAL _ CLK, and is output to the time sequence control circuit; in the second calibration process, the CLK is subjected to inverse halving frequency division and then is supplied to the timing control circuit, namely in the second calibration process, the signal CAL _ CLK has twice the signal period of the first calibration process; providing a signal reset signal RESETN and an enable signal CAL _ PD, and determining the reset of the time sequence control circuit through a NOR gate G0; the generated capacitance control code C _ CTL is used in each calibration step of the two calibration processes<N:0>And outputs to filter tunable capacitor CP1 and tunable capacitor CM1, thereby changing the active filter bandwidth.

The nor gate G0 obtains a low-level reset signal of the timing control circuit through nor operation according to a reset signal RESETN and an enable signal CAL _ PD provided by the digital algorithm circuit.

When the NOR gate G0 outputs 0, the timing control circuit outputs synchronous reset at the rising edge of a signal CAL _ CLK, and clock control signals CTL1, CTL2 and CTL3 are all set to be 0; when the nor gate G0 outputs 1, the output of the timing control circuit generates three clock control signals CTL1, CTL2, CTL3 of the same frequency, the same duty ratio, and different phases under the control of the clock CAL _ CLK, the high level duration is equal to two CAL _ CLK cycles, and the low level duration is equal to eight CAL _ CLK cycles. Where clock control signal CTL2 lags clock control signal CTL1 by one CAL _ CLK period, and clock control signal CTL3 lags clock control signal CTL1 by four CAL _ CLK periods. Herein, the digital signal 1 represents a logic high level and 0 represents a logic low level.

See fig. 2. The reset signal RESETN and the enable signal CAL _ PD can reset the timing control circuit after being operated by the nor gate G0, thereby resetting the whole calibration process. When the signal RST =0, the timing control circuit outputs a synchronous reset at the rising edge of CAL _ CLK, and the clock control signals CTL1, CTL2, and CTL3 are all set to 0. When the signal RST =1, the output of the timing control circuit generates three clock control signals CTL1, CTL2, CTL3 of the same frequency, the same duty ratio, and different phases under the control of the clock CAL _ CLK, the high level duration is equal to two CAL _ CLK periods, and the low level duration is equal to eight CAL _ CLK periods. Where clock control signal CTL2 lags clock control signal CTL1 by one CAL _ CLK period, and clock control signal CTL3 lags clock control signal CTL1 by four CAL _ CLK periods.

See fig. 3. The output of the inverter G1 is simultaneously connected with the inputs of the NAND gate G7, the NAND gate G9 and the NAND gate G10, the output of the inverter G2 is connected with the input of the NAND gate G10, the output of the NAND gate G7 is simultaneously connected with the input of the inverter G3 and the grid of the PMOS tube M9, the output of the NAND gate G8 is simultaneously connected with the input of the inverter G4 and the grid of the PMOS tube M8, the output of the NAND gate G9 is simultaneously connected with the input of the inverter G5 and the grid of the PMOS tube M10, and the output of the NAND gate G10 is simultaneously connected with the input of the inverter G6 and the grid of the PMOS tube M11; the outputs of the inverters G3, G4, G5 and G6 are respectively connected with the grids of the NMOS tubes M12, M13, M15 and M14; the grid electrode of the NMOS tube M1 is connected with the drain electrode, and simultaneously connected with the grid electrodes of the NMOS tubes M2, M3 and M4, and the source electrodes of the NMOS tubes M1-M4 are connected; the drain electrode of the NMOS tube M2 is connected with the drain electrode and the grid electrode of the PMOS tube M5, and is simultaneously connected with the grid electrodes of the PMOS tubes M6 and M7, and the source electrodes of the NMOS tubes M5, M6 and M7 are connected; the source electrodes of the PMOS tubes M8 and M9 are connected with the drain electrode of the M6, the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M12, the drain electrode of the PMOS tube M9 is connected with the drain electrode of the NMOS tube M13, and the source electrode of the NMOS tube M12 and the source electrode of the NMOS tube M13 are connected with the drain electrode of the NMOS tube M3; the source electrodes of the PMOS tubes M10 and M11 are connected with the drain electrode of the M7, the drain electrode of the PMOS tube M10 is connected with the drain electrode of the NMOS tube M14, the drain electrode of the PMOS tube M11 is connected with the drain electrode of the NMOS tube M15, and the source electrode of the NMOS tube M14 and the source electrode of the NMOS tube M15 are connected with the drain electrode of the NMOS tube M4. In the current pulse generating circuit, inverters G1-G6 and two input NAND gates G7-G10 form control logic; the NMOS tubes M1, M2, M3 and M4 form a structure 1:1:1:2, the PMOS tubes M5, M6 and M7 form a current mirror 1:1:2, a current mirror; the NMOS transistors M12 to M15 are used as voltage-controlled switches, and are switched on when the grid is at a high level and switched off when the grid is at a low level; the PMOS transistors M8-M11 are used as voltage-controlled switches, and are switched on when the grid electrode is at a low level and switched off when the grid electrode is at a high level. BN, PUP, AN1, and AP2 are output signals of nand gates G7 to G10, respectively, and B, PDN, AP1, and AN2 are output signals of inverters G3 to G6, respectively. In the first calibration, the signal MODE _ SEL is 0; during the second calibration, MODE _ SEL is 1; after the calibration process is started, a signal CAL _ PD is 0; the signal CAL _ PD is 1 before the start and after the end of the calibration process. When the signal CAL _ PD is 1, the signals BN, PUP, AN1, and AP2 are 1, the signals B, PDN, AN2, and AP1 are 0, and the voltage-controlled switches M8 to M15 are all turned off, and no current flows into or out of the node VP and the node VM.

At the first calibration, the signal CAL _ PD =0 and the signal MODE _ SEL =0. When the clock control signal CTL2=1, the signal AN1= AN2= B = PDN =0, the signal AP1= AP2= BN = PUP =1, M10 and M15 are turned on, M8, M9, M11, M12, M13, M14 are turned off, and the current 2I is turned off ₁ Charging node VP via path 1, current 2I ₁ Node VM is discharged via path 2. When the signal CTL2=0, the signal AP1= AP2= B = PDN =0, the signal AN1= AN2= BN = PUP =1, M11 and M14 are on, M8, M9, M10, M12, M13, M15 are off, and the current 2I is off ₁ Discharging node VP via path 1', current 2I ₁ Node VM is charged via path 2'.

At the second calibration, the signal CAL _ PD =0, and the signal MODE _ SEL =1. When the clock control signal CTL2=1, the signal AN1= AN2= BN = PDN =0, and the signal AP1= AP2= BPUP =1, M9, M10, M12, and M15 are on, M8, M11, M13, and M14 are off, and the current 2I ₁ Charging node VP via path 1, current I ₁ The node VP is discharged through the path 3, the two currents are superposed at the node VP, and the result is 2I ₁ -I ₁ ＝I ₁ Charges node VP; at the same time, current 2I ₁ Discharging node VM via path 2, current I ₁ Charging the node VM through the path 4, and superposing the two currents at the node VM to obtain a result of 2I ₁ -I ₁ ＝I ₁ Discharges node VM. When the clock control signal CTL2=0, the signal AP1= AP2= BN = PDN =0, the signal AN1= AN2= B = PUP =1, M9, M11, M12, M14 are turned on, M8, M10, M13, M15 are turned off, and the current I is set to zero ₁ Via path 3, current 2I ₁ Current I is superimposed at node VP via path 1 ₁ +2I ₁ ＝3I ₁ Discharging the node VP; current 2I ₁ Via path 2', current I ₁ Charging the node VM via path 4, resulting in a size of 3I ₁ Charges node VM.

The digital logic circuit can be formed by an equivalent circuit, and the voltage-controlled switches M8-M15 can also be realized by other types of switches, such as transmission gates.

See fig. 4. The charge discharging circuit includes: the grid and the drain of NMOS pipe M8 link to each other, connect the grid of NMOS pipe M9 simultaneously, and M8 and M9 source link to each other, constitute 1:1, a current mirror; the drain electrode of the NMOS tube M9 is connected with the drain electrode and the grid electrode of the PMOS tube M10, and is simultaneously connected with the grid electrode of the PMOS tube M11, and the source electrodes of the NMOS tube M10 and the PMOS tube M11 are connected to form a structure 1:1, a current mirror; the PMOS tube M11 is connected with the voltage dividing resistors RH and RL in series, and a switch K1 and a switch K2 are arranged at the two ends of the voltage dividing resistor RH; releasing the sample-and-hold circuit under the control of the clock control signal CTL3 and the capacitor C _c1 And a capacitor C _c2 Stored charge, constant current I when switches K1 and K2 are off ₂ The voltage flowing through PMOS transistor M11, voltage-dividing resistor RH and resistor RL to ground, and the voltage of node VOH and node VOL is controlled by current I ₂ Current I determined by resistance RH and resistance RL ₂ Is far greater than I ₁ To ensure that the sampling circuit releases the charge of the sampling circuit before the next sampling; when the clock control signal CTL3 is 1, the switches K1 andthe switch K2 is turned on, the current charges the node NM of the sampling circuit through the path 5 (equivalent to releasing negative charges), and the voltage of the node NM rises; node NP is discharged (corresponding to the release of positive charge) through path 6, node NP is lowered in voltage; when the clock control signal CTL3 is 0, the switches K1 and K2 are turned off. The circuit can also be realized by an equivalent circuit, and after charging and discharging, a certain voltage difference is kept between the node VOH and the node VOL. The switches K1 and K2 may be implemented with NMOS, PMOS or transmission gates.

See fig. 5. The sampling hold circuit samples the output voltage of the filter under the action of a clock control signal CTL1, and when the clock control signal CTL1 is 1, the sampling hold circuit is connected to a capacitor C _c1 And a capacitor C _c2 The switch K3 and the switch K4 are turned on, and when the voltage is stable, the node NP and the node VOP at both sides of the switch K3 are equal, and the node NM and the node VOM at both sides of the switch K4 are equal; when the clock control signal CTL1 is 0, the switch K3 and the switch K4 are turned off, and the capacitor C is utilized _c1 And a capacitor C _c2 Node NP and node NM hold the sampled voltages.

See fig. 6. The capacitor CP1 consists of: fixed capacitance value capacitor C _D One end of the filter is connected with the input node VP of the filter, and the other end of the filter is connected with the output node VOM of the filter; capacitor C _i One end of the switch is connected with the input node VP of the filter through the switch KPi, and the other end of the switch is connected with the output node VOM of the filter; two ends of the switch KQi are respectively connected with a capacitor C _i Both ends of (a); control signal C _ CTLDirectly acting on the control terminal of the switch KPi, and controlling the signal C _ CTLAfter passing through the inverter GPi, acts on the control terminal of the switch kwi. i =0,1,2, \ 8230;, N. Capacitor CM1 is formed identically to CP 1. The two ends of capacitor CM1 are connected to nodes VM and VOP, respectively. KP0, KP1, KP2, KP3, \8230, KPN, KQ1, KQ2, KQ3, \8230, KQN are all voltage controlled switches, high level control is conducted, and low level control is cut off. GP0, GP1, GP2, \ 8230and GPN are inverters. When KPi is on, KQi is cut off; when KPi is cut off, KQi is conducted, C _D Is a fixed capacitance. Capacitor C ₀ 、C ₁ 、C ₂ 、C ₃ 、…C _N The filter is switched in (or not) according to the on (or off) of the switch. Wherein, C ₁ ＝2·C ₀ ，C ₂ ＝2 ² ·C ₀ ，C ₃ ＝2 ³ ·C ₀ ，…，C _N ＝2 ^N ·C ₀ 。C ₀ The size of (d) determines the accuracy of the filter bandwidth calibration. Filter bandwidth BW = 1/(2 π R) _f C _f ). When the control code C _ CTL<N:0>When all bits are 1, the maximum capacitance of the filter is C _D +(2 ^N+1 -1)C ₀ . When the control code C _ CTL<N:0>When all bit positions are 0, the minimum capacitance of the filter is C _D Maximum bandwidth BW of filter _-3dB,MAX ＝1/(2πR _f C _D ) Minimum bandwidth BW of filter _-3dB,MIN ＝1/(2πR _f (C _D +(2 ^N+1 -1)C ₀ ))。

See fig. 7. After the circuit is started, the system is reset to an initial state, the signal CAL _ PD and the signal CAL _ CLK are set to be 1, the signal RESETN and the signal MODE _ SEL are set to be 0, and the adjustable capacitance control code C _ CTL < N:0> of the filter is set to be 0 in each position, and then if the signal CAL _ RST is kept to be 0, the system is kept unchanged in the initial state all the time. When the signal CAL _ RST changes from 0 to 1, the system reset is released, and the calibration mode standby state is entered. Thereafter, when CAL _ START changes from 0 to 1, the system enters calibration mode.

Performing first calibration, outputting a clock control signal CLK (clock _ CLK) after inverting the clock control signal CLK and supplying the inverted clock control signal CAL _ CLK to a time sequence control circuit to generate a high level pulse, resetting the time sequence control circuit, starting from [ N/2] +1 bit in the middle of the digital algorithm circuit, searching to a high bit one by one, then searching to a low bit, and executing until the lowest bit C _ CTL <0> of the capacitance control code is traversed, and finishing the first calibration; and then, carrying out second calibration, wherein the signal MODE _ SEL is set to be 1, the signal CLK is subjected to inverse halving and then is output to the time sequence control circuit through the signal CAL _ CLK, the second calibration is similar to the first calibration, the duty ratio of the clock signal CAL _ CLK used in the second calibration is unchanged, but the period is twice of the first calibration, after the second calibration is finished, the final capacitance control code is calculated and output to the filter, the signal CAL _ PD is set to be 1, the clock signal CAL _ CLK is set to be 1, the signal MODE _ SEL is set to be 0, and the digital algorithm circuit algorithm enters the standby state of the calibration MODE again.

Calibration mode onAt first, the signal MODE _ SEL is 0, the system firstly calibrates for the first time, the clock signal CLK is inverted and then is output by the signal CAL _ CLK to be provided for the time sequence control circuit, then the signal RESETN generates a high level pulse, and the time sequence control circuit resets. The capacitance control code is N +1 bits in total, and the digital algorithm circuit is [ N/2] from the middle]Starting with +1 bit, searching to high bit by bit, then searching to low bit, [ N/2]]Indicating rounding down to N/2. The first and second calibrations are performed in X steps, X being a variable integer, up to the lowest bit C _ CTL<0>Is traversed to. With S _j J =0,1,2, \ 8230;, X, representing the jth step of a calibration. At S ₀ Step (2) mixing C _ CTL<[N/2]+1>Set to 1, control code C _ CTL<N:0>Acting on the filter, under the control of a sequential circuit, at S ₀ At the end of the step, the D flip-flop will latch an LT signal, noted LT ⁰ . By LT ^j-1 Is shown at S _j Step S _j-1 When the last signal CTL3 is 1, the D flip-flop latches the output of the comparator. At S ₁ Step, if LT ⁰ =1, denotes at S ₀ At stepped filter capacitances, the filter response is too fast, so at S ₁ The signal C _ CTL<[N/2]+1>CTL at position 0,C _<[N/2]+2>And setting 1, and increasing the capacitance of the filter. At S ₂ If LT is ¹ =1, denotes at S ₁ Given the filter capacitance, the filter response is too fast, so C _ CTL<[N/2]+2>CTL of position 0, C _<[N/2]+3>Put 1, increase the filter capacitance. If LT is ^j-1 Always 1, the algorithm searches straight to the high order.

At a certain step of calibration, e.g. S _j Search algorithm to search high, S _j-1 Highest bit C _ CTL of step capacitance control code<N>Has been set to 1 while LT ^j-1 =1, indicating that the filter capacitance needs to be increased. At the moment, the algorithm changes to increase the filter capacitance to the lower position search to keep the highest position C _ CTL<N>=1, while the next highest C _ CTL bit will be<N-1>And (5) placing 1.

At a certain step of calibration, e.g. S _j Step, searching algorithm is used for searching high order, and the highest order N order is not traversed, if S _j-1 LT obtained at end of step ^j-1 =0, the algorithm switches to lower search with C_CTLCurrent bit representing traversal, C _ CTL<i-1>Bit indicating that the previous step is set to 1, then C _ CTL is performed<i-1>Set 0, C _ CTL<i-2>、C_CTL<i-3>1, placing. In the next step, the algorithm starts from C _ CTL<i-4>Bit start, search bit by bit to the lower bits.

In searching towards lower bits, e.g. S _j Step, once LT appears ^j-1 =1, then the current bit C _ CTL1, placing; if LT is present ^j-1 =0, then the current bit C _ CTLSet 1, raise it by one bit C _ CTL<i+1>And setting 0. Executing until the lowest bit C _ CTL of the capacitance control code<0>Traversed to end the first calibration.

And then, carrying out second calibration, wherein the signal MODE _ SEL is set to be 1, and the signal CLK is subjected to inverse binary frequency division and then is output to the time sequence control circuit by the signal CAL _ CLK. The signal RESETN generates a high level pulse to reset the timing control circuit and then performs a second calibration. The second calibration is similar to the first calibration in that the duty cycle of the clock signal CAL CLK used in the second calibration is constant, but the period is twice that of the first calibration. After the second calibration is finished, the final capacitance control code is calculated and output to the filter, the signal CAL _ PD is set to 1, the clock signal CAL _ CLK is set to 1, the signal MODE _ SEL is set to 0, and the algorithm enters the standby state of the calibration MODE again.

See fig. 8. The algorithm circuit control timing is illustrated in a logic diagram. When the signal CAL _ RST is 0, the calibration circuit is in a reset state, the signal RESETN and the signal MODE _ SEL are both set to 0, and the signal CAL _ CLK and the signal CAL _ PD are both set to 1. When the signal CAL _ RST changes from low to high, the reset ends, and when the signal CAL _ START is 0, the calibration circuit is in the calibration mode standby state. At some point the signal CAL _ START changes from 0 to 1 and the calibration process begins; at the same time, the algorithm circuit enables the preceding stage circuit to be in a closed state through the signal ST. Through n ₁ One CLK cycle, i.e. n ₁ T _CK The inverted signal CLK is output to the timing control circuit by the signal CAL _ CLK. Then passes through time n ₂ T _CK The signal CAL _ PD changes from 1 to 0, and thereafter remains 0 throughout the calibration process until the calibration is completed. After the signal CAL _ PD becomes 0, n passes ₃ T _CK At t ₁ Time of day, signal RESETN is changed from 0 to 1, the time sequence control circuit is reset, and the reset duration is n ₄ T _CK Then, the signal RESETN changes from 1 to 0, the reset ends, and the timing control circuit starts generating the periodic signals CTL1, CTL2, and CTL3 under the control of the signal CAL _ CLK. At t ₂ At that moment, the first calibration is started. The control code of the tunable capacitor of the filter is N +1 bits at t ₃ Time passes by X ₁ Searching in step +1 to obtain the first searched capacitor control code N _C1 And temporarily stored, the signal MODE _ SEL changes from low to high. Elapsed time n ₅ T _CK The signal RESETN changes from 0 to 1, and the high-level holding time is n ₄ T _CK The timing circuit is reset and then the signal RESETN changes from 1 to 0. At t ₄ At which time a second calibration is initiated. During the second calibration, the period of the signal CAL _ CLK is twice as long as during the first search. By X ₂ +1 search, at t ₅ At the moment, the control code N of the other filter capacitor is obtained _C2 While the signal CAL _ PD changes from low to high. Final capacitance control code N _F ＝2·N _C2 -N _C1 . Elapsed time n ₆ T _CK The signal CAL _ CLK is set to 1 and then goes through time n ₇ T _CK The signal MODE _ SEL changes from high to low. The whole calibration process is finished, and the algorithm circuit enables the preceding stage circuit to be in a working state through a signal ST. n is a radical of an alkyl radical ₁ ～n ₇ Are all integers, T _CK Is the period of the clock signal CLK. 0 and 1 in the description denote low and high of digital logic, respectively.

All features disclosed in this specification may be combined in any combination, except features and/or steps that are mutually exclusive. The above preferred embodiments are only intended to illustrate the technical solution of the present invention and not to limit, and although the present invention has been described in detail by the above preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention defined by the claims.

Claims

1. An active filter bandwidth calibration circuit, comprising: connected at a mixer and sample-and-holdAn adjustable bandwidth active filter between circuits, a sample and hold circuit connected between the adjustable bandwidth active filter and a voltage comparator, a voltage comparator connected between the sample and hold circuit and a D flip-flop, a charge release circuit connected between the sample and hold circuit and a timing control circuit, a D flip-flop connected between the voltage comparator and a digital algorithm circuit, a frequency synthesizer connected between the digital algorithm circuit and a clock generation circuit, a digital algorithm circuit connected between the frequency synthesizer and the timing control circuit, a nor gate G0 connected between the digital algorithm circuit and the timing control circuit, a timing control circuit connected between the digital algorithm circuit and a current pulse generation circuit, a current pulse generation circuit connected between the timing control circuit and the adjustable bandwidth active filter, characterized in that: the clock generation circuit generates a clock signal CLK _ REF as a reference clock of a frequency synthesizer, and the frequency synthesizer generates a clock signal with a period T according to an externally input frequency control signal _CK Frequency of f _CK The clock signal CLK is sent to a digital algorithm circuit, an enable signal CAL _ PD and a reset signal RESETN output by the digital algorithm circuit are sent to a NOR gate G0 to carry out NOR operation, and RST determining a reset signal of a time sequence control circuit is output and sent to the time sequence control circuit; the time sequence control circuit generates three clock control signals CTL1, CTL2 and CTL3 with the same frequency, the same duty ratio and different phases under the control of an output clock CAL _ CLK of the digital algorithm circuit; the charge releasing circuit releases the capacitance charge of the sampling holding circuit under the control of a signal CTL3; the current pulse generating circuit generates two constant current pulses with different sizes according to an input clock control signal CTL2 and a control signal MODE _ SEL output by the digital algorithm circuit, and outputs the constant current pulses to the differential input end of the bandwidth-adjustable active filter; calibrating different filter Bandwidths (BW) using CLK signals of different frequencies _-3dB，F ) (ii) a In the process of each calibration, the sampling and holding circuit samples the time domain of the output voltage of the bandwidth-adjustable active filter under the control of a signal CTL1, and provides the sampling result to a voltage comparator, and the sampling voltage is compared with a reference voltage; d connected in series between voltage comparator and digital arithmetic circuitThe trigger latches the comparison result CMPOUT under the control of the rising edge of the signal CTL3 and provides a comparison result signal LT latched in the D trigger to the digital algorithm circuit; under the action of a clock signal CLK and a trigger output LT, the digital algorithm circuit carries out calibration search twice, each search traverses each bit of capacitance control code of the bandwidth-adjustable active filter, and the optimal capacitance control code N is obtained by searching respectively _C1 、N _C2 (ii) a When the calibration is finished, the capacitance control codes obtained twice are operated to obtain the final capacitance control code N _F ＝2·N _C2 -N _C1 (ii) a The digital algorithm circuit outputs a signal ST for turning off a front-stage mixer circuit, and changes the size of current pulses of the current pulse generating circuit in twice calibration together with an output control signal MODE _ SEL, an enable signal CAL _ PD provided for the NOR gate G0 and a clock control signal CTL2 output by the time sequence control circuit; the capacitance control code C _ CTL < N to be generated during the two calibrations: 0 is larger than the adjustable capacitor CP1 and the adjustable capacitor CM1 which are output to the adjustable bandwidth active filter, thereby changing the bandwidth of the adjustable bandwidth active filter; when the digital algorithm circuit algorithm is finished, the capacitance control code C _ CTL obtained by the operation is less than N:0>, i.e. N _F And the bandwidth of the obtained active filter is the optimal filter bandwidth insensitive to chip PVT change and aging.

2. The active filter bandwidth calibration circuit of claim 1, wherein: at the time of 0, when the positive end of the differential input end of the bandwidth-adjustable active filter applies a current pulse + I _in The negative terminal applies a current pulse-I _in Time-of-flight filter differential output voltage

If V _o ＝0，

Δt＝R _f C _f ln2＝ln2/(2π·BW _-3dB ) Then sample filtering at time t = Δ tThe output voltage of the filter is compared with 0 to judge whether the bandwidth of the filter is larger than a desired value or smaller than the desired value, and the bandwidth calibration of the filter can be carried out by using the principle, wherein R _f And C _f The resistance values of the filter and the capacitance values are respectively, and the resistance values of the resistors RP1 and RM1 are both R _f The capacitance values of the capacitors CP1 and CM1 are both C _f 。

3. The active filter bandwidth calibration circuit of claim 1, wherein: in order to eliminate the inaccuracy of the time delta t caused by the delay time delta tau of the circuit, thereby influencing the bandwidth calibration precision, twice calibration is adopted, and the final calibration result is obtained through calculation, wherein in the first calibration, a current pulse + I is applied to the positive end of the differential input end of the filter _in The negative terminal applies a current pulse-I _in Elapsed time Δ T = T _CK Then sampling the output voltage of the filter and comparing with 0, and actually passing through T due to circuit delay _CK The + Δ τ sample filter output voltage, so T _CK +Δτ＝R _f C _f1 ln2＝ln2/(2π·BW _-3dB，1 ) (ii) a Second calibration, Δ T =2 · T _CK The positive end of the differential input end of the filter applies a current pulse +0.5I _in The negative terminal applies a current pulse-1.5I _in For the same reason, there is 2T _CK +Δτ＝2R _f C _f2 ln2＝2ln2/(2π·BW _-3dB，2 ) Combining the results of the two calibrations, including

The final bandwidth of the calibrated filter is BW _-3dB，F The calibrated filter capacitance not affected by chip PVT, aging and circuit delay is C _F ＝2·C _f2 -C _f1 Wherein, C _f1 Representing the filter capacitance, C, obtained by the first calibration _f2 And represents the filter capacitance value obtained by the second calibration.

4. The active filter bandwidth calibration circuit of claim 1, wherein: frequency synthesizer based onThe period of the clock signal with different frequencies generated by the frequency control signal is T _CK Frequency of f _CK And the desired bandwidth BW of the filter _-3dB，F Satisfying the frequency f of the clock CLK _CK ＝(2π·BW _-3dB，F )/ln2。

5. The active filter bandwidth calibration circuit of claim 1, wherein: in the first calibration process, the digital algorithm circuit inverts the CLK signal, namely CAL _ CLK, and outputs the CLK signal to the time sequence control circuit; in the second calibration process, the CLK is subjected to inverse binary frequency division and then is supplied to the time sequence control circuit, namely in the second calibration process, the signal period of the CAL _ CLK is twice that of the signal period in the first calibration process; the digital algorithm circuit provides a reset signal RESETN and an enable signal CAL _ PD, and the reset of the timing control circuit is determined by the NOR gate G0.

6. The active filter bandwidth calibration circuit of claim 1, wherein: when the NOR gate G0 outputs 0, the sequential control circuit outputs synchronous reset at the rising edge of a clock signal CAL _ CLK, and clock control signals CTL1, CTL2 and CTL3 are all set to be 0; when the nor gate G0 outputs 1, the output of the timing control circuit generates three clock control signals CTL1, CTL2, CTL3 of the same frequency, the same duty ratio, and different phases under the control of the clock CAL _ CLK, the high level duration is equal to two CAL _ CLK cycles, and the low level duration is equal to eight CAL _ CLK cycles, wherein the clock control signal CTL2 lags behind the clock control signal CTL1 by one CAL _ CLK cycle, and the clock control signal CTL3 lags behind the clock control signal CTL1 by four CAL _ CLK cycles.

7. The active filter bandwidth calibration circuit of claim 1, wherein: in the current pulse generating circuit, inverters G1-G6 and two input NAND gates G7-G10 form control logic; NMOS transistors M1, M2, M3 and M4 form a current mirror of 1:2, and PMOS transistors M5, M6 and M7 form a current mirror of 1: 2; the NMOS transistors M12 to M15 are used as voltage-controlled switches, and are switched on when the grid is at a high level and switched off when the grid is at a low level; the PMOS transistors M8-M11 are used as voltage-controlled switches, and are switched on when the grid electrode is at a low level and switched off when the grid electrode is at a high level.

8. The active filter bandwidth calibration circuit of claim 1, wherein: the charge discharging circuit includes: the grid electrode of the NMOS tube M8 is connected with the drain electrode, and is simultaneously connected with the grid electrode of the NMOS tube M9, and the source electrodes of the NMOS tube M8 and the NMOS tube M9 are connected to form a 1:1 current mirror; the drain electrode of the NMOS tube M9 is connected with the drain electrode and the grid electrode of the PMOS tube M10, and is simultaneously connected with the grid electrode of the PMOS tube M11, and the source electrodes of the NMOS tube M10 and the PMOS tube M11 are connected to form a 1:1 current mirror; the PMOS tube M11 is connected with the divider resistors RH and RL in series, and a switch K1 and a switch K2 are arranged at the two ends of the divider resistor RH; releasing the sample-and-hold circuit under the control of the clock control signal CTL3 and the capacitor C _c1 And a capacitor C _c2 Stored charge, constant current I when switches K1 and K2 are off ₂ The voltage flowing through PMOS transistor M11, voltage-dividing resistor RH and resistor RL to ground, and the voltage of node VOH and node VOL is controlled by current I ₂ Current I determined by resistance RH and resistance RL ₂ Far greater than I ₁ To ensure that the sampling circuit releases the charge of the sampling circuit before the next sampling; when the clock control signal CTL3 is 1, the switch K1 and the switch K2 are turned on, the current charges the node NM of the sampling circuit through the path 5, negative charges are released, and the voltage of the node NM rises; node NP discharges through path 6, releasing positive charge, and node NP decreases in voltage; when the clock control signal CTL3 is 0, the switches K1 and K2 are turned off.

9. The active filter bandwidth calibration circuit of claim 1, wherein: the sample-and-hold circuit samples the output voltage of the filter under the action of a clock control signal CTL1, and is connected to a capacitor C when the clock control signal CTL1 is 1 _c1 And a capacitor C _c2 The switch K3 and the switch K4 are conducted, when the voltage is stable, the node NP and the node VOP on two sides of the switch K3 are equal, and the node NM and the node VOM on two sides of the switch K4 are equal; when the clock control signal CTL1 is 0, the switch K3 and the switch K4 are turned off, and the capacitor C is utilized _c1 And a capacitor C _c2 Node NP and node NM hold the sampled voltages.

10. The active filter bandwidth calibration circuit of claim 1, wherein: performing first calibration, outputting a clock control signal CLK (clock _ CLK) after inverting the clock control signal CLK and supplying the inverted clock control signal CAL _ CLK to a time sequence control circuit to generate a high level pulse, resetting the time sequence control circuit, starting from [ N/2] +1 bit in the middle of the digital algorithm circuit, searching to a high bit one by one, then searching to a low bit, and executing until the lowest bit C _ CTL <0> of the capacitance control code is traversed, and finishing the first calibration; and then, carrying out second calibration, wherein the signal MODE _ SEL is set to be 1, the signal CLK is subjected to inverse halving and then is output to the time sequence control circuit through the signal CAL _ CLK, the second calibration is similar to the first calibration, the duty ratio of the clock signal CAL _ CLK used in the second calibration is unchanged, but the period is twice of the first calibration, after the second calibration is finished, the final capacitance control code is calculated and output to the filter, the enable signal CAL _ PD is set to be 1, the clock signal CAL _ CLK is set to be 1, the signal MODE _ SEL is set to be 0, and the digital algorithm circuit algorithm enters the standby state of the calibration MODE again.