CN111030630B - Circuit and method for calibrating RC time constant on chip by using switched capacitor - Google Patents
Circuit and method for calibrating RC time constant on chip by using switched capacitor Download PDFInfo
- Publication number
- CN111030630B CN111030630B CN201911237566.5A CN201911237566A CN111030630B CN 111030630 B CN111030630 B CN 111030630B CN 201911237566 A CN201911237566 A CN 201911237566A CN 111030630 B CN111030630 B CN 111030630B
- Authority
- CN
- China
- Prior art keywords
- circuit
- calibration
- comparator
- capacitor
- current mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 95
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000008859 change Effects 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 27
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 2
- 101100446506 Mus musculus Fgf3 gene Proteins 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101150110982 CPR2 gene Proteins 0.000 description 1
- 102100037584 FAST kinase domain-containing protein 4 Human genes 0.000 description 1
- 101001028251 Homo sapiens FAST kinase domain-containing protein 4 Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/06—Frequency selective two-port networks including resistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Networks Using Active Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor, belonging to the field of analog circuit calibration; the circuit comprises an RC filter on-chip resistor and a variable capacitor; and a current mirror, a comparator, a logic control unit, a bias resistor and a switched capacitor circuit; the three PMOS tubes of the current mirror are respectively connected with the bias resistor, the on-chip resistor and one end of the switch capacitor circuit, the drains of the three PMOS tubes of the current mirror are connected with voltage, the on-chip resistor is connected with the positive input end of the comparator, the switch capacitor circuit is connected with the negative input end of the comparator, and the output end of the comparator is connected with the logic control unit; the logic unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitance to be calibrated; the other ends of the bias resistor, the on-chip resistor and the switched capacitor circuit are grounded; the invention can eliminate the influence of parasitic parameters on the calibration precision, furthest improve the calibration precision and flexibly change the calibration target.
Description
Technical Field
The invention belongs to the technical field of analog circuit calibration, and relates to an on-chip RC filter calibration circuit; and more particularly to a circuit and method for calibrating an on-chip RC time constant using switched capacitors.
Background
RC filters are very widely used as one of the most basic circuit elements. The simplest first order RC low pass filter is shown in fig. 1 and consists of a resistor R in series with a capacitor C. Vin is the input voltage signal, vout is the output voltage signal, and the transfer function of the input signal to the output signal can be expressed as V out /V in RC (product) in the equation is called RC time constant, s=jω, j is an imaginary unit
ω is angular frequency (ω=2pi f). For low frequency signals sRC, the input-output small-scale ratio is about 1, that is, the low frequency signals can be transmitted from the input end to the output end through the circuit without obvious attenuation, while for high frequency signals sRC, when sRC is far greater than 1, the ratio of the output-input signals is far less than 1, the signals can be seriously attenuated, and the high frequency signals can hardly reach the output end. The RC time constant thus determines the filtering effect of the filter. The larger the RC time constant, the more frequency band signals will be attenuated, and the smaller the RC time constant, only particularly high frequency signals will be filtered out by the RC filter. In other words, RC time constantThe smaller the filter bandwidth the larger; the larger the RC time constant, the smaller the filter bandwidth. The RC time constant is very important for the filter performance.
SOC (system-on-chip) chips require more and more devices to be integrated onto the same die. Besides transistors, many capacitors and resistors with high requirements are increasingly integrated on the SOC chip, so that the number of off-chip devices can be reduced, and the overall system cost is reduced. In modern advanced CMOS processes with smaller and smaller feature sizes, the on-chip resistor is typically manufactured with a precision of ±20%, and the on-chip capacitor is typically manufactured with a precision of ±10%. The range of capacitance resistance values of such precision is difficult to meet the requirements of critical circuits, especially filters, on RC time constants. Calibration of capacitance and resistance on a chip is an important technique for design.
The chinese patent application No. 20090056373. X shows a calibration circuit and method of an RC filter, as shown in fig. 2. The calibration circuit comprises an amplifier (Amp), a comparator (Comp), a controller (Logic Control), two divider resistors R1, three switches (S1, S2 and S3) and a resistor R and a variable capacitor C of the RC filter; the output end of the amplifier is connected between the resistor R and the capacitor C. The first input of the amplifier is divided by two resistors R1 to generate a reference voltage Vref of VDD/2, and the second input of the amplifier is connected to one end of the resistor R; with amplifier A 0 Feedback through NMOS tube M1 causes the drain voltage of M1 to be equal to Vref, thus the current through resistor R connected to VDD and the drain of M1 tube
I.e., (VDD-Vref)/R, charges the capacitor C with the current during the Tint time, if the voltage of the capacitor C is charged from zero to Vref, i.e., vdd·t/(2r·c) =vref=vdd/2, the output of the comparator will be inverted, so that the capacitor control word C <4:0> can be adjusted by detecting the time of charging the capacitor C to obtain the desired charging time constant, r·c=tint=1/clk, thereby achieving the purpose of calibrating the RC time constant. Clk1 and Clk1n are non-overlapping clocks. Clk1 duty cycle is 50% and period is 2T. The clocks latch, discharge and clk_logic have certain time delay with each other, so that each module is ensured to be established normally.
The chinese patent application No. 20120571778. X shows another RC filter calibration circuit, which is composed of a comparator, a controller, two voltage dividing resistors 1, 2, two switches 4, 5, and a resistor 3 and a capacitor 6 in a chip as shown in fig. 3; the timing diagram for the operation of this circuit is shown in fig. 4. The circuit uses RC charging principle to realize circuit calibration. By connecting the two input terminals of the comparator, one of which is connected between the first resistor 1 and the variable capacitor 6, the other is connected to the reference voltage Vref of the voltage dividing circuit; the charge clock CLKint and the discharge clock CLKdis are used to control the switches 4 and 5 to charge and discharge the variable capacitance, respectively. The basic principle is still that the capacitor 6 is charged by the current of the resistor 3 in the time T, the voltage charged by the capacitor 6 is compared with Vref, the capacitance value is adjusted by using the comparison result, then charging and discharging are performed again, the repeated process of adjusting the control word is continuously performed by charging and discharging- > comparing- > and finally the capacitor 6 is charged by the resistor 3 in the time T, so that the voltage on the capacitor 6 is basically equal to Vref, and the final variable capacitance control word is obtained. The circuit described in this document allows to compare the capacitive node Vint after each charge is completed, with the switch open, by controlling the duty cycle of the clock, the calibration result being directly dependent on the duty cycle of the clock.
The common feature of the above prior art is that the RC time constant information is obtained by charging the variable capacitor of the RC filter at a time and comparing the voltage value to which the capacitor is charged, or directly adjusting the time for which the variable capacitor is charged to the reference voltage, or adjusting the capacitor to reach the reference voltage under the condition of setting the charging time. The common disadvantages are that the dependence on the control clock is high, the jitter of the clock directly affects the calibration result, and the influence of parasitic resistance and parasitic capacitance is difficult to eliminate because the clock is sensitive to parasitic parameters. These all have a negative impact on the accuracy of the calibration.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provides a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor. The invention can calibrate RC time constant composed of capacitance and resistance on chip by using a calibration circuit composed of fewer components, can well eliminate the influence of parasitic parameters on calibration precision, furthest improves the calibration precision, and can flexibly change the calibration target by utilizing different external clock frequencies according to the needs.
The invention provides a circuit for calibrating an on-chip RC time constant by using a switch capacitor, which is characterized by comprising an on-chip resistor Rint of an RC filter, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror formed by three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit formed by a bias resistor R0 and a first PMOS tube M0 of the current mirror together, and a switch capacitor circuit; the sources of the three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drains of the three PMOS tubes of the current mirror are connected with the voltage VDD, and the gates of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; one end of the on-chip resistor Rint connected with the second PMOS tube M1 of the current mirror is connected with the positive input end of the comparator at the same time, one end of the switch capacitor circuit connected with the third PMOS tube M2 of the current mirror is connected with the negative input end of the comparator at the same time, and the output end of the comparator is connected with the logic control unit; the logic control unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitance C1 to be calibrated and is used for adjusting the effective capacitance value of the variable capacitance C1; the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
The invention provides a calibration method based on an upper circuit, which is characterized by comprising the following steps:
1) Starting calibration, powering up and initializing a circuit;
2) Enabling the bias circuit, starting the bias circuit to work, starting the PMOS tube M0 to establish current, and finishing the establishment of the working point of the current mirror when the grid voltage is gradually stabilized; loading an initial value of a capacitor control word; enabling an external non-overlapping clock CLK/CLKB; the circuit enters a charge and discharge working state;
3) The comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) The logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) Repeating the steps 3) to 4), and simultaneously accumulating the comparison times and checking convergence;
6) Judging whether the condition for exiting the calibration cycle is satisfied according to the result obtained in the step 5), if the condition is not converged and the set maximum comparison times are not reached, the calibration exiting condition is not satisfied, and turning to the step 3) to continue the calibration cycle process; if convergence or the preset maximum comparison times are reached, the calibration exit condition is met, and the calibration cycle is ended;
7) Recording and outputting a calibration control word;
8) And (5) ending the calibration.
The invention has the characteristics and beneficial effects that:
the invention is characterized in that: the same current is injected into the on-chip resistor with one end grounded and the equivalent resistor of the switch capacitance circuit with one end grounded by using an equivalent resistor formed by a switch driven by an external non-overlapping clock and a variable capacitor to be calibrated, and the on-chip variable capacitance control word is correspondingly adjusted by comparing the voltages of the on-chip resistor and the variable capacitance circuit with one end grounded, so that the RC time constant is calibrated.
The beneficial effects of the invention are as follows: the calibration circuit is simple; the calibration process is not affected by parasitic parameters of the circuit; the comparator in the calibration process works continuously, so that the influence of the delay of the comparator on the calibration precision is avoided, and the calibration precision and efficiency can be greatly improved; the calibration process is only related to the frequency of an external control clock and is not influenced by the duty cycle and jitter of the clock; the circuit embodiment of the invention avoids the influence of nonideal factors such as current imbalance and the like of the operational amplifier on the calibration precision; the circuit calibration method based on the invention can realize the purpose of calibrating RC constant to different values only by changing the frequency of an external driving clock, has great flexibility and can conveniently realize the requirement of a complex system on-chip RC time constant calibration; meanwhile, the influence of the comparator mismatch on the calibration can be avoided through a comparator chopping and reasonable algorithm.
Drawings
FIG. 1 is a schematic diagram of a conventional RC filter;
FIG. 2 is a schematic diagram of a conventional RC constant calibration circuit;
FIG. 3 is a schematic diagram of another conventional RC constant calibration circuit;
FIG. 4 is a schematic diagram of the operation timing sequence of a conventional RC constant calibration circuit;
FIG. 5 is a schematic diagram showing the basic components of an RC constant calibration circuit according to an embodiment 1 of the present invention;
FIG. 6 is a schematic diagram showing the parasitic parameters of the RC constant calibration circuit of example 1 of the present invention;
FIG. 7 is a flow chart of the RC constant calibration method of the present invention;
FIG. 8 is a schematic diagram of an embodiment 2 of an RC constant calibration circuit of the present invention, showing parasitic resistance and parasitic capacitance.
Detailed Description
The invention provides a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor, which are described in detail below with reference to the accompanying drawings and embodiments:
example 1
The embodiment 1 of the circuit using the RC filter time constant on the switch capacitor calibration chip is shown in fig. 5, and comprises a resistor Rint on the RC filter chip, a variable capacitor C1 formed by a capacitor array and a calibration circuit, wherein the calibration circuit comprises a current mirror formed by three PMOS tubes M0, M1 and M2, a comparator, a logic control unit, a bias circuit formed by a bias resistor R0 and the PMOS tube M0 together, and a switch capacitor circuit formed by the variable capacitor C1 on the chip to be calibrated, switches S1 and S2 and a decoupling capacitor C2 shown in a dotted line frame of fig. 5; the sources (respectively outputting reference current Iref and working currents I1 and I2) of the three NMOS tubes of the current mirror are respectively connected with a bias resistor R0, an on-chip resistor Rint and one end of an equivalent resistor, the drains of the three NMOS tubes of the current mirror are connected with a voltage VDD, and the gates of the three NMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; the on-chip resistor Rint and one end of the equivalent resistor, which is connected with the current mirror, are simultaneously connected with the input end of the comparator, the output end of the comparator is connected with the logic control unit, and the logic control unit outputs a capacitance control code to be connected with the variable capacitor C1 for adjusting the effective capacitance value of the variable capacitor C1;
the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
The switch capacitor circuit is driven by non-overlapping clocks CLK and CLKB, the circuit is composed of a variable capacitor C1, a decoupling capacitor C2 and two switches, wherein a second switch S2 is connected with the variable capacitor C1 in parallel, one end of a first switch S1 is connected with a circuit composed of the second switch S2 and the C1 in parallel in series, the other end of the first switch S1 is grounded, one end of the decoupling capacitor C2 is connected with a circuit composed of the variable capacitor C1, the first switch S1 and the second switch S2 in parallel and then grounded, and the other end of the switch capacitor circuit is connected with a current mirror to be an output end (output voltage V2) of the switch capacitor circuit.
The switch capacitor circuit forms an equivalent resistor R eq ＝1/(f·C 1 )。
The working principle of the circuit is as follows: when S1 is switched on and S2 is switched off, the variable capacitor C1 is charged to the voltage V2, and when S1 is switched off and S2 is switched on, the electricity of C1 is completely discharged, so that the charge transferred from the node V2 to the ground through the variable capacitor C1 in one period is C 1 ·V 2 The amount of charge transferred from the node V2 to the ground per unit time is f.C 1 ·V 2 I.e. the current through the switched capacitor circuit, then the equivalent resistance of this part of the circuit can be obtained as R eq ＝1/(f·C 1 )。
The on-chip resistor Rint and the equivalent resistor circuit are respectively applied with equal current I by a current mirror formed by M1 and M2, and the voltage of the non-grounding terminal of the on-chip resistor Rint is V1 = I-R under the condition that the external non-overlapping clocks CLK and CLKB drive the switched capacitor circuit to work int The voltage of the non-grounding end of the capacitive switch circuit is v2=i·r eq . The comparator compares the voltage V1 with the voltage V2, outputs the comparison result to the logic control unit, and correspondingly adjusts the capacitance control code C by the logic control unit<5:0>The capacitance control code changes the variable capacitance C1The effective capacitance value will change accordingly, the voltage V2 will also change, the process will repeat until the calibration result converges to 1LSB, the output of the calibration is the corresponding control code of the variable capacitance under the specific voltage, temperature and manufacturing process conditions, and the set of control codes can make the product of the on-chip variable capacitance value and the on-chip resistance value under the condition that the control code is applicable be a constant. C at this time<5:0>The value is R int ·C 1 The required capacitance control code of =1/f.
The parasitic resistances Rp1, rp2 of the current mirror and the parasitic capacitances Cpc, cpr of the equivalent, on-chip resistances in the circuit of the invention are shown in fig. 6. The parasitic capacitance value of switch S2 is a few orders of magnitude smaller than the variable capacitance and negligible. Since the bias current is provided by the current mirror, the voltage drop of the parasitic resistors Rp1 and Rp2 does not affect the voltage drop V1 of the on-chip resistor or the voltage drop V2 of the equivalent resistor, and therefore the parasitic resistor does not affect the calibration accuracy; the parasitic capacitance Cpc is connected in parallel with the decoupling capacitance C2, and only plays a role of decoupling with the voltage V2; cpr and on-chip resistor are in parallel connection, do not participate in conduction under the direct current condition, and do not influence the accuracy of calibration at all. These are all significant advantages of the present invention over the prior art.
The on-chip devices adopted by the implementation can be realized by devices provided by common semiconductor manufacturing processes, the devices serving as the current mirrors can be ensured to work in a saturation region, and the adoption of a sleeved tube type structure or other high-precision current mirror designs is more beneficial to the improvement of the consistency of the output current of the current mirrors. The adopted switching device has the leakage current which is 5 orders of magnitude or more smaller than the output current of the current mirror when being turned off so as not to influence the calibration precision, and the RC time constant formed by the on-resistance of the switch and the effective capacitor is required to be 1 order of magnitude or more smaller than the clock period so as to ensure that the charge and discharge processes can be fully balanced.
The logic control unit consists of a digital logic circuit and is used for correspondingly adjusting the capacitance control code according to the output result of the comparator.
The on-chip variable capacitor C1 to be calibrated is a capacitor array controlled by a switch.
Driving ofThe duty cycle of the clock pulse CLK of the switched capacitor circuit need not be exactly 50% and the stabilizing frequency is f. This frequency f determines the calibrated target value R int ·C 1 ＝1/f。
From the description of the structure and mechanism of the present invention, it can be seen that the proposed technique has several advantages over the prior art:
(1) High precision: the structure of the invention can avoid the damage of various error sources to the calibration precision. For example, the use of an operational amplifier is avoided, and errors caused by the loss of an operational amplifier are avoided; the comparator can be in a continuous working mode, so that the influence of the precision mismatch of the comparator can be completely eliminated by using a chopping technology; continuous operation of the comparator can eliminate adverse effects on calibration caused by delays due to parasitic capacitance at the input end of the comparator.
(2) On-line calibration can be achieved. The comparison process can be continuously carried out through the on-chip resistor and variable capacitance copying unit, the logic control circuit can accurately calibrate at any time according to the comparison result, and the corresponding variable capacitance control code can also be updated at any time to furthest follow the change of the working condition of the chip.
(3) Parasitic resistance and parasitic capacitance do not affect the calibration accuracy.
(4) There is no need to externally provide a reference voltage with high accuracy.
(5) There is no high precision duty cycle and low jitter requirement on the clock, only related to the external clock frequency.
(6) The calibration targets are flexible: the calibration target can be flexibly adjusted by adjusting the external non-overlapping clock frequencies, i.e. by applying clocks of different frequencies to calibrate the RC filter to different time constants.
The flow of the calibration method for RC time constant according to the present embodiment 1 is shown in fig. 7, and includes the following steps:
1) Starting calibration, powering up and initializing a circuit;
2) Enabling the bias circuit, starting the bias circuit to work, starting the PMOS tube M0 to establish current, and finishing the establishment of the working point of the current mirror when the grid voltage is gradually stabilized; loading an initial value of a capacitor control word; enabling an external non-overlapping clock CLK/CLKB; the circuit enters a charge and discharge working state;
3) The comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) The logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) Repeating the steps 3) to 4), and simultaneously accumulating the comparison times and checking convergence;
6) Judging whether the condition of exiting the calibration cycle is met or not according to the result obtained in the step 5), if the condition is not converged and the set maximum comparison times are not reached, converting the calibration process into the calibration cycle process in the step 3), and if the condition is converged or the preset maximum comparison times are reached, the calibration exiting condition is met, and ending the calibration cycle;
7) Recording and outputting a calibration control word;
8) And (5) ending the calibration.
The method comprises the following specific implementation steps:
1) Calibration begins;
2) The circuit working point is established, an initial capacitance control code is loaded, the switch capacitance circuit is driven by an external non-overlapping clock CLK/CLKB, and the circuit enters a normal charge and discharge working state;
3) The comparator compares the voltages V1 and V2, and if the voltage V1 is greater than V2, the comparator outputs 1; if the voltage V1< V2, the comparator outputs 0;
4) If the comparator output is 1, the logic control unit adjusts the capacitance control code according to the result to reduce the capacitance effective value, and V2 is correspondingly increased; if the comparator output is 0, the logic control unit increases the effective value of the capacitor by adjusting the control code, and the voltage V2 is correspondingly reduced, so that the voltages V1 and V2 are gradually close; until convergence to 1LSB;
5) Repeating the steps 3) to 4), checking convergence condition and accumulating comparison times;
6) And (3) judging an exit condition: if the output result of the comparator is 1, after the capacitance control code is adjusted next time, the output of the comparator becomes 0, and the output of the comparator becomes 1 again after the capacitance control word is adjusted next time, so that repeated explanation is that the calibration converges to 1LSB, and the calibration exit condition is satisfied; the other exit condition is that the comparison number reaches the preset maximum comparison number (the maximum comparison number is generally set to be more than twice the comparison number required by normal convergence, so that even if the calibration is abnormal, the calibration cycle can be exited, the dead cycle is prevented from happening), and if the comparison number reaches the maximum comparison number, the calibration exit condition is satisfied. If one of the two conditions is met, the calibration process is exited, otherwise, the calibration process continues until the exit condition is met.
7) Recording and outputting a calibration control word;
8) And (5) ending the calibration.
Example two
In another embodiment of the present invention, as shown in fig. 8, the circuit composition of the present embodiment is similar to that of the first embodiment, except that the connection relationship is different, i.e., the output control word of the logic control unit is connected to the on-chip resistor.
The working principle of the embodiment is as follows: when S1 is turned on and S2 is turned off, the variable capacitor C1 is charged to the voltage V2, and when S1 is turned off and S2 is turned on, the charge on C1 is completely discharged, so that the charge transferred from the node V2 to the ground through the variable capacitor C1 in one period is C 1 ·V 2 The amount of charge transferred from the node V2 to the ground per unit time is f.C 1 ·V 2 I.e. the current through the circuit in the dashed box, the equivalent resistance of this part of the circuit can be obtained as R eq ＝1/(f·C 1 )。
The variable resistor Rint2 and the switch capacitor circuit on the chip are respectively applied with current I by a current mirror formed by M1 and M2, and under the condition that the external non-overlapping clocks CLK and CLKB drive the switch capacitor circuit to work stably, the voltage V2 is stable, and then the voltage of the non-grounding end of the capacitor switch circuit is V 2 ＝I·R eq The voltage of the non-grounding terminal of the resistor is V 0 ＝I·R int2 . The comparator compares the voltages V0 and V2, outputs the comparison result to the logic control unit, and the logic control unit adjusts the on-chip resistance control code R accordingly<5:0>Effective value of resistor Rint2Will change accordingly, the voltage V0 will change, this comparison voltage, update the control code, and the comparison process will be repeated until the calibration result converges to 1LSB, at which point R<5:0>The value is R int2 ·C 1 On-chip resistance control code required for =1/f.
In this embodiment, the parasitic resistances Rp1 and Rp2 and the parasitic capacitances Cpc and Cpr2 are shown in fig. 8. The parasitic capacitance of switch S2 is orders of magnitude smaller than variable capacitance C1 and negligible. Because the current mirror provides bias current, the voltage drop on the series parasitic resistor does not affect the voltage drop V0 of the on-chip variable resistor and the voltage drop V2 on the equivalent resistor, and therefore the parasitic resistor does not affect the calibration accuracy; the parasitic capacitance Cpc is connected in parallel with the decoupling large capacitance C2, and only plays a decoupling role together with the voltage V2; cpr2 and the on-chip variable resistor Rint2 are in parallel connection, do not participate in conduction under the stable direct current condition, and do not influence the accuracy of calibration at all. Showing the superiority of the present invention over the prior art.
This embodiment achieves the purpose of calibrating the RC filter time constant by varying the on-chip resistance. All the advantages of the similar embodiment one can be seen: the high-precision on-line calibration can be realized, high-precision reference voltage is not needed, and the parasitic resistance and parasitic capacitance can not influence the calibration precision; no strict requirements on the duty ratio and jitter of the external clock, flexible calibration targets and the like.
The method of this embodiment 2 is the same as that of embodiment 1, and a description thereof will not be repeated.
The same part of calibration circuit in the two embodiments can calibrate different elements by adjusting the frequency of an external clock and changing connection, is not influenced by parasitic parameters, can enable RC calibration design of a complex system to become very efficient, and greatly reduces the design cost of the system.
The description and applications of the present invention are illustrative, and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and component alternatives and equivalents thereof are well known to those of ordinary skill in the art. The present invention may be embodied in other forms, structures, different parameters, different ratios, and with different components and materials without departing from the basic principles and essential characteristics thereof. Variations and modifications of the disclosed embodiments are considered to be part of the present invention, which is within the principles and spirit of the invention.
Claims (5)
1. The circuit is characterized by comprising an RC filter on-chip resistor Rint, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror formed by three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit formed by a bias resistor R0 and a first PMOS tube M0 of the current mirror together, and a switch capacitor circuit; the sources of the three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drains of the three PMOS tubes of the current mirror are connected with the voltage VDD, and the gates of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; one end of the on-chip resistor Rint connected with the second PMOS tube M1 of the current mirror is connected with the positive input end of the comparator at the same time, one end of the switch capacitor circuit connected with the third PMOS tube M2 of the current mirror is connected with the negative input end of the comparator at the same time, and the output end of the comparator is connected with the logic control unit; the logic control unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitance C1 to be calibrated and is used for adjusting the effective capacitance value of the variable capacitance C1; the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
2. The circuit is characterized by comprising an RC filter on-chip resistor Rint, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror formed by three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit formed by a bias resistor R0 and a first PMOS tube M0 of the current mirror together, and a switch capacitor circuit; the sources of the three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drains of the three PMOS tubes of the current mirror are connected with the voltage VDD, and the gates of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; one end of the on-chip resistor Rint connected with the second PMOS tube M1 of the current mirror is connected with the positive input end of the comparator at the same time, one end of the switch capacitor circuit connected with the third PMOS tube M2 of the current mirror is connected with the negative input end of the comparator at the same time, and the output end of the comparator is connected with the logic control unit; the logic control unit outputs a control code of a resistor Rint, and the resistor Rint control code is connected to the resistor Rint to be calibrated and used for adjusting the effective resistance value of the resistor Rint; the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
3. The circuit for calibrating an on-chip RC time constant according to claim 1 or 2, wherein the switched capacitor circuit is driven by non-overlapping clocks CLK and CLKB, the switched capacitor circuit comprises a variable capacitor C1, a decoupling capacitor C2 and two switches, wherein a second switch S2 is connected in parallel with the variable capacitor C1, one end of the first switch S1 is connected in series with a circuit formed by connecting the second switch S2 in parallel with the variable capacitor C1, the other end of the first switch S1 is grounded, one end of the decoupling capacitor C2 is connected in parallel with a circuit formed by connecting the variable capacitor C1, the first switch S1 and the second switch S2, and the other end of the decoupling capacitor C2 is connected with a current mirror to form an output end of the switched capacitor circuit.
4. A method of calibrating a circuit using switched capacitor calibration of an on-chip RC time constant as claimed in claim 1 or 2, comprising the steps of:
1) Starting calibration, powering up and initializing a circuit;
2) Enabling the bias circuit, starting the bias circuit to work, starting the PMOS tube M0 to establish current, and finishing the establishment of the working point of the current mirror when the grid voltage is gradually stabilized; loading an initial value of a capacitor control word; enabling an external non-overlapping clock CLK/CLKB; the circuit enters a charge and discharge working state;
3) The comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) The logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) Repeating the steps 3) to 4), and simultaneously accumulating the comparison times and checking convergence;
6) Judging whether the condition for exiting the calibration cycle is satisfied according to the result obtained in the step 5), if the condition is not converged and the set maximum comparison times are not reached, the calibration exiting condition is not satisfied, and turning to the step 3) to continue the calibration cycle process; if convergence or the preset maximum comparison times are reached, the calibration exit condition is met, and the calibration cycle is ended;
7) Recording and outputting a calibration control word;
8) And (5) ending the calibration.
5. The method of claim 4, wherein,
the step 3) is specifically as follows: the comparator compares the voltages V1 and V2, and if the voltage V1 is greater than V2, the comparator outputs 1; if the voltage V1< V2, the comparator outputs 0;
the step 4) is specifically as follows: if the comparator output is 1, the logic control unit adjusts the capacitance control code according to the result to reduce the capacitance effective value, and V2 is correspondingly increased; if the comparator output is 0, the logic control unit increases the effective value of the capacitor by adjusting the control code, and the voltage V2 is correspondingly reduced, so that the voltages V1 and V2 are gradually close; until convergence is achieved that the difference between V1 and V2 is less than the voltage change caused by the capacitor control word 1LSB;
the step 6) is specifically as follows: and (3) judging an exit condition: if the output result of the comparator is 1, after the capacitance control code is adjusted next time, the output of the comparator becomes 0, and the output of the comparator becomes 1 again after the capacitance control word is adjusted next time, so that repeated explanation is that the calibration converges to 1LSB, and the calibration exit condition is satisfied; the other exit condition is that the comparison times reach the preset maximum comparison times, and if the comparison times reach the maximum comparison times, the calibration exit condition is also met; if one of the two conditions is met, the calibration process is exited, otherwise, the calibration process continues until the exit condition is met.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911237566.5A CN111030630B (en) | 2019-12-06 | 2019-12-06 | Circuit and method for calibrating RC time constant on chip by using switched capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911237566.5A CN111030630B (en) | 2019-12-06 | 2019-12-06 | Circuit and method for calibrating RC time constant on chip by using switched capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111030630A CN111030630A (en) | 2020-04-17 |
| CN111030630B true CN111030630B (en) | 2023-05-05 |
Family
ID=70207321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911237566.5A Active CN111030630B (en) | 2019-12-06 | 2019-12-06 | Circuit and method for calibrating RC time constant on chip by using switched capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111030630B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490751B (en) * | 2020-04-22 | 2023-05-12 | 上海微阱电子科技有限公司 | On-chip resistor self-calibration circuit |
| CN111917293B (en) * | 2020-06-22 | 2021-06-22 | 东南大学 | Switched capacitor DC-DC converter in multi-voltage domain composite feedback mode |
| CN112098795B (en) * | 2020-08-14 | 2023-05-05 | 中国电子科技集团公司第十三研究所 | Two-port on-chip calibration part model and parameter determination method |
| CN113505554B (en) * | 2021-07-05 | 2024-08-16 | 台山市利华电子厂有限公司 | Aging pre-calibration method and system |
| CN114337600B (en) * | 2022-03-11 | 2022-06-03 | 华南理工大学 | On-chip differential active RC filter calibration and tuning method |
| CN114696617B (en) * | 2022-05-30 | 2022-08-16 | 苏州锴威特半导体股份有限公司 | Step-down and push-pull cascade type DC-DC converter and control chip thereof |
| CN116148744B (en) * | 2023-04-17 | 2023-06-20 | 华南理工大学 | Hybrid inductive current sensor capable of being calibrated online and calibration method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN110113028A (en) * | 2019-04-29 | 2019-08-09 | 西安电子科技大学 | Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6134525B2 (en) * | 2012-02-13 | 2017-05-24 | 株式会社メガチップス | Calibration circuit |
-
2019
- 2019-12-06 CN CN201911237566.5A patent/CN111030630B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN110113028A (en) * | 2019-04-29 | 2019-08-09 | 西安电子科技大学 | Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111030630A (en) | 2020-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111030630B (en) | Circuit and method for calibrating RC time constant on chip by using switched capacitor | |
| US8933738B2 (en) | Signal duty cycle detector and calibration system | |
| KR100750650B1 (en) | Tuning circuit | |
| US8552797B2 (en) | High accuracy RC calibradion circuit | |
| US7385453B2 (en) | Precision oscillator having improved temperature coefficient control | |
| US8659362B2 (en) | Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation | |
| CN108023571B (en) | Calibration circuit and calibration method | |
| US8878621B2 (en) | Temperature-compensated semiconductor resistor device | |
| US7239197B2 (en) | Gm-C time constant tuning circuit | |
| KR100633361B1 (en) | Tuning circuit | |
| US20070241832A1 (en) | Programmable precision oscillator | |
| US10868544B2 (en) | Digitally reconfigurable ultra-high precision internal oscillator | |
| US7461285B2 (en) | Programmable resistor array having current leakage control | |
| US7411381B2 (en) | Circuit calibration using a time constant | |
| US8364433B1 (en) | Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters | |
| CN107370463A (en) | A kind of imbalance self-correcting amplifier based on back-gate effect and channel-length modulation | |
| CN113552793B (en) | Self-calibration high-precision digital time conversion circuit | |
| US7548129B2 (en) | On-chip R-C time constant calibration | |
| CN107800435B (en) | Compensation circuit and cancellation method for parasitic effect of capacitor array | |
| CN101330284A (en) | Apparatus for correcting time constant and correlation method thereof | |
| US7924068B2 (en) | Automatic adjustment circuit, and filter circuit | |
| CN118054781B (en) | RC calibration method using digital DLL technology | |
| US12107592B2 (en) | Comparator offset correction | |
| US20240283403A1 (en) | Oscillator circuit device | |
| US20240364357A1 (en) | Methods, systems, and apparatuses for calibrating resistor-capacitor (rc) circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A circuit and method for calibrating on-chip RC time constant using switching capacitors Granted publication date: 20230505 Pledgee: China Minsheng Banking Corp Shenzhen branch Pledgor: SHENZHEN NUORUIXIN TECHNOLOGY Co.,Ltd. Registration number: Y2024980022747 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |