CN107800435B - Compensation circuit and cancellation method for parasitic effect of capacitor array - Google Patents
Compensation circuit and cancellation method for parasitic effect of capacitor array Download PDFInfo
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- CN107800435B CN107800435B CN201711205212.3A CN201711205212A CN107800435B CN 107800435 B CN107800435 B CN 107800435B CN 201711205212 A CN201711205212 A CN 201711205212A CN 107800435 B CN107800435 B CN 107800435B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application belongs to the technical field of electronic circuit design, and particularly relates to a compensation circuit and a cancellation method for parasitic effect of a capacitor array, comprising the following steps: the first sampling switch is connected with the first sampling switch; in the sampling phase, a port switch at the non-inverting input end of the differential circuit and a port switch at the inverting input end of the differential circuit are closed, a second sampling switch and a fourth sampling switch are opened, a first compensation capacitor and a second compensation capacitor are disconnected, and a capacitor array at the non-inverting input end of the differential circuit and a capacitor array at the inverting input end of the differential circuit are charged to generate parasitic capacitance; in the non-sampling phase, a port switch at the non-inverting input end and a port switch at the inverting input end of the differential circuit are opened, a first sampling switch and a third sampling switch are opened, a second sampling switch and a fourth sampling switch are closed, a first compensation capacitor and a second compensation capacitor are charged, and parasitic capacitance generated by the differential circuit in the sampling phase is compensated.
Description
Technical Field
The application belongs to the technical field of electronic circuit design, and particularly relates to a compensation circuit and a cancellation method for parasitic effects of a capacitor array.
Background
The application of a low-power Successive Approximation Register (SAR) analog-to-digital conversion circuit (ADC) is becoming wider and wider, and the SARADC circuit outputs an effective result by using a comparator to generate an effective signal which pushes SAR logic to start the preparation and comparison of the next bit, so that the sampling rate of the circuit can be greatly improved. Currently, SARADC from 10MHz to 100MHz has mass production applications. In order to continuously increase the sampling rate, the capacitance values of the SARADC capacitor array are smaller and smaller, and the minimum unit capacitance is much smaller than 5fF.
Because the unit capacitance of the capacitor array is very small, parasitic effects generated by the charge and discharge of the capacitance, such as parasitic capacitance of a sampling switch tube, parasitic capacitance of a comparator input pair tube and the like, have the influence of the parasitic effects generated by the parasitic capacitances on the charge and discharge of the capacitor array exceeding the weight of the low-order capacitance, and the influence on the sampling signal of the capacitor array cannot be ignored more and more.
Disclosure of Invention
In view of the above, the embodiments of the present application provide a capacitance array parasitic effect compensation circuit and a cancellation method for canceling parasitic capacitance generated by a capacitance array.
A first aspect of an embodiment of the present application provides a compensation circuit for parasitic effects of a capacitor array, applied to a differential circuit, where a non-inverting input terminal of the differential circuit is connected to a first capacitor array, and an inverting input terminal of the differential circuit is connected to a second capacitor array, the compensation circuit includes:
the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch, the fourth sampling switch, the first port switch and the second port switch;
the in-phase signal sampling end of the differential circuit is connected with the first end of the first port switch, and the second end of the first port switch is connected with the in-phase input end of the differential circuit;
the inverted signal sampling end of the differential circuit is connected with the first end of the second port switch, and the second end of the second port switch is connected with the inverted input end of the differential circuit;
the first compensation capacitor and the second sampling switch are connected in series between the first end of the first port switch and the second end of the second port switch, and the first sampling switch is connected in parallel at two ends of the first compensation capacitor;
the second compensation capacitor and the fourth sampling switch are connected in series between the first end of the second port switch and the second end of the first port switch, and the third sampling switch is connected in parallel at two ends of the second compensation capacitor;
in a sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance;
in the non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to offset parasitic capacitance generated by the differential circuit in the sampling phase.
A second aspect of the embodiments of the present application provides a method for counteracting parasitic effects of a capacitive array, where the method includes:
in a sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance;
in the non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to offset parasitic capacitance generated by the differential circuit in the sampling phase. Compared with the prior art, the technical scheme of the embodiment of the application has the beneficial effects that:
the embodiment of the application provides a compensation circuit for parasitic effect of a capacitor array, which comprises: the first sampling switch is connected with the first sampling switch; in the sampling phase, a port switch at the non-inverting input end of the differential circuit and a port switch at the inverting input end of the differential circuit are closed, meanwhile, a second sampling switch and a fourth sampling switch are opened, a first compensation capacitor and a second compensation capacitor are disconnected, and a capacitor array at the non-inverting input end of the differential circuit and a capacitor array at the inverting input end of the differential circuit are charged to generate parasitic capacitance; in the non-sampling phase, a port switch at the non-inverting input end and a port switch at the inverting input end of the differential circuit are opened, meanwhile, a first sampling switch and a third sampling switch are opened, a second sampling switch and a fourth sampling switch are closed, a first compensation capacitor and a second compensation capacitor are charged, and parasitic capacitance generated by the differential circuit in the sampling phase is compensated, so that parasitic capacitance generated by a capacitor array is offset.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a compensation circuit for parasitic effects of a capacitor array according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a capacitor array at the input of a differential circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a differential circuit input capacitor array with a parasitic compensation circuit according to an embodiment of the present application;
FIG. 4 is a circuit diagram of a transmission gate switch structure according to an embodiment of the present application;
FIG. 5 is a graph showing a comparison of output curves of a differential circuit including a capacitor array in a state with and without a compensation circuit according to an embodiment of the present application;
fig. 6 is a flowchart of a method for canceling parasitic effects of a capacitor array according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to illustrate the technical scheme of the application, the following description is made by specific examples.
Referring to fig. 1, a circuit diagram for compensating parasitic effects of a capacitor array according to an embodiment of the present application is provided, and the circuit diagram is applied to a differential circuit, wherein a non-inverting input terminal of the differential circuit is connected to a first capacitor array, and an inverting input terminal of the differential circuit is connected to a second capacitor array, and the circuit diagram includes:
the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch, the fourth sampling switch, the first port switch and the second port switch;
the in-phase signal sampling end of the differential circuit is connected with the first end of the first port switch, and the second end of the first port switch is connected with the in-phase input end of the differential circuit;
the inverted signal sampling end of the differential circuit is connected with the first end of the second port switch, and the second end of the second port switch is connected with the inverted input end of the differential circuit;
the first compensation capacitor and the second sampling switch are connected in series between the first end of the first port switch and the second end of the second port switch, and the first sampling switch is connected in parallel at two ends of the first compensation capacitor;
the second compensation capacitor and the fourth sampling switch are connected in series between the first end of the second port switch and the second end of the first port switch, and the third sampling switch is connected in parallel at two ends of the second compensation capacitor;
in a sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance;
in the non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to offset parasitic capacitance generated by the differential circuit in the sampling phase.
In the embodiment of the application, the differential circuit has two input signals, namely an in-phase input signal and an opposite-phase input signal, the difference value of the two signals, namely the difference value of the in-phase input signal and the opposite-phase input signal is the effective input signal of the differential circuit, and the output of the circuit is the amplification of the difference value of the two input signals.
The differential circuit where the first capacitor array and the second capacitor array are located has a very high operating frequency, so that the first capacitor array and the second capacitor array also need a relatively high sampling rate, and the capacitance values of the first capacitor array and the second capacitor array are relatively small, and are all of fF stages.
The first capacitor array is connected between the non-inverting input end of the differential circuit and the reference voltage VREF of the differential circuit, the first capacitor array comprises a plurality of capacitors, and the size of the sampling total capacitor of the first capacitor array is equal to the sum of the plurality of capacitors.
The second capacitor array is connected between the inverting input end of the differential circuit and the reference voltage VREF of the differential circuit, the second capacitor array comprises a plurality of capacitors, and the size of the sampling total capacitor of the second capacitor array is equal to the sum of the plurality of capacitors.
The first capacitor array and the second capacitor array are arranged at two input ends of the differential circuit, and the first capacitor array sampling total capacitance and the second capacitor array sampling total capacitance are equal in size because of the characteristics of the differential circuit and the operation error is reduced.
Referring to fig. 2, a circuit diagram of a capacitor array at an input end of a differential circuit according to an embodiment of the present application is shown, wherein each stage of capacitors of the first capacitor array and the second capacitor array is added with a capacitor switch, and the capacitor switch is controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit where the differential circuit is located to form a successive approximation switch circuit of the capacitor array. The capacitive switch increases parasitic capacitance generated by sampling and charging the capacitive array.
The first capacitor array samples the total capacitance with the size of C Total (S) ＝C 0 +C 1 +C 2 ......+C n 。
The first capacitor array and the second capacitor array are completely symmetrical and equal, and the series number and the capacitance of each stage of the capacitor arrays are completely consistent.
Further, the differential circuit includes a synchronous sampling differential circuit and an asynchronous sampling differential circuit.
The synchronous sampling differential circuit is also called a tracking sampling differential circuit, namely, the sampling frequency is always kept in a fixed proportion with the actual operating frequency of the circuit at the sampling input end of the differential circuit, so that the sampling frequency is adjusted in real time along with the change of the operating frequency of the system.
The asynchronous sampling differential circuit is also called a timing sampling differential circuit, i.e. the sampling period or sampling frequency is always kept constant at the sampling input of the differential circuit. In this sampling mode, the sampling frequency is not adjusted with the fundamental frequency variation of the analog input signal.
The first capacitor array and the second capacitor array form a successive approximation type capacitor array with sampling control signals, whether the synchronous sampling differential circuit or the asynchronous sampling differential circuit is operated.
Further, please refer to fig. 3, which shows a parasitic effect compensation circuit of the differential circuit input capacitor array according to an embodiment of the present application. The non-inverting input end of the differential circuit is connected with a first capacitor array, the inverting input end of the differential circuit is connected with a second capacitor array, each stage of capacitor of the first capacitor array and the second capacitor array is added with a capacitor switch, and the capacitor switch is controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit where the differential circuit is positioned to form a successive approximation switch circuit of the capacitor array; the compensation circuit includes: the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch, the fourth sampling switch, the first port switch and the second port switch; the in-phase signal sampling end of the differential circuit is connected with the first end of the first port switch, and the second end of the first port switch is connected with the in-phase input end of the differential circuit; the inverting signal sampling end of the differential circuit is connected with the first end of the second port switch, and the second end of the second port switch is connected with the inverting input end of the differential circuit.
In sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit to open the capacitor switches step by step, charge step by step and generate parasitic capacitance.
In a non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, the first capacitor array and the second capacitor array are controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit to charge the first compensation capacitor and the second compensation capacitor step by step, and then the capacitor switches are opened step by step; the parasitic capacitance generated at the sampling phase is cancelled.
According to the parasitic effect compensation circuit of the successive approximation type capacitor array at the input end of the differential circuit, the parasitic capacitance generated by charging the successive approximation type capacitor array in the sampling phase is counteracted by adding one compensation capacitor at each of the two input ends of the differential circuit. The problem that the parasitic effect generated by the successive approximation type capacitor array sampling and charging parasitic capacitance has an influence on the charge and discharge of the capacitor array exceeding the weight of the low-order capacitor is solved.
In the embodiment of the application, two input ends of the differential circuit are respectively a non-inverting input end which is in the same direction as the output end and an inverting input end which is opposite to the output end; in the opposite direction of the connection of the non-inverting input end and the differential circuit, an input port connected with the first capacitor array and the first port switch is a non-inverting signal sampling end; and in the opposite direction of the connection of the inverting input end and the differential circuit, an input port connected with the second capacitor array and the second port switch is an inverting signal sampling end.
In the embodiment of the application, the first port switch, the second port switch, the first sampling switch, the second sampling switch, the third sampling switch and the fourth sampling switch synchronously switch actions; the first port switch, the second port switch, the first sampling switch and the third sampling switch have the same switch actions, the second sampling switch and the fourth sampling switch have the same switch actions, and the first sampling switch and the second sampling switch have opposite actions.
The first port switch, the second port switch, the first sampling switch and the third sampling switch are kept synchronously closed or opened, and the second sampling switch and the fourth sampling switch are kept synchronously and oppositely operated; ensuring that the first compensation capacitor and the second compensation capacitor are both disconnected when the first capacitor array and the second capacitor array are charged in a sampling phase; and the first capacitor array, the second capacitor array, the in-phase signal sampling end and the anti-phase signal sampling end are respectively disconnected in a non-sampling phase, and the first capacitor array and the second capacitor array are respectively discharged to the second compensation capacitor and the first compensation capacitor.
In the embodiment of the application, the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch and the fourth sampling switch are integrated in one circuit unit; or, the first compensation capacitor, the first sampling switch and the second sampling switch are integrated in one circuit unit, and the second compensation capacitor, the third sampling switch and the fourth sampling switch are integrated in one circuit unit.
The first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch and the fourth sampling switch form the compensation circuit, and the compensation circuit is applied to the differential circuit with the capacitor array; the compensation circuit belongs to the integrated digital circuit with the sampling by the differential circuit, so the compensation circuit adopts an integrated circuit mode.
Further, the first compensation capacitor, the first sampling switch and the second sampling switch form a compensation circuit of the second capacitor array, and are integrated in a circuit unit; the second compensation capacitor, the third sampling switch and the fourth sampling switch form a compensation circuit of the first capacitor array, and the compensation circuit is integrated in a circuit unit.
In an embodiment of the present application, the first port switch includes: a single tube switch, a transmission gate switch and a bootstrap switch; the second port switch includes: a single tube switch, a transmission gate switch and a bootstrap switch; the first sampling switch includes: a single tube switch, a transmission gate switch and a bootstrap switch; the second sampling switch includes: a single tube switch, a transmission gate switch and a bootstrap switch; the third sampling switch includes: a single tube switch, a transmission gate switch and a bootstrap switch; the fourth sampling switch includes: a single tube switch, a transmission gate switch and a bootstrap switch;
further, in the successive approximation type capacitor array, the capacitor switch comprises a single tube switch, a transmission gate switch and a bootstrap switch;
the single-tube switch refers to a switch structure which uses a single switch tube as a switch, and can be a PMOS transistor switch, an NMOS transistor switch, an NPN transistor triode switch, a PNP transistor triode switch and the like.
The bootstrap switch comprises a CMOS gate voltage bootstrap switch and a dual-channel MOS gate voltage bootstrap switch; the bootstrap switching circuit has higher linearity than the conventional CMOS/NMOS switching circuit, allows a wider range of input signals, and may even exceed the supply voltage, and thus is widely used in sample-and-hold circuits and conversion circuits.
The transmission gate switch is a controllable switching circuit capable of transmitting both digital and analog signals. For example, a CMOS transmission gate is formed by a PMOS and an NMOS transistor in parallel, which has a very low on-resistance (hundreds of ohms) and a very high off-resistance (greater than 10≡9 ohms).
The first sampling switch and the second sampling switch may adopt a transmission gate switch structure.
Fig. 4 is a circuit diagram of a transmission gate switch structure according to an embodiment of the application. As shown in the figure, a PMOS and an NMOS are connected in parallel, the starting voltages of the two transistors are the same, when the first sampling switch is an NMOS switch tube and the second sampling switch is a PMOS switch tube, the first sampling switch is turned on and the second sampling switch is turned off when the first end voltage is higher than the second end voltage; when the second sampling switch is an NMOS switch tube and the first sampling switch is a PMOS switch tube, the second sampling switch is turned on and the first sampling switch is turned off when the first end voltage is higher than the second end voltage.
The transmission gate switch structure realizes the requirements that the first sampling switch and the second sampling switch synchronously act and have opposite actions, and the same can be applied to the related switch combination such as the third sampling switch and the fourth sampling switch.
Further, a compensation capacitance of a suitable size is the basis for the compensation circuit to realize cancellation of parasitic capacitance generated by the differential circuit at the sampling phase.
The more the successive approximation type capacitor array at the input end of the differential circuit has the number of stages, the larger the parasitic capacitance generated by sampling and charging of the capacitor array is, and the parasitic capacitance is in a proportional relation with the total capacitance of the capacitor array; the size of the first capacitor array is equal to the size of the second capacitor array, and the size of the first compensation capacitor is equal to the size of the second compensation capacitor.
Further, the size of the compensation capacitor is equal to 3-8% of the size of the capacitor array; the size of the first compensation capacitor is equal to 3-8% of the size of the second capacitor array; the size of the second compensation capacitor is equal to 3-8% of the size of the first capacitor array. In an embodiment of the present application, the size of the first compensation capacitor is equal to 5% of the size of the second capacitor array, and the size of the second compensation capacitor is equal to 5% of the size of the first capacitor array.
Referring to fig. 5, a comparison graph of output curves of a differential circuit including a capacitor array in a state with and without a compensation circuit according to an embodiment of the application is shown. As shown in the figure, the reference voltage VREF is 1.0V, and the successive approximation type capacitor array at the input end of the differential circuit comprises an input-output curve with good linearity after the compensation circuit counteracts parasitic capacitance: 0 input, output code 0,1.0V input, output code1023, full width; the output curve of the parasitic capacitance is formed at the input end of the differential circuit without the compensation circuit, and the output reaches full-width code1023 at 95% of the input voltage. This 5% difference is in fact the effect of parasitic capacitance. Capacitive arrayThe total column capacitance is C Total (S) ＝C 0 +C 1 +C 2 ......+C n This 5% of the total capacitance can be regarded as essentially the equivalent of the parasitic capacitance. I.e. cc=c Total (S) X 5% to obtain
Further, referring to fig. 6, a flowchart of a method for canceling parasitic effects of a capacitor array according to an embodiment of the application is shown.
The method for counteracting the parasitic effect of the capacitor array is based on a compensation circuit for the parasitic effect of the capacitor array. The compensation circuit is applied to the differential circuit, the non-inverting input end of the differential circuit is connected with the first capacitor array, and the inverting input end of the differential circuit is connected with the second capacitor array; the compensation circuit includes:
the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch, the fourth sampling switch, the first port switch and the second port switch;
the in-phase signal sampling end of the differential circuit is connected with the first end of the first port switch, and the second end of the first port switch is connected with the in-phase input end of the differential circuit;
the inverted signal sampling end of the differential circuit is connected with the first end of the second port switch, and the second end of the second port switch is connected with the inverted input end of the differential circuit;
the first compensation capacitor and the second sampling switch are connected in series between the first end of the first port switch and the second end of the second port switch, and the first sampling switch is connected in parallel at two ends of the first compensation capacitor;
the second compensation capacitor and the fourth sampling switch are connected in series between the first end of the second port switch and the second end of the first port switch, and the third sampling switch is connected in parallel to two ends of the second compensation capacitor.
The specific counteracting method comprises the following steps:
in step S601, in the sampling phase, the first port switch and the second port switch are closed, and simultaneously, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance.
In the embodiment of the application, the first port switch and the second port switch are closed, and meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit to open the capacitor switches step by step, charge step by step and generate parasitic capacitance.
In step S602, in the non-sampling phase, the first port switch and the second port switch are opened, and simultaneously, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to cancel parasitic capacitance generated by the differential circuit in the sampling phase.
In the embodiment of the application, the first port switch and the second port switch are disconnected, meanwhile, the first sampling switch and the third sampling switch are disconnected, the second sampling switch and the fourth sampling switch are closed, the first capacitor array and the second capacitor array are controlled by a synchronous sampling control circuit or an asynchronous sampling control circuit to charge the first compensation capacitor and the second compensation capacitor step by step, and then the capacitor switches are disconnected step by step; the parasitic capacitance generated at the sampling phase is cancelled.
Further, the size of the first compensation capacitor is equal to the size of the parasitic capacitor generated by charging the second capacitor array; the second compensation capacitor is equal to the parasitic capacitor generated by charging the first capacitor array.
In the embodiment of the present application, the size of the parasitic capacitance generated by the charging of the first capacitor array is equal to 5% of the size of the second capacitor array, and the size of the parasitic capacitance generated by the charging of the second capacitor array is equal to 5% of the size of the first capacitor array.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
The embodiment of the application provides a method for counteracting parasitic effect of a capacitor array, which is applied to a compensation circuit with the parasitic effect of the capacitor array and comprises the following steps: the first sampling switch is connected with the first sampling switch; in the sampling phase, a port switch at the non-inverting input end of the differential circuit and a port switch at the inverting input end of the differential circuit are closed, meanwhile, a second sampling switch and a fourth sampling switch are opened, a first compensation capacitor and a second compensation capacitor are disconnected, and a capacitor array at the non-inverting input end of the differential circuit and a capacitor array at the inverting input end of the differential circuit are charged to generate parasitic capacitance; in the non-sampling phase, a port switch at the non-inverting input end and a port switch at the inverting input end of the differential circuit are opened, meanwhile, a first sampling switch and a third sampling switch are opened, a second sampling switch and a fourth sampling switch are closed, a first compensation capacitor and a second compensation capacitor are charged, and parasitic capacitance generated by the differential circuit in the sampling phase is compensated, so that parasitic capacitance generated by a capacitor array is offset. The method for counteracting the parasitic effect of the capacitor array solves the problem that the influence of the parasitic effect generated by the parasitic capacitance on the charge and discharge of the capacitor array exceeds the weight of the low-order capacitance and the influence on the sampling signal of the capacitor array cannot be ignored more and more.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (9)
1. A compensation circuit for parasitic effects of a capacitor array, the compensation circuit being applied to a differential circuit, wherein a non-inverting input terminal of the differential circuit is connected to a first capacitor array, and an inverting input terminal of the differential circuit is connected to a second capacitor array, the compensation circuit comprising:
the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch, the fourth sampling switch, the first port switch and the second port switch;
the in-phase signal sampling end of the differential circuit is connected with the first end of the first port switch, and the second end of the first port switch is connected with the in-phase input end of the differential circuit;
the inverted signal sampling end of the differential circuit is connected with the first end of the second port switch, and the second end of the second port switch is connected with the inverted input end of the differential circuit;
the first compensation capacitor and the second sampling switch are connected in series between the first end of the first port switch and the second end of the second port switch, and the first sampling switch is connected in parallel at two ends of the first compensation capacitor;
the second compensation capacitor and the fourth sampling switch are connected in series between the first end of the second port switch and the second end of the first port switch, and the third sampling switch is connected in parallel at two ends of the second compensation capacitor;
in a sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance; the first port switch, the second port switch, the first sampling switch and the third sampling switch have the same switching action;
in the non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to offset parasitic capacitance generated by the differential circuit in the sampling phase.
2. The capacitive array parasitic effect compensation circuit of claim 1 wherein,
the first port switch, the second port switch, the first sampling switch, the second sampling switch, the third sampling switch and the fourth sampling switch synchronously switch actions; the second sampling switch and the fourth sampling switch have the same switch action, and the first sampling switch and the second sampling switch have opposite actions.
3. The capacitive array parasitic effect compensation circuit of claim 1 wherein,
the first compensation capacitor, the second compensation capacitor, the first sampling switch, the second sampling switch, the third sampling switch and the fourth sampling switch are integrated in one circuit unit;
or, the first compensation capacitor, the first sampling switch and the second sampling switch are integrated in one circuit unit, and the second compensation capacitor, the third sampling switch and the fourth sampling switch are integrated in one circuit unit.
4. The capacitive array parasitic effect compensation circuit of claim 1 wherein,
the first port switch includes: a single tube switch, a transmission gate switch and a bootstrap switch;
the first sampling switch includes: single tube switches, transmission gate switches, and bootstrap switches.
5. The capacitive array parasitic effect compensation circuit of claim 1 wherein a size of said first compensation capacitor is equal to 3-8% of a size of said second capacitive array.
6. The capacitive array parasitic effect compensation circuit of claim 5, wherein a size of said first compensation capacitor is equal to 5% of a size of said second capacitive array.
7. A method of cancellation of capacitive array parasitics, based on a compensation circuit of capacitive array parasitics as claimed in any one of claims 1 to 6, the method comprising:
in a sampling phase, the first port switch and the second port switch are closed, meanwhile, the second sampling switch and the fourth sampling switch are opened, and the first capacitor array and the second capacitor array are charged to generate parasitic capacitance;
in the non-sampling phase, the first port switch and the second port switch are opened, meanwhile, the first sampling switch and the third sampling switch are opened, the second sampling switch and the fourth sampling switch are closed, and the first compensation capacitor and the second compensation capacitor are charged to offset parasitic capacitance generated by the differential circuit in the sampling phase.
8. The method of claim 7, wherein,
the first compensation capacitor is equal to the parasitic capacitor generated by charging the second capacitor array.
9. The method of claim 8, wherein,
the magnitude of parasitic capacitance generated by the charging of the first capacitive array is equal to 5% of the magnitude of the second capacitive array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711205212.3A CN107800435B (en) | 2017-11-27 | 2017-11-27 | Compensation circuit and cancellation method for parasitic effect of capacitor array |
Applications Claiming Priority (1)
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