CN111030630A - Circuit and method for calibrating on-chip RC time constant by using switched capacitor - Google Patents

Circuit and method for calibrating on-chip RC time constant by using switched capacitor Download PDF

Info

Publication number
CN111030630A
CN111030630A CN201911237566.5A CN201911237566A CN111030630A CN 111030630 A CN111030630 A CN 111030630A CN 201911237566 A CN201911237566 A CN 201911237566A CN 111030630 A CN111030630 A CN 111030630A
Authority
CN
China
Prior art keywords
circuit
calibration
comparator
capacitor
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911237566.5A
Other languages
Chinese (zh)
Other versions
CN111030630B (en
Inventor
陈勇刚
肖玉忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Nuoruixin Technology Co ltd
Original Assignee
Shenzhen Nuoruixin Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Nuoruixin Technology Co ltd filed Critical Shenzhen Nuoruixin Technology Co ltd
Priority to CN201911237566.5A priority Critical patent/CN111030630B/en
Publication of CN111030630A publication Critical patent/CN111030630A/en
Application granted granted Critical
Publication of CN111030630B publication Critical patent/CN111030630B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/06—Frequency selective two-port networks including resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention relates to a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor, belonging to the field of analog circuit calibration; the circuit comprises an on-chip resistor of an RC filter and a variable capacitor; the current mirror, the comparator, the logic control unit, the bias resistor and the switched capacitor circuit are connected; the three PMOS tubes of the current mirror are respectively connected with one end of a bias resistor, an on-chip resistor and a switch capacitor circuit, drain electrodes of the three PMOS tubes of the current mirror are all connected with voltage, the on-chip resistor is connected with a positive input end of a comparator, the switch capacitor circuit is connected with a negative input end of the comparator, and an output end of the comparator is connected with a logic control unit; the logic unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitor to be calibrated; the other ends of the bias resistor, the on-chip resistor and the switched capacitor circuit are all grounded; the invention can eliminate the influence of parasitic parameters on the calibration precision, improve the calibration precision to the maximum extent, and the calibration target can be flexibly changed.

Description

Circuit and method for calibrating on-chip RC time constant by using switched capacitor
Technical Field
The invention belongs to the technical field of analog circuit calibration, and relates to an on-chip RC filter calibration circuit; and more particularly to a circuit and method for calibrating an on-chip RC time constant using a switched capacitor.
Background
The RC filter is widely used as one of the most basic circuit units. The simplest first-order RC low-pass filter is shown in fig. 1 and consists of a resistor R and a capacitor C connected in series. Vin is the input powerThe voltage signal, Vout, is the output voltage signal, and the transfer function of the input signal to the output signal can be expressed as Vout/Vin1/(1+ sRC), RC (product) in the formula is called RC time constant, s is j ω, j is an imaginary unit
Figure BDA0002305299900000011
ω is the angular frequency (ω ═ 2 π f). For low frequency signal sRC term much smaller than 1, the input-output small signal ratio is equal to 1, i.e. the low frequency signal can be transmitted from the input end to the output end through the circuit without obvious attenuation, while for high frequency signal sRC is very large, when sRC is much larger than 1, the output-input signal ratio is much smaller than 1, the signal is severely attenuated, and the high frequency signal can hardly reach the output end. The RC time constant determines the filtering effect of the filter. The larger the RC time constant, the more frequency band signals will be attenuated, and the smaller the RC time constant, only particularly high frequency signals will be filtered by the RC filter. In other words, the smaller the RC time constant, the larger the filter bandwidth; the larger the RC time constant, the smaller the filter bandwidth. The RC time constant is very important to the filter performance.
SOC (system-on-chip) chips require the integration of more and more devices onto the same silicon chip. In addition to transistors, many capacitors and resistors with high requirements are increasingly integrated on the SOC chip, which can reduce the number of off-chip devices and the overall system cost. In modern advanced CMOS processes with smaller and smaller feature sizes, the manufacturing accuracy of on-chip resistors is generally within the range of ± 20%, and the manufacturing accuracy of on-chip capacitors is generally within the range of ± 10%. The range of capacitance and resistance variation with such accuracy is difficult to satisfy the requirements of critical circuits, especially filters, on RC time constants. Calibration of on-chip capacitance resistance becomes an important technology for design.
Chinese patent application No. 200910056373.X shows a calibration circuit and method for an RC filter, as shown in fig. 2. The calibration circuit comprises an amplifier (Amp), a comparator (Comp), a controller (LogicControl), two divider resistors R1, three switches (S1, S2 and S3), and a resistor R and a variable capacitor C of an RC filter; wherein the output of the amplifierThe terminal is connected between the resistor R and the capacitor C. The first input of the amplifier is divided by two resistors R1 to generate a reference voltage Vref of VDD/2, and the second input of the amplifier is connected to one end of the resistor R; by means of amplifiers A0The drain voltage of M1 is equal to Vref by the feedback of an NMOS transistor M1, so that the current of a resistor R connected between VDD and the drain of the M1 transistor
That is, (VDD-Vref)/R, the capacitor C is charged with the current during time Tint, if the voltage of the capacitor C is charged from zero to Vref, i.e., VDD · T/(2R · C) ═ Vref ═ VDD/2, the output of the comparator is inverted, so that the time during which the capacitor C is charged can be detected to adjust the capacitor control word C <4:0> to obtain the desired charging time constant, and R · C ═ Tint ═ 1/clk, thereby achieving the purpose of calibrating the RC time constant. Clk1 is a non-overlapping clock with Clk1 n. Clk1 has a 50% duty cycle and a period of 2T. Certain time delay exists among the clocks latch, discharge and clk _ logic, and the establishment of each module is ensured to be normal.
Chinese patent application No. 201120571778.X discloses another RC filter calibration circuit, which is composed of a comparator, a controller, two voltage dividing resistors 1 and 2, two switches 4 and 5, a resistor 3 in a chip, and a capacitor 6, as shown in fig. 3; the timing diagram of the circuit operation is shown in fig. 4. The circuit utilizes the circuit calibration realized by the RC charging principle. By connecting two input ends of the comparator, one is connected to Vint between the first resistor 1 and the variable capacitor 6, and the other is connected to a reference voltage Vref of the voltage division circuit; the charging clock CLKint and the discharging clock CLKdis are used to control the switches 4 and 5 to charge and discharge the variable capacitor, respectively. The basic principle is that the capacitor 6 is charged by the current of the resistor 3 within the time T, the voltage charged by the capacitor 6 is compared with the Vref, the capacitance value is adjusted by using the comparison result, then the charging and discharging are carried out again, the capacitor 6 is charged by the resistor 3 within the time T through the repeated process of constantly charging and discharging- > comparing- > adjusting the control word, and the voltage on the capacitor 6 is basically equal to the Vref, so that the final variable capacitor control word is obtained. The circuit described in this document can make the comparison with the switches off after the capacitive node Vint is charged each time by controlling the duty cycle of the clock, where the calibration result directly depends on the duty cycle of the clock.
The common feature of the above prior arts is that the RC time constant information is obtained by charging the variable capacitor of the RC filter once and comparing the voltage value of the capacitor charged, or the time of charging the variable capacitor locking capacitor to the reference voltage is directly adjusted, or the capacitor is adjusted to reach the reference voltage under the condition of setting the charging time. The common disadvantage is that the dependence on the control clock is high, the clock jitter directly affects the calibration result, and the influence on parasitic parameters is sensitive, and the influence of parasitic resistance and parasitic capacitance is difficult to eliminate. These can negatively affect the accuracy of the calibration.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provides a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor. The invention can use less components to form a calibration circuit to calibrate the RC time constant formed by the on-chip capacitor resistor, can well eliminate the influence of parasitic parameters on the calibration precision, improves the calibration precision to the maximum extent, and can flexibly change the calibration target by using different external clock frequencies according to the requirements.
The invention provides a circuit for calibrating an on-chip RC time constant by using a switched capacitor, which is characterized by comprising an on-chip resistor Rint of an RC filter, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror formed by three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit formed by a bias resistor R0 and a first PMOS tube M0 of the current mirror, and a switched capacitor circuit; the source electrodes of three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drain electrodes of the three PMOS tubes of the current mirror are all connected with the voltage VDD, and the grid electrodes of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; the on-chip resistor Rint is connected with one end of a second PMOS tube M1 of the current mirror and is connected with the positive input end of the comparator, the switched capacitor circuit is connected with one end of a third PMOS tube M2 of the current mirror and is connected with the negative input end of the comparator, and the output end of the comparator is connected with the logic control unit; the logic unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitor C1 to be calibrated and is used for adjusting the effective capacitance value of a capacitor C1; and the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
The invention provides a calibration method based on an upper circuit, which is characterized by comprising the following steps:
1) starting calibration, powering up and initializing a circuit;
2) enabling the bias circuit, starting the bias circuit to work, starting to establish current by the PMOS tube M0, and finishing establishing a current mirror working point after the grid voltage is gradually stabilized; loading an initial value of a capacitance control word; enabling the external non-overlapping clocks CLK/CLKB; the circuit enters a charge-discharge working state;
3) the comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) the logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) repeating the steps 3) to 4), and meanwhile accumulating the comparison times and checking the convergence condition;
6) judging whether the condition for exiting the calibration cycle is met or not according to the result obtained in the step 5), if the condition is not converged and the set maximum comparison frequency is not reached, the condition for exiting the calibration is not met, and turning to the step 3) to continue the calibration cycle process; if convergence or the preset maximum comparison times are reached, the calibration exit condition is met, and the calibration cycle is ended;
7) recording and outputting a calibration control word;
8) and finishing the calibration.
The invention has the characteristics and beneficial effects that:
the invention is characterized in that: the RC time constant is calibrated by injecting the same current into the on-chip resistor with one end grounded and the equivalent resistor of the switched capacitor circuit with one end grounded through an equivalent resistor formed by a switch driven by an external non-overlapped clock and a variable capacitor to be calibrated, and correspondingly adjusting the control word of the on-chip variable capacitor by comparing the voltages of the on-chip resistor with the equivalent resistor of the switched capacitor circuit with one end grounded.
The invention has the beneficial effects that: the calibration circuit of the invention is simple; the calibration process is not influenced by circuit parasitic parameters; the comparator in the calibration process works continuously, so that the influence of the delay of the comparator on the calibration precision is avoided, and the calibration precision and efficiency can be greatly improved; the calibration process is only related to the frequency of an external control clock and is not influenced by the duty ratio and jitter of the clock; the circuit embodiment of the invention avoids the influence of non-ideal factors of the operational amplifier, such as current offset and the like, on the calibration precision; the calibration method based on the circuit can realize the purpose of calibrating the RC constant to different values only by changing the frequency of the external driving clock, has great flexibility, and can conveniently realize the requirement of a complex system on the calibration of the on-chip RC time constant; meanwhile, the influence of the comparator losing accompanied on calibration can be avoided by the chopper of the comparator and a reasonable algorithm.
Drawings
FIG. 1 is a schematic diagram of a conventional RC filter;
FIG. 2 is a schematic diagram of a conventional RC constant calibration circuit;
FIG. 3 is a schematic diagram of another conventional RC constant calibration circuit;
FIG. 4 is a timing diagram illustrating the operation of a conventional RC constant calibration circuit;
FIG. 5 is a schematic diagram of the basic components of an RC constant calibration circuit in accordance with an embodiment 1 of the present invention;
FIG. 6 is a schematic diagram of the RC constant calibration circuit of embodiment 1 showing the composition of parasitic parameters;
FIG. 7 is a flow chart of the RC constant calibration method of the present invention;
fig. 8 is a schematic diagram of the RC constant calibration circuit of embodiment 2 of the present invention, showing the parasitic resistance and the parasitic capacitance.
Detailed Description
The invention provides a circuit and a method for calibrating an on-chip RC time constant by using a switched capacitor, which are described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
The circuit embodiment 1 for calibrating the on-chip RC filter time constant by using the switched capacitor of the invention is specifically composed as shown in fig. 5, and comprises an on-chip resistor Rint of the RC filter, a variable capacitor C1 composed of a capacitor array and a calibration circuit, wherein the calibration circuit comprises a current mirror composed of three PMOS transistors M0, M1 and M2, a comparator, a logic control unit, a bias circuit composed of a bias resistor R0 and a PMOS transistor M0, and a switched capacitor circuit composed of an on-chip variable capacitor C1 to be calibrated, switches S1 and S2 and a decoupling capacitor C2 and shown in a dashed line frame of fig. 5; the source electrodes (respectively outputting reference current Iref, working current I1 and I2) of three NMOS tubes of the current mirror are respectively connected with one ends of a bias resistor R0, an on-chip resistor Rint and an equivalent resistor, the drain electrodes of the three NMOS tubes of the current mirror are all connected with a voltage VDD, and the grid electrodes of the three NMOS tubes of the current mirror are connected with each other and then connected with a bias resistor R0; the on-chip resistor Rint and one end of the equivalent resistor, which is connected with the current mirror, are simultaneously connected with the input end of the comparator, the output end of the comparator is connected with the logic control unit, and the output capacitance control code of the logic control unit is connected with the variable capacitor C1 and is used for adjusting the effective capacitance value of the capacitor C1;
and the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
The switched capacitor circuit is driven by non-overlapping clocks CLK and CLKB, and the circuit is composed of a first capacitor C1, a decoupling capacitor C2 and two switches, wherein a second switch S2 is connected with the first capacitor C1 in parallel, one end of the first switch S1 is connected with a circuit composed of a second switch S2 and a second switch C1 in parallel in series, the other end of the first switch S1 is grounded, one end of the decoupling capacitor C2 is connected with a circuit composed of a first capacitor C1, a first switch S1 and a second switch S2 in parallel and then grounded, and the other end of the switched capacitor circuit is connected with a current mirror to form an output end (output voltage V2) of the switched capacitor circuit.
The switched capacitor circuit forms an equivalent resistor Req＝1/(f·C1)。
The working principle of the circuit is as follows: when S1 is turned on and S2 is turned off, the capacitor C1 is charged to a voltageV2, when S1 is turned off and S2 is turned on, C1 is completely discharged, so that the charge transferred from node V2 to ground through capacitor C1 in one period is C1·V2The amount of charge transferred from node V2 to ground per unit time is f.C1·V2I.e. the current through the switched capacitor circuit, then the equivalent resistance of this part of the circuit can be obtained as Req＝1/(f·C1)。
The on-chip resistor Rint and the equivalent resistor circuit are respectively applied with equal current I by a current mirror consisting of M1 and M2, and under the condition that the external non-overlapping clocks CLK and CLKB drive the switched capacitor circuit to work, the voltage of the non-grounding end of the on-chip resistor Rint is V1 ═ I.RintThe voltage of the non-grounded terminal of the capacitor switch circuit is V2 ═ I · Req. The comparator compares the voltage V1 with the voltage V2, outputs the comparison result to the logic control unit, and the logic control unit adjusts the capacitance control code C accordingly<5:0>The capacitance control code changes the effective capacitance value of the capacitor C1 and changes accordingly, the voltage V2 changes accordingly, the process is repeated until the calibration result converges to 1LSB, the output of the calibration is the corresponding control code of the variable capacitor under the conditions of specific voltage, temperature and manufacturing process, and the set of control codes can ensure that the product of the on-chip variable capacitance value and the on-chip resistance value under the condition that the control code is applicable is a constant. At this time C<5:0>The value is Rint·C11/f the required capacitance control code.
Fig. 6 shows parasitic resistances Rp1, Rp2 of the current mirror in the circuit of the present invention and parasitic capacitances Cpc, Cpr of the equivalent resistance, on-chip resistance. The parasitic capacitance value of switch S2 is negligibly smaller than the variable capacitance by several orders of magnitude. Because the current mirror provides bias current, the voltage drop of the parasitic resistors Rp1 and Rp2 does not affect the voltage drop V1 of the on-chip resistor and the voltage drop V2 of the equivalent resistor, and therefore the parasitic resistors do not affect the calibration accuracy; the parasitic capacitor Cpc is connected in parallel with the decoupling capacitor C2 and only plays a role of decoupling together with the voltage V2; the Cpr and the on-chip resistor are in parallel connection, do not participate in conduction under the direct current condition, and do not influence the calibration precision at all. These are all significant advantages of the present invention over the prior art.
The on-chip devices adopted by the implementation can be realized by devices provided by common semiconductor manufacturing processes, the devices serving as the current mirrors can be ensured to work in a saturation region, and the consistency of the output current of the current mirrors can be improved by adopting a sleeved barrel type structure or other high-precision current mirror designs. The adopted switch device has the leakage current which is 5 orders of magnitude or more smaller than the output current of the current mirror when the switch device is switched off so as not to influence the calibration precision, and the RC time constant formed by the switch on-resistance and the effective capacitor needs to be 1 orders of magnitude or more smaller than the clock period so as to ensure that the charging and discharging process can be fully balanced.
The logic control unit is composed of a digital logic circuit and is used for correspondingly adjusting the capacitance control code according to the output result of the comparator.
The on-chip variable capacitor C1 to be calibrated is a switch-controlled capacitor array.
The duty cycle of the clock CLK driving the switched capacitor circuit does not have to be exactly 50% and the stable frequency is f. This frequency f determines the target value R of the calibrationint·C1＝1/f。
As can be seen from the description of the structure and mechanism of the present invention, the technology proposed by the present invention has several advantages compared with the prior art:
(1) high precision: the structure of the invention can avoid the damage of a plurality of error sources to the calibration precision. For example, the use of an operational amplifier is avoided, and errors caused by the mismatching of the operational amplifier are avoided; the comparator can be in a continuous working mode, so that the influence of the failure of the precision of the comparator can be completely eliminated by using a chopping technology; the continuous operation of the comparator can eliminate the adverse effect of delay caused by the parasitic capacitance of the input end of the comparator on the calibration.
(2) On-line calibration can be achieved. Through the on-chip resistor and the variable capacitor copying unit, the comparison process in the invention can be continuously carried out, the logic control circuit can carry out accurate calibration at any time according to the comparison result, and the corresponding variable capacitor control code can be updated at any time so as to follow the change of the working condition of the chip to the maximum extent.
(3) Parasitic resistance and parasitic capacitance do not affect calibration accuracy.
(4) There is no need to provide a high precision reference voltage externally.
(5) There is no high precision duty cycle and low jitter requirement for the clock, only in relation to the external clock frequency.
(6) The calibration target is flexible: the calibration target can be flexibly adjusted by adjusting the frequency of the external non-overlapping clocks, i.e. by applying clocks of different frequencies to calibrate the RC filter to different time constants.
Fig. 7 shows a flow of a calibration method based on the RC time constant of this embodiment 1, which includes the following steps:
1) starting calibration, powering up and initializing a circuit;
2) enabling the bias circuit, starting the bias circuit to work, starting to establish current by the PMOS tube M0, and finishing establishing a current mirror working point after the grid voltage is gradually stabilized; loading an initial value of a capacitance control word; enabling the external non-overlapping clocks CLK/CLKB; the circuit enters a charge-discharge working state;
3) the comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) the logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) repeating the steps 3) to 4), and meanwhile accumulating the comparison times and checking the convergence condition;
6) judging whether a condition for exiting the calibration cycle is met or not according to the result obtained in the step 5), if the condition is not converged and does not reach the set maximum comparison time, transferring the calibration cycle to the step 3), continuing the calibration cycle, and if the condition is converged or reaches the preset maximum comparison time, meeting the condition for exiting the calibration and ending the calibration cycle;
7) recording and outputting a calibration control word;
8) and finishing the calibration.
The method comprises the following concrete implementation steps:
1) starting calibration;
2) establishing a circuit working point, loading an initial capacitor control code, driving a switched capacitor circuit by an external non-overlapped clock CLK/CLKB, and enabling the circuit to enter a normal charging and discharging working state;
3) the comparator compares the voltages V1 and V2, and if the voltage V1> V2, the comparator outputs 1; if voltage V1< V2, the comparator outputs 0;
4) if the output of the comparator is 1, the logic control unit adjusts the capacitance control code according to the result to reduce the effective value of the capacitance, and V2 is correspondingly increased; if the output of the comparator is 0, the logic control unit increases the effective value of the capacitor by adjusting the control code, and correspondingly reduces the voltage V2, so that the voltages V1 and V2 are gradually close to each other; until convergence to 1 LSB;
5) repeating the steps 3) to 4), and checking the convergence condition and accumulating the comparison times;
6) and (3) judging an exit condition: if the output result of the comparator is 1, after the capacitance control code is adjusted for the next time, the output of the comparator is changed into 0, the output of the comparator is changed into 1 again when the capacitance control word is adjusted for the next time, so that the calibration is repeatedly explained to converge to 1LSB, and the calibration exit condition is met; the other exit condition is that the comparison number reaches a preset maximum comparison number (the maximum comparison number is generally set to be greater than twice the comparison number required for normal convergence, so that even an abnormal calibration loop can exit to prevent occurrence of a dead loop), and if the comparison number reaches the maximum comparison number, the calibration exit condition is also satisfied. If one of the two conditions is satisfied, the calibration process will exit, otherwise, the calibration process will continue until the exit condition is satisfied.
7) Recording and outputting a calibration control word;
8) and finishing the calibration.
Example two
Fig. 8 shows another embodiment of a calibration circuit of an RC filter, which is similar to the first embodiment, except that the connection relationship is different, that is, the output control word of the logic control unit is connected to the on-chip resistor.
The working principle of the embodiment is as follows: when S1 is turned on and S2 is turned off, the capacitor C1 is charged to V2, and when S1 is turned off and S2 is turned on, the charge on C1 is completedAll discharge is so that the charge transferred from node V2 to ground through capacitor C1 in one cycle is C1·V2The amount of charge transferred from node V2 to ground per unit time is f.C1·V2I.e. the current through the circuit in the dashed box, then the equivalent resistance of this part of the circuit can be obtained as Req＝1/(f·C1)。
The on-chip variable resistor Rint2 and the switched capacitor circuit are applied with current I by a current mirror consisting of M1 and M2, respectively, and under the condition that the external non-overlapping clocks CLK and CLKB drive the switched capacitor circuit to work stably, the voltage V2 is stable, so that the voltage of the non-grounding end of the capacitor switched circuit is V2＝I·ReqThe voltage of the non-grounded terminal of the resistor is V0＝I·Rint2. The comparator will compare the voltages V0 and V2, and output the comparison result to the logic control unit, which will adjust the on-chip resistance control code R accordingly<5:0>The effective value of the resistor Rint2 changes accordingly, the voltage V0 changes, the comparison voltage, the updated control code and the comparison process are continuously executed in a loop until the calibration result converges to 1LSB, and R is the time when the calibration result converges to 1LSB<5:0>The value is Rint2·C11/f the required on-chip resistance control code.
In the present embodiment, the parasitic resistances Rp1 and Rp2 and the parasitic capacitances Cpc and Cpr2 are as shown in fig. 8. The parasitic capacitance of switch S2 is negligibly smaller than the on-chip capacitance C1. Because the current mirror provides bias current, the voltage drop on the series parasitic resistor does not affect the voltage drop V0 of the on-chip variable resistor and the voltage drop V2 on the equivalent resistor, so the parasitic resistor does not affect the calibration precision; the parasitic capacitor Cpc is connected in parallel with the decoupling large capacitor C2 and only plays a role of decoupling together with the voltage V2; cpr2 and the on-chip variable resistor Rint2 are in parallel connection, do not participate in conduction under the condition of stabilizing direct current, and do not influence the calibration accuracy at all. Showing the superiority of the present invention over the prior art.
The embodiment achieves the aim of calibrating the time constant of the RC filter by changing the on-chip resistance. All the advantages of the similar embodiment one can be seen: the calibration method has high precision, can realize online calibration, does not need high-precision reference voltage, and does not influence the calibration precision by parasitic resistance and parasitic capacitance; no strict requirements on the duty ratio and the jitter of an external clock are required, the calibration target is flexible, and the like.
The method of example 2 is the same as that of example 1, and the description thereof will not be repeated.
According to the two embodiments of the invention, different elements can be calibrated by adjusting the frequency of the external clock and changing the connection of the same part of the calibration circuit, and the calibration circuit is not influenced by parasitic parameters, so that the RC calibration design of a complex system becomes very efficient, and the design cost of the system is greatly reduced.
The description and use of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and substitutions of parts and equivalents of the embodiments are well within the skill of those in the art. The present invention may be embodied in other forms, structures, parameters, proportions, and with other components and materials, without departing from the spirit or essential characteristics thereof. Variations and modifications of the disclosed embodiment may be made as part of the present invention, which is also within the spirit and scope of the invention.

Claims (5)

1. A circuit for calibrating an on-chip RC time constant by using a switched capacitor is characterized by comprising an on-chip resistor Rint of an RC filter, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror consisting of three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit consisting of a bias resistor R0 and a first PMOS tube M0 of the current mirror, and a switched capacitor circuit; the source electrodes of three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drain electrodes of the three PMOS tubes of the current mirror are all connected with the voltage VDD, and the grid electrodes of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; the on-chip resistor Rint is connected with one end of a second PMOS tube M1 of the current mirror and is connected with the positive input end of the comparator, the switched capacitor circuit is connected with one end of a third PMOS tube M2 of the current mirror and is connected with the negative input end of the comparator, and the output end of the comparator is connected with the logic control unit; the logic unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitor C1 to be calibrated and is used for adjusting the effective capacitance value of a capacitor C1; and the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
2. A circuit for calibrating an on-chip RC time constant by using a switched capacitor is characterized by comprising an on-chip resistor Rint of an RC filter, an on-chip variable capacitor C1 and a calibration circuit, wherein the calibration circuit comprises a current mirror consisting of three PMOS (P-channel metal oxide semiconductor) tubes, a comparator, a logic control unit, a bias circuit consisting of a bias resistor R0 and a first PMOS tube M0 of the current mirror, and a switched capacitor circuit; the source electrodes of three PMOS tubes of the current mirror are respectively connected with the bias resistor R0, the on-chip resistor Rint and one end of the switch capacitor circuit, the drain electrodes of the three PMOS tubes of the current mirror are all connected with the voltage VDD, and the grid electrodes of the three PMOS tubes of the current mirror are connected with the bias resistor R0 after being connected with each other; the on-chip resistor Rint is connected with one end of a second PMOS tube M1 of the current mirror and is connected with the positive input end of the comparator, the switched capacitor circuit is connected with one end of a third PMOS tube M2 of the current mirror and is connected with the negative input end of the comparator, and the output end of the comparator is connected with the logic control unit; the logic unit outputs a control code of the resistor Rint, and the control code of the resistor Rint is connected to the resistor Rint to be calibrated and used for adjusting the effective resistance value of the resistor Rint; and the bias resistor R0, the on-chip resistor Rint and the other end of the switched capacitor circuit are all grounded.
3. The circuit for calibrating on-chip RC time constant using switched capacitor as claimed in claim 1 or 2, wherein said switched capacitor circuit is driven by non-overlapping clocks CLK and CLKB, and comprises a variable capacitor C1, a decoupling capacitor C2 and two switches, wherein the second switch S2 is connected in parallel with the first capacitor C1, one end of the first switch S1 is connected in series with the circuit formed by the second switch S2 in parallel with the variable capacitor C1, the other end of the first switch S1 is grounded, one end of the decoupling capacitor C2 is connected in parallel with the circuit formed by the first capacitor C1, the first switch S1 and the second switch S2 and then grounded, and the other end is connected with the current mirror as the output terminal of the switched capacitor circuit.
4. A method of calibrating a circuit according to claim 1 or 2, comprising the steps of:
1) starting calibration, powering up and initializing a circuit;
2) enabling the bias circuit, starting the bias circuit to work, starting to establish current by the PMOS tube M0, and finishing establishing a current mirror working point after the grid voltage is gradually stabilized; loading an initial value of a capacitance control word; enabling the external non-overlapping clocks CLK/CLKB; the circuit enters a charge-discharge working state;
3) the comparator compares the voltages V1 and V2, and the judgment result is transmitted to the logic control unit;
4) the logic control unit correspondingly adjusts the capacitance control word according to the output result of the comparator and updates the capacitance control word;
5) repeating the steps 3) to 4), and meanwhile accumulating the comparison times and checking the convergence condition;
6) judging whether the condition for exiting the calibration cycle is met or not according to the result obtained in the step 5), if the condition is not converged and the set maximum comparison frequency is not reached, the condition for exiting the calibration is not met, and turning to the step 3) to continue the calibration cycle process; if convergence or the preset maximum comparison times are reached, the calibration exit condition is met, and the calibration cycle is ended;
7) recording and outputting a calibration control word;
8) and finishing the calibration.
5. The method of claim 4,
the step 3) is specifically as follows: the comparator compares the voltages V1 and V2, and if the voltage V1> V2, the comparator outputs 1; if voltage V1< V2, the comparator outputs 0;
the step 4) is specifically as follows: if the output of the comparator is 1, the logic control unit adjusts the capacitance control code according to the result to reduce the effective value of the capacitance, and V2 is correspondingly increased; if the output of the comparator is 0, the logic control unit increases the effective value of the capacitor by adjusting the control code, and correspondingly reduces the voltage V2, so that the voltages V1 and V2 are gradually close to each other; until it converges that the difference between V1 and V2 is less than the voltage change caused by the capacitance control word 1 LSB;
the step 6) is specifically as follows: and (3) judging an exit condition: if the output result of the comparator is 1, after the capacitance control code is adjusted for the next time, the output of the comparator is changed into 0, the output of the comparator is changed into 1 again when the capacitance control word is adjusted for the next time, so that the calibration is repeatedly explained to converge to 1LSB, and the calibration exit condition is met; the other exit condition is that the comparison times reach the preset maximum comparison times, and if the comparison times reach the maximum comparison times, the calibration exit condition is also met; if one of the two conditions is satisfied, the calibration process exits, otherwise, the calibration process continues until the exit condition is satisfied.
CN201911237566.5A 2019-12-06 2019-12-06 Circuit and method for calibrating RC time constant on chip by using switched capacitor Active CN111030630B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911237566.5A CN111030630B (en) 2019-12-06 2019-12-06 Circuit and method for calibrating RC time constant on chip by using switched capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911237566.5A CN111030630B (en) 2019-12-06 2019-12-06 Circuit and method for calibrating RC time constant on chip by using switched capacitor

Publications (2)

Publication Number Publication Date
CN111030630A true CN111030630A (en) 2020-04-17
CN111030630B CN111030630B (en) 2023-05-05

Family

ID=70207321

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911237566.5A Active CN111030630B (en) 2019-12-06 2019-12-06 Circuit and method for calibrating RC time constant on chip by using switched capacitor

Country Status (1)

Country Link
CN (1) CN111030630B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490751A (en) * 2020-04-22 2020-08-04 上海微阱电子科技有限公司 On-chip resistor self-calibration circuit
CN111917293A (en) * 2020-06-22 2020-11-10 东南大学 Switched capacitor DC-DC converter in multi-voltage domain composite feedback mode
CN112098795A (en) * 2020-08-14 2020-12-18 中国电子科技集团公司第十三研究所 Two-port on-chip calibration piece model and parameter determination method
CN113505554A (en) * 2021-07-05 2021-10-15 广东工业大学 Aging pre-calibration method and system
CN114337600A (en) * 2022-03-11 2022-04-12 华南理工大学 On-chip differential active RC filter calibration and tuning method
CN114696617A (en) * 2022-05-30 2022-07-01 苏州锴威特半导体股份有限公司 Step-down and push-pull cascade type DC-DC converter and control chip thereof
CN116148744A (en) * 2023-04-17 2023-05-23 华南理工大学 Hybrid inductive current sensor capable of being calibrated online and calibration method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656519A (en) * 2009-08-13 2010-02-24 捷顶微电子（上海）有限公司 Calibration circuit of RC filter and method
US20130207711A1 (en) * 2012-02-13 2013-08-15 Kawasaki Microelectronics Inc. Calibration circuit
CN110113028A (en) * 2019-04-29 2019-08-09 西安电子科技大学 Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656519A (en) * 2009-08-13 2010-02-24 捷顶微电子（上海）有限公司 Calibration circuit of RC filter and method
US20130207711A1 (en) * 2012-02-13 2013-08-15 Kawasaki Microelectronics Inc. Calibration circuit
CN110113028A (en) * 2019-04-29 2019-08-09 西安电子科技大学 Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490751A (en) * 2020-04-22 2020-08-04 上海微阱电子科技有限公司 On-chip resistor self-calibration circuit
CN111490751B (en) * 2020-04-22 2023-05-12 上海微阱电子科技有限公司 On-chip resistor self-calibration circuit
CN111917293A (en) * 2020-06-22 2020-11-10 东南大学 Switched capacitor DC-DC converter in multi-voltage domain composite feedback mode
CN111917293B (en) * 2020-06-22 2021-06-22 东南大学 Switched capacitor DC-DC converter in multi-voltage domain composite feedback mode
CN112098795B (en) * 2020-08-14 2023-05-05 中国电子科技集团公司第十三研究所 Two-port on-chip calibration part model and parameter determination method
CN112098795A (en) * 2020-08-14 2020-12-18 中国电子科技集团公司第十三研究所 Two-port on-chip calibration piece model and parameter determination method
CN113505554A (en) * 2021-07-05 2021-10-15 广东工业大学 Aging pre-calibration method and system
CN114337600A (en) * 2022-03-11 2022-04-12 华南理工大学 On-chip differential active RC filter calibration and tuning method
CN114337600B (en) * 2022-03-11 2022-06-03 华南理工大学 On-chip differential active RC filter calibration and tuning method
CN114696617A (en) * 2022-05-30 2022-07-01 苏州锴威特半导体股份有限公司 Step-down and push-pull cascade type DC-DC converter and control chip thereof
CN114696617B (en) * 2022-05-30 2022-08-16 苏州锴威特半导体股份有限公司 Step-down and push-pull cascade type DC-DC converter and control chip thereof
CN116148744A (en) * 2023-04-17 2023-05-23 华南理工大学 Hybrid inductive current sensor capable of being calibrated online and calibration method thereof
CN116148744B (en) * 2023-04-17 2023-06-20 华南理工大学 Hybrid inductive current sensor capable of being calibrated online and calibration method thereof

Also Published As

Publication number Publication date
CN111030630B (en) 2023-05-05

Similar Documents

Publication Publication Date Title
CN111030630B (en) Circuit and method for calibrating RC time constant on chip by using switched capacitor
US7385453B2 (en) Precision oscillator having improved temperature coefficient control
US8552797B2 (en) High accuracy RC calibradion circuit
US8659362B2 (en) Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation
CN108023571B (en) Calibration circuit and calibration method
US6097244A (en) Highly-linear continuous-time filter for a 3-volt supply with PLL-controlled resistor and digitally-controlled capacitor
US20070241832A1 (en) Programmable precision oscillator
CN106788351B (en) Rail-to-rail reference voltage comparator with offset voltage testing and correcting functions
WO2008097400A1 (en) Low-voltage comparator-based switched-capacitor networks
JP2006319985A (en) Tuning circuit
US20200177189A1 (en) Digitally Reconfigurable Ultra-High Precision Internal Oscillator
CN112422106A (en) Comparator for inhibiting offset voltage and method for inhibiting offset voltage of comparator
US7461285B2 (en) Programmable resistor array having current leakage control
US10666235B1 (en) Temperature compensated oscillation circuit
CN115395888A (en) Low-power-consumption high-precision RC oscillator based on cycle detection
WO2021261072A1 (en) Current source circuit and electronic apparatus
CN107370463B (en) Offset self-correction operational amplifier based on back gate effect and channel length modulation effect
CN108111146B (en) Automatic calibration circuit for time constant of active filter
US6903602B2 (en) Calibrated fully differential RC filter
Zhou et al. A 1.6 MHz swing-boosted relaxation oscillator with±0.15%/V 23.4 ppm/° C frequency inaccuracy using voltage-to-delay feedback
US8471630B2 (en) Fast settling reference voltage buffer and method thereof
US8364433B1 (en) Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters
CN101330284B (en) Apparatus for correcting time constant and correlation method thereof
CN107800435B (en) Compensation circuit and cancellation method for parasitic effect of capacitor array
US7548129B2 (en) On-chip R-C time constant calibration

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant