CN114696617A - Step-down and push-pull cascade type DC-DC converter and control chip thereof - Google Patents
Step-down and push-pull cascade type DC-DC converter and control chip thereof Download PDFInfo
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- CN114696617A CN114696617A CN202210598076.3A CN202210598076A CN114696617A CN 114696617 A CN114696617 A CN 114696617A CN 202210598076 A CN202210598076 A CN 202210598076A CN 114696617 A CN114696617 A CN 114696617A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a step-down and push-pull cascade DC-DC converter and a control chip thereof, wherein the converter consists of a starting circuit, a main control circuit, a step-down output driving circuit, a push-pull output circuit, an over-current sampling circuit, a feedback regulating circuit and a plurality of sub-circuits, adopts a cascade double-end topological structure, has the advantages of small volume and high power density, and gives consideration to the limitation of wide-range input and low-voltage heavy current output, the control chip of the main control circuit is a core device of the invention, and comprises a high-voltage starting module, a reference voltage module, an under-voltage locking module, a clock module, a time setting module, a push-pull output module, a step-down output module, a soft starting module, a logic control module, an error amplifier, a PWM (pulse width modulation) comparator and an over-current detection module, and realizes the precise control of two loop control modes of a voltage mode and a current mode and the dead time or the overlapping time of compatible push-pull output signal through the time setting module, thereby increasing the efficiency of the converter.
Description
Technical Field
The invention belongs to the technical field of power conversion, and particularly relates to a step-down and push-pull cascade type DC-DC converter and a control chip thereof.
Background
With the development of modern industry and national defense technology, the technical requirements for the power grade, the voltage grade, the efficiency, the volume, the weight and the like of a high-voltage high-power DC-DC module power supply are continuously improved, which provides new challenges for designers of power supply modules. The double-end topological structure fully utilizes the magnetic core of the transformer, and an additional magnetic core reset circuit is not needed, so that the size of a power supply is reduced, and the double-end topological structure is the optimal topological selection for high-power density application. The single-stage isolated converter hardly meets the requirements of high-voltage input, low-voltage heavy-current output and high power density at the same time, and the cascade topology can well meet the requirements of all aspects.
Disclosure of Invention
In order to achieve the purpose, the invention provides a voltage-reduction and push-pull cascade type current-mode DC-DC converter which has wide input range, high power density and convenient multi-path output, and the technical scheme of the invention is as follows: a step-down and push-pull cascade type current mode DC-DC converter control chip comprises a high-voltage starting module, a reference voltage module, an under-voltage locking module, a clock module, an error amplifier, a PWM comparator, an overcurrent detection module and a logic control module, and further comprises a time setting module, wherein the time setting module comprises: the voltage-current converter comprises an amplifier AMP01, an NMOS transistor N01, an NMOS transistor N02, an NMOS transistor N03, a PMOS transistor P01, a PMOS transistor P02, a PMOS transistor P03 and a resistor RTIMERealize the external resistor RTIMEAdjusting internal charging and discharging current; the time setting circuit comprises an inverter INV01, an inverter INV02, an inverter INV03, an inverter INV04, an inverter INV05, an amplifier AMP02, an amplifier AMP03, a capacitor C _ PUSH, a capacitor C _ PULL, and a PMThe OS tube P04, the PMOS tube P05, the NMOS tube N04 and the NMOS tube N05 form the setting of dead time or overlapping time; externally connected resistor R of TIME pinTIMEBy means of an internal time setting module and a resistor RTIMETo be compatible with both voltage and current loop control modes.
In the voltage-current converter, an inverting input end of an amplifier AMP01 is connected with a TIME pin and an output end thereof, an output end thereof is connected with drain ends of a PMOS tube P01 and an NMOS tube N01, a source end of a PMOS tube P01 is connected with a source end of a PMOS tube P02 and a source end of a PMOS tube P03, a gate end of the PMOS tube P01 is connected with a gate end of a PMOS tube P02 and a gate end of a PMOS tube P03, a gate end and a drain end of the PMOS tube P01 are connected, a gate end of the NMOS tube N01 is connected with a gate end of an NMOS tube N02 and a gate end of an NMOS tube N03, a source end of an NMOS tube N01 is connected with a source end of an NMOS tube N02 and a source end of an NMOS tube N03, a gate end and a drain end of the NMOS tube N01 are connected, a drain end of the PMOS tube P02 generates a current I _ OT 6, a drain end of the NMOS tube N02 generates a current I _ DT1, a drain end of the PMOS tube P03 generates a drain end of an NMOS tube DT2, and a drain end of the NMOS tube P6474 generates a drain end of the NMOS tube DT 2.
As an improvement of the invention, in the time setting circuit, the input end of the inverter INV02 is connected with the signal CLK, the grid end of the NMOS tube N04 and the grid end of the PMOS tube P04, the output end of the inverter INV02 is connected with the grid ends of the PMOS tube P05 and the NMOS tube N05, the drain end of the PMOS tube P04 is connected with the drain end of the NMOS tube N04, the output end of the inverter INV01 and the inverting input end of the amplifier AMP02, the source end of the PMOS tube P04 is connected with the current I _ OT1, the source end of the NMOS tube N04 is connected with the current I _ DT1, the source end of the PMOS tube P05 is connected with the current I _ OT2, the drain end of the PMOS tube P05 is connected with the drain end of the NMOS tube N05, the output end of the inverter INV03 and the inverting input end of the amplifier AMP03, the inverting input end of the NMOS tube N05 is connected with the current I _ DT2, the non-phase input end of the amplifier 02 is connected with the inverting input end of the capacitor AMP Vref, the inverting input end of the capacitor AMP 28 is connected with one end of the capacitor SH, the inverting input end of the capacitor AMP 42 and the inverting input end of the PMOS tube Vref, the other end of the capacitor C _ PULL is grounded, the output end of the amplifier AMP02 is connected with the input end of the inverter INV04, and the output end of the amplifier AMP03 is connected with the input end of the inverter INV 05.
As an improvement of the invention, the current mirror proportionality coefficients formed by an NMOS tube N01, an NMOS tube N02, an NMOS tube N03, a PMOS tube P01, a PMOS tube P02 and a PMOS tube P03 are all 1: 1,
wherein I _ OT1= I _ OT2= I _ DT1= I _ DT2= (VREF/2)/RTIME，
Dead time Δ T1= [ C _ PUSH = (V)REF/2)]/I_DT1，
Overlap time Δ T2= [ C _ PUSH = (V)REF/2)]/I_OT1。
Taking the overlap time as an example, the resistance RTIMEOne end of the voltage follower is grounded, the other end is connected with the TIME pin, and the output signal of the voltage follower formed by the operational amplifier AMP01 is at the resistor RTIMEThe constant pair of ground current is formed, the current signals are conducted to the drain terminals of P04 and P05 by a current mirror formed by PMOS tubes P01, P02 and P03, a delay circuit is formed by the current mirror and the capacitors C _ PUSH and C _ PULL, and a group of pulse signals PUSH _ IN and PULL _ IN with fixed overlapping time are generated.
A step-down and push-pull cascade DC-DC converter comprises a main control circuit of the converter, wherein the main control circuit comprises the chip U1, a resistor R1, a resistor R2 and a resistor RRTResistance RTIMECapacitor CSSAnd a capacitor CREFThe HD pin of the chip U1 is connected with the IH pin of the chip U2, the LD pin of the chip U1 is connected with the IL pin of the chip U2, the PUSH pin of the chip U1 is connected with the gate end of the NMOS tube N3, one end of the resistor R1 is connected with the end of the transformer T1 primary winding LP1 with the same name, the other end is connected with the resistor R2 and the UVLO pin of the chip U1, and the resistor R1 is connected with the UVLO pin of the transformer T1RTRT pin and resistor R of chip U1TIMEA TIME pin and a capacitor C connected with the chip U1SSAn SS pin and a capacitor C of the chip U1 are connectedREFThe REF pin of chip U1 is connected.
As an improvement of the present invention, the control chip U1 generates the buck driving signals HD and LD, the PUSH-PULL output signals PUSH and PULL, the waveforms of the buck driving signals HD and LD are completely complementary, the phase difference is 180 DEG, the frequency is identical to the internal clock signal, the PUSH-PULL output signals PUSH and PULL are 50% duty ratio PWM signals, the frequency is half of the internal clock signal, and the dead time or the overlap time is kept fixed under different control modes.
Based on the technical scheme, the voltage divider formed by the resistor R1 and the resistor R2An undervoltage protection input signal that will provide line voltage; rRTThe frequency of the built-in oscillator can be set; rTIMECan be through to ground or to REFThe legs are connected to set the length of overlapping or dead time, so as to ensure the stable operation of the converter under various control modes; cSSThe time for the system to start can be set; cREFCan be REFStabilize the transient voltage and reduce the ripple.
As an improvement of the present invention, the converter further comprises:
a voltage-reducing output drive circuit, which comprises a chip U2, a capacitor C3, a capacitor C4, an inductor L1, an NMOS tube N1 and an NMOS tube N2, wherein a VCC pin of the chip U2 is connected with VDD, the capacitor C3 is connected with a VDD pin of the chip U2, one end of the capacitor C4 is connected with a HB pin of the chip U2, the other end of the capacitor C4 is connected between a HS pin of the chip U2 and a drain terminal of the NMOS tube N2 and the inductor L1, a gate terminal of the NMOS tube N1 is connected with an HO pin of the chip U2, a source terminal of the NMOS tube C4 is connected with the drain terminal of the NMOS tube N2 and one end of the inductor L1, the drain terminal of the NMOS tube N1 is connected with a same name terminal of a primary winding LP1 of a transformer T1, a gate terminal of the NMOS tube N2 is connected with an LO pin of the chip U2, and a source terminal of the VSS pin of the chip U2 and the ground;
the PWM signals HD and LD generated by the control chip U1 are input into the chip U2, and then the NMOS transistor N1 and the NMOS transistor N2 (driving power transistor) are inverted, and the voltage generated after passing through the inductor L1 supplies power to the post-stage push-pull topology, where the voltage V _ L1= VIN × D, and D is the duty ratio of HD. The capacitor C3 is used as a decoupling capacitor for filtering noise waves of VCC, and the capacitor C4 is a high-voltage capacitor for supplying power to the chip U2.
The push-pull output circuit comprises a transformer T2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6 and a capacitor COUTThe dotted end of the primary winding LP2 of the transformer T2 is connected with the dotted end of the primary winding LP3, the dotted end of the primary winding LP2 is connected with the drain end of an NMOS tube N4, the source end of an NMOS tube N4 is grounded, the gate end of the NMOS tube N4 is connected with the PULL pin of a chip U1, a control signal of the gate end of the NMOS tube N4 is generated by the PUSH pin, the dotted end of the primary winding LP3 of the transformer T2 is connected with one side of an inductor L1, the dotted end of the primary winding LP3 is connected with the drain end of the NMOS tube N3, the source end of the NMOS tube N3 is grounded, and the dotted end of the secondary winding LS2 of the transformer T2 is connected with the drain end of the NMOS tube N6 and the drain end of the NMOS tube N65, the synonym end of the secondary winding LS2 is connected with the synonym end of the secondary winding LS3, the synonym end of the secondary winding LS3 of the transformer T2 is connected with the VOUT end, the synonym end of the secondary winding LS3 is connected with the drain end of the NMOS tube N5 and the gate end of the NMOS tube N6, and the capacitor COUTOne end of the secondary winding LS3 is connected to the same name of the secondary winding LS3, and the other end of the secondary winding LS3 is grounded. The primary winding LP2 and the secondary winding LS2 form a transformer, the primary winding LP3 and the secondary winding LS3 form a transformer, and the two transformers share one magnetic core.
The push-pull signal of the chip U1 directly drives the NMOS transistor N3 and the NMOS transistor N4, the positive pole transformer T2 consists of five windings, wherein a primary winding LP2, a primary winding LP3, a secondary winding LS2 and a secondary winding LS3 participate in power conversion from input voltage to output voltage, and LS is connected with the power converterAUXThe auxiliary winding is specially used for supplying power for the control chip. The output of the transformer is rectified by a rectifying circuit composed of an NMOS tube N5 and an NMOS tube N6, and then the pair C is connectedOUTCharging is performed while outputting the voltage signal VOUT.
Based on the technical scheme, a VCC pin of the chip U1 generates a power supply signal VCC in the starting stage, and the power supply is supplied to the U2 through a VDD pin of the U2; and after starting, the auxiliary winding LSAUXThe output voltage is rectified by a diode D2 to generate a power supply VCC, and the power supply VCC supplies power to the chip U1 and the chip U2.
As a modification of the present invention, the converter further includes a start circuit including a resistor R3, a capacitor C1, a capacitor C2, a capacitor C5, a diode D2, and an auxiliary winding LSAUXOne end of a resistor R3 is connected with the same name end of a primary winding LP1 of the transformer T1, the other end of the resistor R3 is connected with a capacitor C1 and a VIN pin of a chip U1, and the anode of a diode D2 is connected with an auxiliary winding LSAUXA capacitor C5 is connected to the cathode of the diode D2 and the auxiliary winding LS at the same name endAUXBetween the different terminals, auxiliary winding LSAUXThe synonym terminal is grounded.
Based on the above technical scheme, because the control chip integrates the high-voltage starting circuit, the input voltage VIN can directly charge the starting capacitor C1 through the starting current-limiting resistor R3, along with the increase of the VIN voltage, the control chip U1 generates a VCC voltage signal to charge the capacitor C2, after the VCC voltage of 9V is stabilized, the system starts soft start, and is turned onStarting from the auxiliary winding LSAUXThe capacitor C5 is charged through the rectifier diode D2, and when the voltage is higher than a certain value, it will completely replace the internal start module to supply power to the control chip U1 and also supply power to the half-bridge driving chip U2. The maximum charging current of the integrated high-voltage starting module can reach 25mA, so that the starting time of the system is reduced from hundreds of milliseconds to tens of milliseconds, and meanwhile, the efficiency of the converter is improved.
As an improvement of the invention, the converter further comprises an over-current sampling circuit which comprises a transformer T1, a diode D1 and a resistor RCS1Resistance RCS2And a capacitor CCSThe homonymous terminal of a secondary winding LS1 of the transformer is connected with the anode of a diode D1, the heteronymous terminal of a secondary winding LS1 of the transformer is grounded, the homonymous terminal of a secondary winding LP1 is connected with a VIN terminal, and a resistor R is connected with the positive terminal of a diode D1CS1A resistor R connected between the cathode of the diode D1 and the different name terminal of the secondary winding LS1CS1And a capacitor C is connected between the cathode of the diode D1CSAnd a resistance RCS2Resistance RCS2The other end is connected to the CS pin of chip U1.
Based on the technical scheme, the current sampling transformer T1 samples the input current, and the sampled input current passes through the rectifier diode D1 and then passes through the RCS1Generating over-current sampled input signal, and passing through resistor RCS2And a capacitor CCSThe low-pass filter is formed and then input to a control chip, the current of the system is monitored in real time, and damage to the converter under abnormal conditions such as magnetic saturation or short circuit is prevented.
As an improvement of the invention, the converter further comprises a feedback regulation circuit comprising a resistor RFB1Resistance RFB2Optocoupler U3 and resistor RCOMPAnd a capacitor CCOMPComposition, resistance RFB1One end of the secondary winding LS3 is connected with the same name end, and the other end is connected with a resistor RFB2R is resistance toFB2Is grounded, and the input end of the optocoupler U3 is connected with the resistor RFB1And a resistance RFB2Its output end is connected with COMP pin of chip U1 and resistor RCOMPOne end of the COMP pin of the chip U1 is connected with the capacitor CCOMP。
Based on the technical proposal, the utility model has the advantages that,resistance RFB1And a resistance RFB2The voltage divider will output a voltage VOUTSampling is carried out, the transmission of an isolation signal is completed through an optocoupler U3, the duty ratio of a PWM signal is regulated and controlled through a COMP pin, the feedback regulation of output voltage is realized, and a resistor RCOMPAnd a capacitor CCOMPA zero is formed to achieve frequency compensation for the system loop.
Compared with the prior art, the invention has the beneficial effects that:
1) the cascade double-end topological structure is adopted, the limitation of wide-range input and low-voltage large-current output is considered, a peripheral circuit is simplified, the system volume is reduced, and the power density of the system is improved.
2) The control chip can be used for a voltage mode and a current mode, is suitable for topological structures such as a full bridge, a half bridge and a push-pull mode, has a wider voltage range, and has good adaptability to various application environments and multi-path output.
3) The control chip integrates a high-voltage starting module, and has the advantages of small starting current, low power consumption and high conversion efficiency (the starting current obtained in a finished product test is only 150 muA, the power consumption is less than 4mA during normal work, and the system efficiency can reach more than 90%).
Drawings
Fig. 1 is a schematic circuit diagram of a time setting module according to the present invention.
FIG. 2 is a waveform diagram of key signals of the present invention.
Fig. 3 is a schematic circuit diagram of a buck and push-pull cascade current mode DC-DC converter according to the present invention.
Fig. 4 is a schematic diagram of the buck and push-pull cascade topology of the present invention.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific embodiments, which are to be understood as merely illustrative of the invention and not as limiting the scope of the invention.
Example (b): as shown in FIG. 1, a buck-push-pull cascade type current mode DC-DC converter control chip comprises a high-voltage starting module, a reference voltage module,Under-voltage locking module, clock module, error amplifier, PWM comparator, overflow detection module and logic control module, the chip still includes the time setting module, and the time setting module includes: the voltage-current converter comprises an amplifier AMP01, an NMOS tube N01, an NMOS tube N02, an NMOS tube N03, a PMOS tube P01, a PMOS tube P02, a PMOS tube P03 and a resistor RTIMEExternal connection resistor R of TIME pinTIMEBy means of an internal time setting module and a resistor RTIMEThe external resistor R is realized by compatible two loop control modes of voltage and currentTIMEFor adjusting internal charging and discharging current, the NMOS transistor N01, the NMOS transistor N02, the NMOS transistor N03, the PMOS transistor P01, the PMOS transistor P02 and the PMOS transistor P03 are MOS transistors with the same width-length ratio, and the proportionality coefficients of current mirrors formed by the NMOS transistor N01, the NMOS transistor N02, the NMOS transistor N03 and the PMOS transistor P01 are all 1: 1, I _ OT1= I _ OT2= I _ DT1= I _ DT2= (V _ OT1= I _ DT2= (V _ DT)REF/2)/ RTIME(ii) a The time setting circuit comprises an inverter INV01, an inverter INV02, an inverter INV03, an inverter INV04, an inverter INV05, an amplifier AMP02, an amplifier AMP03, a capacitor C _ PUSH, a capacitor C _ PULL, a PMOS pipe P04, a PMOS pipe P05, an NMOS pipe N04 and an NMOS pipe N05, and the time setting circuit is used for setting dead time or overlapping time (wherein C _ PUSH = C _ PULL);
dead time Δ T1= [ C _ PUSH = (V)REF/2)]/I_DT1，
Overlap time Δ T2= [ C _ PUSH = (V)REF/2)]/I_OT1。
Taking the overlap time as an example, the resistance RTIMEOne end of the voltage follower is grounded, the other end is connected with the TIME pin, and the output signal of the voltage follower formed by the operational amplifier AMP01 is at the resistor RTIMEThe constant pair of ground current is formed, the current signals are conducted to the drain terminals of P04 and P05 by a current mirror formed by PMOS tubes P01, P02 and P03, a delay circuit is formed by the current mirror and the capacitors C _ PUSH and C _ PULL, and a group of pulse signals PUSH _ IN and PULL _ IN with fixed overlapping time are generated.
Taking the current control mode as an example, the waveforms of the main signals are shown in fig. 2, where t1=0.22 μ s, which is the pulse width of the internal clock signal CLK; the period t = t1+ t2 of the clock signal, t2 being the low level time of CLK; the frequency of the other clock signal CLK2 is half CLK; Δ T is the overlap time of the push-pull signals.
In the voltage-current converter, an inverting input end of an amplifier AMP01 is connected with a TIME pin and an output end thereof, an output end thereof is connected with drain ends of a PMOS tube P01 and an NMOS tube N01, a source end of a PMOS tube P01 is connected with a source end of a PMOS tube P02 and a source end of a PMOS tube P03, a gate end of the PMOS tube P01 is connected with a gate end of a PMOS tube P02 and a gate end of a PMOS tube P03, a gate end and a drain end of a PMOS tube P01 are connected, a gate end of an NMOS tube N01 is connected with a gate end of an NMOS tube N02 and a gate end of an NMOS tube N03, a source end of an NMOS tube N01 is connected with a source end of an NMOS tube N02 and a source end of an NMOS tube N03, a gate end and a drain end of an NMOS tube N01 are connected, a drain end of the PMOS tube P02 generates a current I _ OT1, a drain end of an NMOS tube N02 generates a current I _ DT1, a drain end of the PMOS tube P03 is connected with an I _ OT2, and a drain end of an NMOS tube N2 generates a current.
In the time setting circuit, the input end of an inverter INV02 is connected with a signal CLK, the grid end of an NMOS tube N04 and the grid end of a PMOS tube P04, the output end of an inverter INV02 is connected with the grid ends of a PMOS tube P05 and an NMOS tube N05, the drain end of a PMOS tube P04 is connected with the drain end of an NMOS tube N04, the output end of an inverter INV01 and the inverting input end of an amplifier AMP02, the source end of the PMOS tube P04 is connected with a current I _ OT1, the source end of an NMOS tube N04 is connected with a current I _ DT1, the source end of a PMOS tube P05 is connected with a current I _ OT2, the drain end of a PMOS tube P05 is connected with the drain end of an NMOS tube N05, the output end of the inverter INV03 and the inverting input end of an amplifier AMP03, the source end of an NMOS tube N05 is connected with a current I _ DT2, the noninverting input end of an amplifier 02 is connected with a non-inverting input end Vref, the inverting input end of a capacitor C _ PUSH is connected with one end of a capacitor C _ PUSH, the other end of the capacitor C _ SH is connected with ground, the non-inverting input end of the amplifier 03 is connected with a capacitor Vref, the inverting input end of the capacitor C _ PUSH is connected with a capacitor C _ PUSH, the capacitor C _ PUSH is connected with a capacitor C _ PULL, and the other end of the capacitor C _ PULL is connected with a capacitor C _ PUSH is connected with a ground, an output end of the amplifier AMP02 is connected to an input end of the inverter INV04, and an output end of the amplifier AMP03 is connected to an input end of the inverter INV 05.
As shown in fig. 3, the main control circuit of the buck and push-pull cascade DC-DC converter comprises the chip U1, the resistor R1, the resistor R2, and the resistor RRTResistance RTIMECapacitor CSSAnd a capacitor CREFThe HD pin of the chip U1 is connected with the IH pin of the chip U2, the LD pin of the chip U1 is connected with the IL pin of the chip U2, the PUSH pin of the chip U1 is connected with the gate end of the NMOS tube N3, and the resistor R1IThe end of the primary winding LP1 of the transformer T1 is connected, the other end of the primary winding LP1 is connected with a resistor R2 and a UVLO pin of a chip U1, and the resistor RRTRT pin and resistor R of chip U1TIMEA TIME pin and a capacitor C connected with the chip U1SSAn SS pin and a capacitor C of the chip U1 are connectedREFThe REF pin of chip U1 is connected.
The control chip U1 generates buck drive signals HD and LD, PUSH-PULL output signals PUSH and PULL, the waveforms of the buck drive signals HD and LD are fully complementary, the phase difference is 180 °, the frequency is identical to the internal clock signal, the PUSH-PULL output signals PUSH and PULL are 50% duty ratio PWM signals, the frequency is half of the internal clock signal, and the two keep fixed dead time or overlap time under different control modes. The voltage divider formed by the resistor R1 and the resistor R2 provides an undervoltage protection input signal of the line voltage; rRTThe frequency of the built-in oscillator can be set; rTIMECan be conducted through the ground or the REFThe legs are connected to set the length of overlapping or dead time, so as to ensure the stable operation of the converter under various control modes; cSSThe time of the system soft start can be set; cREFCan be REFStabilize the transient voltage and reduce the ripple.
The converter further includes: step-down output drive circuit and push-pull output circuit, step-down and the cascaded formula topology of push-pull are shown in FIG. 4, and the preceding stage is step-down topology structure, and the back level is push-pull topology structure, and step-down circuit carries out the step-down transform to input voltage, and the output that obtains will be as push-pull circuit's power input, and inductance L1 that shares promptly is equivalent to a current source to push-pull circuit. Compared with a single-stage push-pull topology, the power amplifier saves a primary capacitor and a secondary inductor, and effectively improves the power density. In addition, because the voltage regulation is completed by the voltage reduction circuit, the voltage stress of the switching tube of the push-pull stage is small and is irrelevant to the input voltage, and the input voltage range can be wide.
A voltage-reducing output drive circuit, which comprises a chip U2, a capacitor C3, a capacitor C4, an inductor L1, an NMOS tube N1 and an NMOS tube N2, wherein a VCC pin of the chip U2 is connected with VDD, the capacitor C3 is connected with a VDD pin of the chip U2, one end of the capacitor C4 is connected with a HB pin of the chip U2, the other end of the capacitor C4 is connected between a HS pin of the chip U2 and a drain terminal of the NMOS tube N2 and the inductor L1, a gate terminal of the NMOS tube N1 is connected with an HO pin of the chip U2, a source terminal of the NMOS tube C4 is connected with the drain terminal of the NMOS tube N2 and one end of the inductor L1, the drain terminal of the NMOS tube N1 is connected with a same name terminal of a primary winding LP1 of a transformer T1, a gate terminal of the NMOS tube N2 is connected with an LO pin of the chip U2, and a source terminal of the VSS pin of the chip U2 and the ground;
the PWM signals HD and LD generated by the control chip U1 are input into the chip U2, and then the NMOS transistor N1 and the NMOS transistor N2 (driving power transistor) are inverted, and the voltage generated after passing through the inductor L1 supplies power to the post-stage push-pull topology, where the voltage V _ L1= VIN × D, and D is the duty ratio of HD. The capacitor C3 is used as a decoupling capacitor for filtering noise waves of VCC, and the capacitor C4 is a high-voltage capacitor for supplying power to the chip U2.
The push-pull output circuit comprises a transformer T2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6 and a capacitor COUTThe dotted terminal of a primary winding LP2 of a transformer T2 is connected with the dotted terminal of a primary winding LP3, the dotted terminal of the primary winding LP2 is connected with the drain terminal of an NMOS tube N4, the source terminal of the NMOS tube N4 is grounded, the gate terminal of an NMOS tube N4 is connected with a PULL pin of a chip U1, a control signal of the gate terminal of the NMOS tube N4 is generated by the PUSH pin, the dotted terminal of the primary winding LP3 of the transformer T2 is connected with one side of an inductor L1, the dotted terminal of the primary winding LP3 is connected with the drain terminal of the NMOS tube N3, the source terminal of the NMOS tube N3 is grounded, the dotted terminal of a secondary winding LS2 of the transformer T2 is connected with the drain terminal of the NMOS tube N6 and the gate terminal of the NMOS tube N5, the dotted terminal of the secondary winding LS2 is connected with the dotted terminal of the secondary winding LS3, the dotted terminal of the secondary winding LS3 of the secondary winding LS2 is connected with the dotted terminal of the NMOS tube LS2, the dotted terminal of the secondary winding LS3 is connected with the drain terminal of the NMOS tube N6, and the drain terminal of the NMOS 6 of the NMOS tube N5OUTOne end of the secondary winding LS3 is connected to the same name of the secondary winding LS3, and the other end of the secondary winding LS3 is grounded. The primary winding LP2 and the secondary winding LS2 form a transformer, the primary winding LP3 and the secondary winding LS3 form a transformer, and the two transformers share one magnetic core.
The push-pull signal of the chip U1 directly drives the NMOS transistor N3 and the NMOS transistor N4, the positive pole transformer T2 consists of five windings, wherein a primary winding LP2, a primary winding LP3, a secondary winding LS2 and a secondary winding LS3 participate in power conversion from input voltage to output voltage, and LS is connected with the power converterAUXFor auxiliary windings, specially adapted thereforAnd supplying power to the control chip. The output of the transformer is rectified by a rectifying circuit composed of an NMOS tube N5 and an NMOS tube N6, and then the pair C is connectedOUTThe charging is carried out, meanwhile, a voltage signal VOUT is output, a VCC pin of the chip U1 generates a power supply signal VCC in a starting stage, and power is supplied to the U2 through a VDD pin of the U2; and after starting, the auxiliary winding LSAUXThe output voltage is rectified by a diode D2 to generate a power supply VCC, and the power supply VCC supplies power to the chip U1 and the chip U2.
The converter also comprises a starting circuit which comprises a resistor R3, a capacitor C1, a capacitor C2, a capacitor C5, a diode D2 and an auxiliary winding LSAUXOne end of a resistor R3 is connected with the same name end of a primary winding LP1 of the transformer T1, the other end of the resistor R3 is connected with a capacitor C1 and a VIN pin of a chip U1, and the anode of a diode D2 is connected with an auxiliary winding LSAUXA capacitor C5 is connected to the cathode of the diode D2 and the auxiliary winding LS at the same name endAUXBetween the different terminals, auxiliary winding LSAUXThe synonym terminal is grounded. Because the control chip integrates the high-voltage starting circuit, the input voltage VIN can directly charge the starting capacitor C1 through the starting current-limiting resistor R3, the control chip generates a VCC voltage of 9V to charge the capacitor C2 along with the increase of the VIN voltage, the system starts soft start after the VCC voltage of 9V is stabilized, and the auxiliary winding LS startsAUXThe capacitor C5 is charged through the rectifier diode D2, and when the voltage is higher than 9.3V, the capacitor C5 completely replaces the internal starting module to supply power to the control chip. The maximum charging current of the integrated high-voltage starting module can reach 25mA, so that the starting time of the system is reduced from hundreds of milliseconds to tens of milliseconds, and meanwhile, the efficiency of the converter is improved.
The converter also comprises an overcurrent sampling circuit which comprises a transformer T1, a diode D1 and a resistor RCS1And a resistor RCS2And a capacitor CCSThe homonymous terminal of a secondary winding LS1 of the transformer is connected with the anode of a diode D1, the heteronymous terminal of a secondary winding LS1 is grounded, the homonymous terminal of LP1 is connected with a VIN terminal, and a resistor R is connected with the positive terminal of a diode D1CS1A resistor R connected between the cathode of the diode D1 and the different name terminal of the secondary winding LS1CS1And a capacitor C is connected between the negative electrode of the diode D1CSAnd a resistance RCS2Resistance RCS2The other end is connected to the CS pin of chip U1. Electric current miningThe sample transformer T1 samples the input current, passes through the rectifier diode D1, and then passes through RCS1Generating over-current sampled input signal, and passing through resistor RCS2And a capacitor CCSThe low-pass filter is formed and then input to the control chip, the current of the system is monitored in real time, and the converter is prevented from being damaged under abnormal conditions such as magnetic saturation or short circuit.
The converter further comprises a feedback regulation circuit comprising a resistor RFB1Resistance RFB2Optocoupler U3 and resistor RCOMPAnd a capacitor CCOMPComposition, resistance RFB1One end of the secondary winding LS3 is connected with the same name end, and the other end is connected with a resistor RFB2R is resistance toFB2Is grounded, and the input end of the optocoupler U3 is connected with the resistor RFB1And a resistance RFB2Its output end is connected with COMP pin of chip U1 and resistor RCOMPOne end of the COMP pin of the chip U1 is connected with the capacitor CCOMP. Resistance RFB1And a resistance RFB2The voltage divider will output a voltage VOUTSampling is carried out, the transmission of an isolation signal is completed through an optocoupler U3, the duty ratio of a PWM signal is regulated and controlled through a COMP pin, the feedback regulation of output voltage is realized, and a resistor RCOMPAnd a capacitor CCOMPThe frequency compensation of the system loop is implemented as a zero.
The working principle is as follows: after power-on, the starting circuit starts to supply power to the control chip U1 along with the increase of the VIN voltage; when the chip U1 starts working, a group of PWM signals HD and LD with phase difference of 180 degrees are generated, and the group of PWM signals directly drive the power tubes N1 and N2 of the buck stage after being amplified by the half-bridge driving chip U2; the push-pull signals generated at the same time directly drive power tubes N3 and N4 of the push-pull stage, and power conversion is completed through a transformer T2; meanwhile, the diode D2 is turned on to replace an integrated high-voltage starting module to start normal power supply for the chip, the overcurrent sampling module also starts to work in the period so as to ensure the safe work of the converter, and the feedback regulating circuit also can regulate and control the duty ratio of the PWM signal in real time to keep the stability of the output voltage.
It should be noted that the above-mentioned contents only illustrate the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and it is obvious to those skilled in the art that several modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations fall within the protection scope of the claims of the present invention.
Claims (10)
1. The utility model provides a step-down and push-pull cascade type current mode DC-DC converter control chip, the chip includes high-pressure start-up module, reference voltage module, under-voltage locking module, clock module, error amplifier, PWM comparator, overflows detection module and logic control module, its characterized in that, the chip still includes the time and sets up the module, and the time sets up the module and includes:
the voltage-current converter comprises an operational amplifier AMP01, a current mirror composed of an NMOS tube N01, an NMOS tube N02, an NMOS tube N03, a PMOS tube P01, a PMOS tube P02 and a PMOS tube P03, and a resistor RTIMERealize the external resistor RTIMEAdjusting internal charging and discharging current;
the time setting circuit comprises an inverter INV01, an inverter INV02, an inverter INV03, an inverter INV04, an inverter INV05, an amplifier AMP02, an amplifier AMP03, a capacitor C _ PUSH, a capacitor C _ PULL, a PMOS tube P04, a PMOS tube P05, an NMOS tube N04 and an NMOS tube N05, and the time setting circuit is used for setting dead time or overlapping time; externally connected resistor R of TIME pinTIMEBy means of an internal time setting module and a resistor RTIMETo be compatible with both voltage and current loop control modes.
2. The buck-push-pull cascade type current-mode DC-DC converter control chip as claimed in claim 1, in the voltage-current converter, the inverting input end of an operational amplifier AMP01 is connected with a TIME pin and the output end thereof, the output end of the PMOS transistor P3678 is connected with the drain ends of a PMOS transistor P01 and an NMOS transistor N01, the source end of the PMOS transistor P01 is connected with the source end of a PMOS transistor P02 and the source end of a PMOS transistor P03, the gate end of the PMOS transistor P01 is connected with the gate end of the PMOS transistor P02 and the gate end of a PMOS transistor P03, the gate end of the PMOS transistor P01 is connected with the drain end of the PMOS transistor P01, the gate end of the NMOS transistor N01 is connected with the gate end of an NMOS transistor N02 and the gate end of an NMOS transistor N03, the source end of the NMOS transistor N01 is connected with the source end of the NMOS transistor N02 and the source end of the NMOS transistor N03, the gate end of the NMOS transistor N01 is connected with the drain end, the drain end of the PMOS transistor P02 generates a current I _ OT1, the drain end of the NMOS transistor N02 generates a current I _ DT1, the drain end of the PMOS transistor P03 generates a current I _ OT2, and the drain end of the NMOS transistor N03 generates a current I _ DT 2.
3. The control chip of claim 2, wherein in the time-setting circuit, the input terminal of inverter INV02 is connected to the signal CLK, the gate terminal of NMOS transistor N04 and the gate terminal of PMOS transistor P04, the output terminal of inverter INV02 is connected to the gate terminals of PMOS transistor P05 and NMOS transistor N05, the drain terminal of PMOS transistor P04 is connected to the drain terminal of NMOS transistor N04, the output terminal of inverter INV01 and the inverting input terminal of amplifier AMP02, the source terminal of PMOS transistor P04 is connected to current I _ AMP 1, the source terminal of NMOS transistor N04 is connected to current I _ DT1, the source terminal of PMOS transistor P05 is connected to current I _ OT2, the drain terminal of PMOS transistor P05 is connected to the drain terminal of NMOS transistor N05, the output terminal of inverter INV03 and the inverting input terminal of amplifier 03, the current I _ AMP 2 of NMOS transistor N05, the non-inverting input terminal of amplifier 02 is connected to the ground, the non-inverting input terminal of amplifier 02 is connected to the non-inverting input terminal of the same-phase capacitor PUSH, and one terminal of the capacitor PUSH _ SH C is connected to ground, the non-inverting input end of the amplifier AMP03 is connected with Vref, the inverting input end of the amplifier AMP03 is connected with the capacitor C _ PULL, the other end of the capacitor C _ PULL is grounded, the output end of the amplifier AMP02 is connected with the input end of the inverter INV04, and the output end of the amplifier AMP03 is connected with the input end of the inverter INV 05.
4. The buck-push-pull cascade type current mode DC-DC converter control chip as claimed in claim 3, wherein current mirror proportionality coefficients formed by NMOS transistor N01, NMOS transistor N02, NMOS transistor N03, PMOS transistor P01, PMOS transistor P02 and PMOS transistor P03 are all 1: 1,
wherein I _ OT1= I _ OT2= I _ DT1= I _ DT2= (VREF/2)/RTIME，
Dead time Δ T1= [ C _ PUSH = (V)REF/2)]/I_DT1，
Overlap time Δ T2= [ C _ PUSH = (V)REF/2)]/I_OT1。
5. A kind ofThe buck and push-pull cascade DC-DC converter is characterized in that the converter master control circuit comprises the chip U1, a resistor R1, a resistor R2 and a resistor R according to any one of claims 1 to 4RTResistance RTIMECapacitor CSSAnd a capacitor CREFThe HD pin of the chip U1 is connected with the IH pin of the chip U2, the LD pin of the chip U1 is connected with the IL pin of the chip U2, the PUSH pin of the chip U1 is connected with the gate end of the NMOS tube N3, one end of the resistor R1 is connected with the end of the transformer T1 primary winding LP1 with the same name, the other end is connected with the resistor R2 and the UVLO pin of the chip U1, and the resistor R1 is connected with the UVLO pin of the transformer T1RTRT pin and resistor R of chip U1TIMEA TIME pin and a capacitor C connected with the chip U1SSAn SS pin and a capacitor C of the chip U1 are connectedREFThe REF pin of chip U1 is connected.
6. The buck-PUSH cascade type DC-DC converter according to claim 5, wherein the control chip U1 generates buck driving signals HD and LD and PUSH-PULL output signals PUSH and PULL, the waveforms of the buck driving signals HD and LD are completely complementary, the phase difference is 180 °, the frequency is consistent with the internal clock signal, the PUSH-PULL output signals PUSH and PULL are 50% duty ratio PWM signals, the frequency is half of the internal clock signal, and the dead time or the overlap time is kept fixed under different control modes.
7. The buck-push-pull cascaded DC-DC converter according to claim 6, further comprising:
a voltage-reducing output driving circuit, which comprises a chip U2, a capacitor C3, a capacitor C4, an inductor L1, an NMOS tube N1 and an NMOS tube N2, wherein the capacitor C3 is connected with a VDD pin of the chip U2, one end of the capacitor C4 is connected with a HB pin of the chip U2, the other end of the capacitor C4 is connected between the HS pin of the chip U2 and a drain terminal of an NMOS tube N2 and the inductor L1, a gate terminal of the NMOS tube N1 is connected with an HO pin of the chip U2, a source terminal of the NMOS tube N2 is connected with a drain terminal of the NMOS tube N2 and one end of the inductor L1, a drain terminal of the NMOS tube N1 is connected with a primary winding LP1 dotted terminal, a gate terminal of the NMOS tube N2 is connected with an LO pin of the chip U2, and a source terminal of the NMOS tube U2 is connected with a ground;
the push-pull output circuit comprises a transformer T2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6 and a capacitor COUTThe dotted end of a primary winding LP2 of the transformer T2 is connected with the dotted end of a primary winding LP3, the dotted end of a primary winding LP2 is connected with the drain end of an NMOS tube N4, the source end of an NMOS tube N4 is grounded, the gate end of an NMOS tube N4 is connected with the PULL pin of a chip U1, the dotted end of a primary winding LP3 of the transformer T2 is connected with one side of an inductor L1, the dotted end of a primary winding LP3 is connected with the drain end of an NMOS tube N3, the source end of an NMOS tube N3 is grounded, the dotted end of a secondary winding LS2 of the transformer T2 is connected with the drain end of an NMOS tube N6 and the gate end of an NMOS tube N5, the dotted end of a secondary winding LS 6 is connected with the dotted end of a secondary winding 3, the dotted end of a secondary winding LS3 of the transformer T2 is connected with the dotted end, the dotted end of a secondary winding LS3 is connected with the drain end of an NMOS tube N5 and the drain end of an NMOS tube N3874, and the gate end of an NMOS tube N6, and the gate end of an NMOS tube C capacitor COUTOne end of the secondary winding LS3 is connected to the same name of the secondary winding LS3, and the other end of the secondary winding LS3 is grounded.
8. The buck-push-pull cascade DC-DC converter according to claim 7, wherein the converter further comprises a start-up circuit including a resistor R3, a capacitor C1, a capacitor C2, a capacitor C5, a diode D2, and an auxiliary winding LSAUXOne end of a resistor R3 is connected with the same name end of a primary winding LP1 of the transformer T1, the other end of the resistor R3 is connected with a capacitor C1 and a VIN pin of a chip U1, and the anode of a diode D2 is connected with an auxiliary winding LSAUXA capacitor C5 is connected to the cathode of the diode D2 and the auxiliary winding LS at the same name endAUXBetween the synonyms.
9. The buck-push-pull cascade DC-DC converter according to claim 8, wherein the converter further comprises an over-current sampling circuit comprising a transformer T1, a diode D1, and a resistor RCS1Resistance RCS2And a capacitor CCSThe dotted terminal of a secondary winding LS1 of the transformer T1 is connected with the anode of a diode D1, the different-dotted terminal of the secondary winding LS1 is grounded, the dotted terminal of a primary winding LP1 is connected with a VIN terminal, and a resistor RCS1A resistor R connected between the cathode of the diode D1 and the different name terminal of the secondary winding LS1CS1And a capacitor C is connected between the negative electrode of the diode D1CSAnd a resistorRCS2Resistance RCS2The other end is connected to the CS pin of chip U1.
10. The buck-push-pull cascaded DC-DC converter according to claim 9, wherein the converter further comprises a feedback regulation circuit including a resistor RFB1Resistance RFB2Optocoupler U3 and resistor RCOMPAnd a capacitor CCOMPComposition, resistance RFB1One end of the secondary winding LS3 is connected with the same name end, and the other end is connected with a resistor RFB2R is resistance toFB2Is grounded, and the input end of the optocoupler U3 is connected with the resistor RFB1And a resistance RFB2Its output end is connected with COMP pin of chip U1 and resistor RCOMPOne end of the COMP pin of the chip U1 is connected with the capacitor CCOMP。
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| TW202118212A (en) * | 2019-06-28 | 2021-05-01 | 台灣積體電路製造股份有限公司 | Dc-dc converter |
| CN110708820A (en) * | 2019-10-31 | 2020-01-17 | 苏州锴威特半导体股份有限公司 | LED constant current driving circuit controlled through LLC resonance |
| CN111030630A (en) * | 2019-12-06 | 2020-04-17 | 深圳市纽瑞芯科技有限公司 | Circuit and method for calibrating on-chip RC time constant by using switched capacitor |
| CN112117899A (en) * | 2020-08-19 | 2020-12-22 | 苏州锴威特半导体股份有限公司 | BOOST converter controlled by current mode |
| CN112701909A (en) * | 2020-12-15 | 2021-04-23 | 深圳市航天新源科技有限公司 | Combined circuit of voltage type push-pull converter |
| CN216216502U (en) * | 2021-10-15 | 2022-04-05 | 中车株洲电力机车研究所有限公司 | Prevent electric current backward flow circuit and switching power supply |
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