CN211791285U - Circuit for improving dynamic response of power supply system and switching power supply using circuit - Google Patents
Circuit for improving dynamic response of power supply system and switching power supply using circuit Download PDFInfo
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- CN211791285U CN211791285U CN202020127391.4U CN202020127391U CN211791285U CN 211791285 U CN211791285 U CN 211791285U CN 202020127391 U CN202020127391 U CN 202020127391U CN 211791285 U CN211791285 U CN 211791285U
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Abstract
The utility model relates to a promote switching power supply of electrical power generating system dynamic response's circuit and applied this circuit. The circuit for improving the dynamic response of the power supply system can detect the load change of the power supply system, and the minimum working frequency of the switching system realizes the quick dynamic response when the load is switched within a certain time range by setting the maximum quick dynamic response time of the system. The switching power supply includes a transformer and a control circuit. The control circuit judges the load state of the system by carrying out platform sampling on the voltage signal generated by the auxiliary winding unit of the transformer, and switches the minimum working frequency of the system according to the load state, so that the dynamic response speed of the power supply system is improved. The control circuit comprises the circuit for improving the dynamic response of the power supply system, and the switching power supply can realize the performance of quick dynamic response.
Description
Technical Field
The utility model relates to the field of electronic technology, especially a promote switching power supply of electrical power generating system dynamic response's circuit and applied this circuit.
Background
Power converters are widely used in consumer electronic devices because they can convert power from one form to another. Common forms of conversion are: alternating Current (AC) to Direct Current (DC), direct current to alternating current (DC), and direct current to Direct Current (DC). The power converter includes a linear power supply and a switching power supply. The conversion mode can be divided into an isolated type and a non-isolated type. In recent years, a primary side feedback isolation type switching power supply does not need a secondary optical coupler, and Tl431 and a secondary constant current level secondary control circuit greatly reduce the system cost, so that the primary side feedback isolation type switching power supply is widely applied to low-power occasions. The switching power supply needs to meet the requirement that when a load generates transient, the output voltage can be maintained within a specific tolerance range, and the normal operation of the system is ensured.
As shown in fig. 4, the primary-side feedback switching power supply assumes that the minimum operating frequency is Fmin and the output capacitance is Cout, and assuming that the load changes from 0A to 1A, the maximum change Δ Vout of the output voltage is:
according to the equation, when the load is in transient state in the constant voltage mode, the maximum variation of the output voltage is inversely proportional to Fmin.
The primary side feedback switch power supply working in a Discontinuous (DCM) mode has an input power transmission equation as follows:
wherein Lp is the primary inductance of the transformer, Ip is the peak current flowing through the primary inductance, and Fsw is the working frequency of the switching power supply.
The relation that the system input power is in direct proportion to the Fsw can be obtained according to the formula (2). When the system enters an idle state, Fsw is reduced to Fmin to ensure that the power consumption of the system is minimized. However, when the system is switched to a full-load state instantly when the system is in no-load, the reduction of the working frequency causes a large reduction of the output voltage, which results in a poor dynamic response, so that it is difficult to achieve both the fast dynamic response and the low standby power consumption of the system under a light-load condition.
Disclosure of Invention
In view of this, the utility model aims at providing a promote the circuit of electrical power generating system dynamic response and use the switching power supply of this circuit, promote electrical power generating system dynamic response's circuit, can be applied to former limit feedback switching power supply, can realize electrical power generating system's quick dynamic response performance.
The utility model discloses a following scheme realizes: a circuit for improving dynamic response of a power supply system comprises a sample-and-hold circuit, an error amplification circuit, a load detection circuit, a clock frequency division circuit and a dynamic response improving circuit; the sampling and holding circuit is respectively electrically connected with a transformer feedback winding unit in a power supply system and the error amplifying circuit and is used for carrying out error comparison and amplification on a voltage VSH output after the feedback voltage FB is subjected to platform sampling and a reference voltage Vref1 input into the error amplifying circuit through the error amplifying circuit and outputting an error voltage signal Vea; the error amplifying circuit is electrically connected with the load detection circuit and is used for comparing the Vea voltage signal with a reference voltage Vref2 input into the load detection circuit through the load detection circuit and then outputting a load judgment signal load; the load detection circuit is electrically connected with the dynamic response lifting circuit and is used for inputting the load signal into the dynamic response lifting circuit; the clock frequency division circuit is electrically connected with the dynamic response boost circuit and is used for inputting clock signals clk2 and clk3 to the dynamic response boost circuit, and the dynamic response boost circuit changes the minimum working frequency through switching the clk2 and clk3 signals so as to boost the dynamic response of the power supply system.
Further, the sample-and-hold circuit comprises a controlled switch K1 and a first capacitor C1 electrically connected thereto; one end of the controlled switch K1 is connected with a feedback voltage FB, the other end of the controlled switch K1 is connected with the upper pole plate of the first capacitor C1, and a control end of the controlled switch K1 inputs a sampling control signal Tsp; the lower plate of the first capacitor is grounded, and the upper plate of the first capacitor outputs a voltage signal VSH.
Further, the error amplifying circuit adopts a fixed gain amplifier, a non-inverting input terminal of the fixed gain amplifier is connected with the reference voltage Vref1, an inverting input terminal of the fixed gain amplifier is connected with an output terminal of the sample-and-hold circuit and inputs the voltage VSH, and an output terminal of the fixed gain amplifier, which is used as an output terminal of the error amplifying circuit, is connected with an input terminal of the load detection circuit and outputs the voltage Vea.
Furthermore, the load detection circuit adopts a comparator, the non-inverting input end of the comparator is used as the input end of the load detection circuit and is connected with the output end of the error amplification circuit, and voltage Vea is input; the inverting input end of the comparator is connected with a reference voltage Vref2, and the output end of the comparator is used as the output end of the load detection circuit, is connected with the dynamic response boost circuit and outputs a signal load.
Further, the clock frequency division circuit includes a first inverter, a second inverter, a first delay unit, a first nand gate, a first or gate, a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a tenth D flip-flop, and an eleventh D flip-flop; the input end of the first inverter inputs a power system working period Tsw signal, and the output of the first inverter is respectively connected with the first input end of the first NAND gate and the input end of the second inverter; the output end of the second inverter is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the second input end of the first nand gate, and the output end of the first nand gate is respectively connected with the reset end of the first D flip-flop and the reset ends of the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, the ninth D flip-flop, the tenth D flip-flop and the eleventh D flip-flop; a first input end of the first OR gate inputs a power supply system working period Tsw signal, a second input end of the first OR gate inputs a fixed high-frequency clock signal clk1, and an output end of the first OR gate is connected with a clk end of the first D flip-flop; the D end of the first D trigger is connected with the QN end of the first D trigger, and the Q end of the first D trigger is connected with the clk end of the second D trigger; the D end of the second D trigger is connected with the QN end of the second D trigger, and the Q end of the second D trigger is connected with the clk end of the third D trigger; the D end of the third D trigger is connected with the QN end of the third D trigger, and the Q end of the third D trigger is connected with the clk end of the fourth D trigger; a D end of the fourth D flip-flop is connected with a QN end thereof, and a Q end of the fourth D flip-flop is connected with a clk end of the fifth D flip-flop; a D end of the fifth D flip-flop is connected with a QN end thereof, and a Q end of the fifth D flip-flop is connected with a clk end of the sixth D flip-flop; a D end of the sixth D flip-flop is connected to a QN end thereof, and a Q end of the sixth D flip-flop is connected to a clk end of the seventh D flip-flop; a D end of the seventh D flip-flop is connected to a QN end thereof, and a Q end of the seventh D flip-flop is connected to a clk end of the eighth D flip-flop; a D end and a QN end of the eighth D flip-flop are connected, and a Q end of the eighth D flip-flop is connected to a clk end of the ninth D flip-flop; a D end of the ninth D flip-flop is connected to a QN end thereof, and a Q end of the ninth D flip-flop is connected to a clk end of the tenth D flip-flop; a D end of the tenth D flip-flop is connected to a QN end thereof, and a Q end of the tenth D flip-flop is connected to a clk end of the eleventh D flip-flop; the D end of the tenth D trigger is connected with the QN end thereof; the Q end of the ninth D flip-flop outputs a frequency-divided signal clk2, and the Q end of the eleventh D flip-flop outputs a frequency-divided signal clk 3.
Further, the first delay circuit comprises a first bias current source, a delay capacitor C2, a Schmitt trigger, a second switch K2 and a third switch K3; the second switch K2 and the third switch K3 are used as input ends of the first delay unit and are controlled by the input end of the first delay unit; a power supply Vdd is respectively connected with one end of the delay capacitor C2, one end of the third switch K3 and the input end of the Schmitt trigger through a second switch K2; the other end of the third switch K3 is connected with one end of the first bias current source, and the other end of the first bias current source and the other end of the delay capacitor C2 are both grounded; and the output end of the Schmitt trigger is used as the output end of the first delay unit.
Further, the dynamic response boost circuit comprises a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, a fifteenth D flip-flop, a sixteenth D flip-flop, a seventeenth D flip-flop, an eighteenth D flip-flop, a third inverter, a first NOR gate, a second NOR gate, a third NOR gate, a first AND gate and a second OR gate; the reset end of the twelfth D trigger and the reset ends of the thirteenth D trigger, the fourteenth D trigger, the fifteenth D trigger, the sixteenth D trigger, the seventeenth D trigger and the eighteenth D trigger are connected with the input end of the third inverter and the output end of the load detection circuit comparator, and input a signal load for generating a variable pulse signal controlled by the load signal; a D end of the twelfth D flip-flop is connected with a QN end thereof, and a Q end of the twelfth D flip-flop is connected with the clk end of the thirteenth D flip-flop; a D end of the thirteenth D flip-flop is connected to a QN end thereof, and a Q end of the thirteenth D flip-flop is connected to a clk end of the fourteenth D flip-flop; a D end of the fourteenth D flip-flop is connected to a QN end thereof, and a Q end of the fourteenth D flip-flop is connected to a clk end of the fifteenth D flip-flop; a D end of the fifteenth D flip-flop is connected to a QN end thereof, and a Q end of the fifteenth D flip-flop is connected to a clk end of the sixteenth D flip-flop; the D end of the sixteenth D flip-flop is connected to the QN end of the sixteenth D flip-flop and the first input end of the first nor gate respectively; the Q end of the sixteenth D flip-flop is connected with the clk end of the seventeenth D flip-flop; a D end of the seventeenth D flip-flop is connected with a QN end of the seventeenth D flip-flop, and a Q end of the seventeenth D flip-flop is connected with a clk end of the eighteenth D flip-flop; the D end of the eighteenth D trigger is respectively connected with the QN end of the eighteenth D trigger and the second input end of the first NOR gate; the output end of the first NOR gate is connected with the first input end of the second NOR gate, and the second input end of the second NOR gate is connected with the output end of the third NOR gate; the output end of the third inverter is connected with the first input end of the third nor gate, the second input end of the third nor gate is respectively connected with the output end of the second nor gate and the first input end of the first and gate, and the second input end of the first and gate is connected with the Q end of the ninth D flip-flop and receives a signal clk 2; the output end of the first and gate is connected with the first input end of the second or gate, the second input end of the second or gate is connected with the Q end of the eleventh D flip-flop, and receives a signal clk 3; the output terminal of the second or gate outputs a Toff _ max pulse signal.
Furthermore, the invention also provides a switching power supply applying the circuit for improving the dynamic response of the power supply system, which comprises a transformer, a peripheral circuit and a control circuit thereof; the transformer and the peripheral circuit thereof are electrically connected with the control circuit; the transformer and the peripheral circuit thereof comprise a transformer T1, a transformer T1 feedback winding unit, a power tube Q1, a detection resistor RCS, a first diode Do, an output capacitor Cout and an output load Rload; the control circuit is connected with a feedback winding unit of the transformer T1 and used for generating a switching signal to adjust the pulse width and the frequency of the transformer;
the dotted terminal of the secondary winding on the primary side of the transformer T1 is connected with the feedback winding unit of the transformer T1; the synonym end of the secondary winding on the primary side of the transformer T1 is grounded; the dotted terminal of the primary side first winding of the transformer T1 is connected to the drain electrode of the power tube Q1; the source electrode of the power tube Q1 is connected with one end of the detection resistor RCS; the grid electrode of the power tube Q1 is connected with the control circuit; the other end of the detection resistor RCS is grounded; the synonym end of the primary side first winding of the transformer T1 is connected with the input voltage; the dotted end of the transformer T1 side winding is connected with the anode of the first diode Do; the cathode of the first diode Do is connected with one end of the output capacitor Cout and one end of the output load Rload respectively; the other end of the output capacitor Cout is respectively connected with the synonym end of the amplitude winding of the transformer T1 and the other end of the output load Rload and is grounded at the same time;
the transformer T1 is connected with a feedback winding unit and comprises a second diode D1, a voltage division resistor R and a third capacitor C3; one end of the divider resistor R is connected with one end of the third capacitor C3 and is grounded at the same time; the other end of the third capacitor C3 is connected with the cathode of the second diode D1; the anode of the second diode D1 is connected with the other end of the divider resistor R and is connected with the same-name end of the secondary winding on the primary side of the transformer T1;
the control circuit comprises a circuit for improving the dynamic response of the power supply system and a logic drive circuit; the circuit for improving the dynamic response of the power supply system is electrically connected with the logic driving circuit; the logic circuit is connected with the gate of the power tube Q1 and is used for transmitting the Toff _ max pulse signal and controlling the maximum off time of the Q1 power tube through the signal.
Compared with the prior art, the utility model discloses following beneficial effect has:
(1) the utility model provides a dynamic response circuit of lifting power supply system can reach former limit feedback switching power supply and compromise the purpose of optimizing stand-by power consumption and quick dynamic response.
(2) The utility model discloses realize the quick dynamic response in the certain time span when taking into account system light load and no-load standby power consumption. Make and use the utility model discloses a quick dynamic response performance can be realized to former limit feedback switching power supply system.
Drawings
Fig. 1 is a schematic block diagram of a switching power supply according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a clock divider circuit according to an embodiment of the present invention, wherein the first inverter is 201, the second inverter is 202, the first delay unit is 203, the first nand gate is 204, the first or gate is 205, the first D flip-flop is 206, the second D flip-flop is 207, the third D flip-flop is 208, the fourth D flip-flop is 209, the fifth D flip-flop is 210, the sixth D flip-flop is 211, the seventh D flip-flop is 212, the eighth D flip-flop is 213, the ninth D flip-flop is 214, the tenth D flip-flop is 215, and the eleventh D flip-flop is 216.
Fig. 3 is a schematic diagram of a dynamic response boost circuit according to an embodiment of the present invention, wherein the twelfth D flip-flop is 301, the thirteenth D flip-flop is 302, the fourteenth D flip-flop is 303, the fifteenth D flip-flop is 304, the sixteenth D flip-flop is 305, the seventeenth D flip-flop is 306, the eighteenth D flip-flop is 307, the third inverter is 309, the first nor gate is 308, the second nor gate is 310, the third nor gate is 311, the first and gate is 312, and the second or gate is 313.
Fig. 4 is a schematic diagram of a relationship between an output voltage and a working frequency of a conventional primary-side feedback switching power supply according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a waveform signal of a load detection circuit according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a waveform signal of a clock divider circuit according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a waveform signal of a dynamic response boost circuit according to an embodiment of the present invention.
Fig. 8 is a schematic view of the working principle of the embodiment of the present invention.
Fig. 9 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of a logic circuit according to an embodiment of the present invention.
Fig. 11 is a schematic diagram of the first delay unit 203 according to an embodiment of the present invention.
Detailed Description
The present invention will be further explained with reference to the drawings and the embodiments.
As shown in fig. 1, the present embodiment provides a circuit for improving dynamic response of a power supply system, which includes a sample-and-hold circuit, an error amplification circuit, a load detection circuit, a clock frequency division circuit, and a dynamic response improving circuit; the sampling and holding circuit is respectively electrically connected with a transformer feedback winding unit in a power supply system and the error amplifying circuit and is used for carrying out error comparison and amplification on a voltage VSH output after the feedback voltage FB is subjected to platform sampling and a reference voltage Vref1 input into the error amplifying circuit through the error amplifying circuit and outputting an error voltage signal Vea; the error amplifying circuit is electrically connected with the load detection circuit and is used for comparing the Vea voltage signal with a reference voltage Vref2 input into the load detection circuit through the load detection circuit and then outputting a load judgment signal load; the load detection circuit is electrically connected with the dynamic response lifting circuit and is used for inputting the load signal into the dynamic response lifting circuit; the clock frequency division circuit is electrically connected with the dynamic response boost circuit and is used for inputting clock signals clk2 and clk3 to the dynamic response boost circuit, and the dynamic response boost circuit changes the minimum working frequency through switching the clk2 and clk3 signals so as to boost the dynamic response of the power supply system.
As shown in fig. 9, in the present example, the sample-and-hold circuit includes a controlled switch K1 and a first capacitor C1 electrically connected thereto; one end of the controlled switch K1 is connected with a feedback voltage FB, the other end of the controlled switch K1 is connected with the upper pole plate of the first capacitor C1, and a control end of the controlled switch K1 inputs a sampling control signal Tsp; the lower plate of the first capacitor is grounded, and the upper plate of the first capacitor outputs a voltage signal VSH.
In this embodiment, the error amplifying circuit is a fixed gain amplifier, a non-inverting input of the fixed gain amplifier is connected to the reference voltage Vref1, an inverting input of the fixed gain amplifier is connected to the output of the sample-and-hold circuit, and the voltage VSH is input to the fixed gain amplifier, and an output of the fixed gain amplifier is used as an output of the error amplifying circuit and connected to the input of the load detecting circuit, and outputs the voltage Vea.
In this embodiment, the load detection circuit employs a comparator, a non-inverting input terminal of the comparator is used as an input terminal of the load detection circuit and is connected to an output terminal of the error amplification circuit, and the voltage Vea is input; the inverting input end of the comparator is connected with a reference voltage Vref2, and the output end of the comparator is used as the output end of the load detection circuit, is connected with the dynamic response boost circuit and outputs a signal load.
As shown in fig. 2, in the present embodiment, the clock divider circuit includes a first inverter 201, a second inverter 202, a first delay unit 203, a first nand gate 204, a first or gate 205, a first D flip-flop 206, a second D flip-flop 207, a third D flip-flop, a fourth D flip-flop 209, a fifth D flip-flop 210, a sixth D flip-flop 211, a seventh D flip-flop 212, an eighth D flip-flop 213, a ninth D flip-flop 214, a tenth D flip-flop 215, and an eleventh D flip-flop 216; the input end of the first inverter 201 inputs a power system duty cycle Tsw signal, and the output of the first inverter 201 is connected to the first input end of the first nand gate 204 and the input end of the second inverter 202 respectively; the output end of the second inverter 202 is connected to the input end of the first delay unit 203, the output end of the first delay unit 203 is connected to the second input end of the first nand gate 204, and the output end of the first nand gate 204 is connected to the reset end of the first D flip-flop 206 and the reset ends of the second D flip-flop 207, the third D flip-flop 208, the fourth D flip-flop, the fifth D flip-flop 210, the sixth D flip-flop 211, the seventh D flip-flop 212, the eighth D flip-flop 213, the ninth D flip-flop 214, the tenth D flip-flop 215, and the eleventh D flip-flop 216, respectively; a first input end of the first or gate 205 inputs a power supply system working period Tsw signal, a second input end of the first or gate 205 inputs a fixed high-frequency clock signal clk1, and an output end of the first or gate 205 is connected with a clk end of the first D flip-flop 206; the D terminal of the first D flip-flop 206 is connected to the QN terminal thereof, and the Q terminal of the first D flip-flop 206 is connected to the clk terminal of the second D flip-flop 207; the D terminal of the second D flip-flop 207 is connected to the QN terminal thereof, and the Q terminal of the second D flip-flop 207 is connected to the clk terminal of the third D flip-flop 208; the D terminal of the third D flip-flop 208 is connected to the QN terminal thereof, and the Q terminal of the third D flip-flop 208 is connected to the clk terminal of the fourth D flip-flop; a D end of the fourth D flip-flop is connected to a QN end thereof, and a Q end of the fourth D flip-flop is connected to a clk end of the fifth D flip-flop 210; a D terminal of the fifth D flip-flop 210 is connected to a QN terminal thereof, and a Q terminal of the fifth D flip-flop 210 is connected to a clk terminal of the sixth D flip-flop 211; the D terminal of the sixth D flip-flop 211 is connected to the QN terminal thereof, and the Q terminal of the sixth D flip-flop 211 is connected to the clk terminal of the seventh D flip-flop 212; the D terminal of the seventh D flip-flop 212 is connected to the QN terminal thereof, and the Q terminal of the seventh D flip-flop 212 is connected to the clk terminal of the eighth D flip-flop 213; the D terminal of the eighth D flip-flop 213 and the QN terminal thereof, and the Q terminal of the eighth D flip-flop 213 are connected to the clk terminal of the ninth D flip-flop 214; the D terminal of the ninth D flip-flop 214 is connected to the QN terminal thereof, and the Q terminal of the ninth D flip-flop 214 is connected to the clk terminal of the tenth D flip-flop 215; the D terminal of the tenth D flip-flop 215 is connected to the QN terminal thereof, and the Q terminal of the tenth D flip-flop 215 is connected to the clk terminal of the eleventh D flip-flop 216; the D end of the tenth D trigger is connected with the QN end thereof; the Q terminal of the ninth D flip-flop 214 outputs a frequency-divided signal clk2, and the Q terminal of the eleventh D flip-flop 216 outputs a frequency-divided signal clk 3.
As shown in fig. 11, the first delay circuit includes a first bias current source, a delay capacitor C2, a schmitt trigger, a second switch K2, and a third switch K3; the second switch K2 and the third switch K3 are used as input ends of the first delay unit and are controlled by the input end of the first delay unit; a power supply Vdd is respectively connected with one end of the delay capacitor C2, one end of the third switch K3 and the input end of the Schmitt trigger through a second switch K2; the other end of the third switch K3 is connected with one end of the first bias current source, and the other end of the first bias current source and the other end of the delay capacitor C2 are both grounded; and the output end of the Schmitt trigger is used as the output end of the first delay unit.
As shown in fig. 3, in the present embodiment, the dynamic response boost circuit includes a twelfth D flip-flop 301, a thirteenth D flip-flop 302, a fourteenth D flip-flop 303, a fifteenth D flip-flop 304, a sixteenth D flip-flop 305, a seventeenth D flip-flop 306, an eighteenth D flip-flop 307, a third inverter 309, a first nor gate 308, a second nor gate 310, a third nor gate 311, a first and gate 312, and a second or gate 313; the reset terminal of the twelfth D flip-flop 301 and the reset terminals of the thirteenth D flip-flop 302, the fourteenth D flip-flop 303, the fifteenth D flip-flop 304, the sixteenth D flip-flop 305, the seventeenth D flip-flop 306 and the eighteenth D flip-flop 307 are all connected to the input terminal of the third inverter 309 and the output terminal of the load detection circuit comparator, and input a signal load for generating a variable pulse signal controlled by the load signal; the D terminal of the twelfth D flip-flop 301 is connected to the QN terminal thereof, and the Q terminal of the twelfth D flip-flop 301 is connected to the clk terminal of the thirteenth D flip-flop 302; a D terminal of the thirteenth D flip-flop 302 is connected to a QN terminal thereof, and a Q terminal of the thirteenth D flip-flop 302 is connected to a clk terminal of the fourteenth D flip-flop 303; a D terminal of the fourteenth D flip-flop 303 is connected to a QN terminal thereof, and a Q terminal of the fourteenth D flip-flop 303 is connected to a clk terminal of the fifteenth D flip-flop 304; the D terminal of the fifteenth D flip-flop 304 is connected to the QN terminal thereof, and the Q terminal of the fifteenth D flip-flop 304 is connected to the clk terminal of the sixteenth D flip-flop 305; the D terminal of the sixteenth D flip-flop 305 is connected to the QN terminal of the sixteenth D flip-flop 305 and the first input terminal of the first nor gate 308, respectively; the Q terminal of the sixteenth D flip-flop 305 is connected to the clk terminal of the seventeenth D flip-flop 306; the D terminal of the seventeenth D flip-flop 306 is connected to the QN terminal of the seventeenth D flip-flop 306, and the Q terminal of the seventeenth D flip-flop 306 is connected to the clk terminal of the eighteenth D flip-flop 307; the D terminal of the eighteenth D flip-flop 307 is connected to the QN terminal of the eighteenth D flip-flop 307 and the second input terminal of the first nor gate 308, respectively; an output terminal of the first nor gate 308 is connected to a first input terminal of the second nor gate 310, and a second input terminal of the second nor gate 310 is connected to an output terminal of the third nor gate 311; an output end of the third inverter 309 is connected to the first input end of the third nor gate 311, a second input end of the third nor gate 311 is respectively connected to an output end of the second nor gate 310 and a first input end of a first and gate 312, a second input end of the first and gate 312 is connected to a Q end of the ninth D flip-flop 214 and receives a signal clk 2; an output end of the first and gate 312 is connected to a first input end of the second or gate 313, a second input end of the second or gate 313 is connected to a Q end of the eleventh D flip-flop 216, and receives a signal clk 3. The output of the second or gate 313 is a Toff _ max pulse signal that controls the maximum off time of the Q1 power transistor shown in fig. 1.
Preferably, in this embodiment, a switching power supply applying the circuit for improving the dynamic response of the power supply system is further provided, which includes a transformer, a peripheral circuit thereof, and a control circuit; the transformer and the peripheral circuit thereof are electrically connected with the control circuit; the transformer and the peripheral circuit thereof comprise a transformer T1, a transformer T1 feedback winding unit, a power tube Q1, a detection resistor RCS, a first diode Do, an output capacitor Cout and an output load Rload; the control circuit is connected with a feedback winding unit of the transformer T1 and used for generating a switching signal to adjust the pulse width and the frequency of the transformer;
the dotted terminal of the secondary winding on the primary side of the transformer T1 is connected with the feedback winding unit of the transformer T1; the synonym end of the secondary winding on the primary side of the transformer T1 is grounded; the dotted terminal of the primary side first winding of the transformer T1 is connected to the drain electrode of the power tube Q1; the source electrode of the power tube Q1 is connected with one end of the detection resistor RCS; the grid electrode of the power tube Q1 is connected with the control circuit; the other end of the detection resistor RCS is grounded; the synonym end of the primary side first winding of the transformer T1 is connected with the input voltage; the dotted end of the transformer T1 side winding is connected with the anode of the first diode Do; the cathode of the first diode Do is connected with one end of the output capacitor Cout and one end of the output load Rload respectively; the other end of the output capacitor Cout is respectively connected with the synonym end of the amplitude winding of the transformer T1 and the other end of the output load Rload and is grounded at the same time;
the transformer T1 is connected with a feedback winding unit and comprises a second diode D1, a voltage division resistor R and a first capacitor C1; one end of the divider resistor R is connected with one end of the first capacitor C1 and is grounded at the same time; the other end of the first capacitor C1 is connected with the cathode of the second diode D1; the anode of the second diode D1 is connected with the other end of the divider resistor R and is connected with the same-name end of the secondary winding on the primary side of the transformer T1;
the control circuit comprises a circuit for improving the dynamic response of the power supply system and a logic drive circuit; the circuit for improving the dynamic response of the power supply system is electrically connected with the logic driving circuit; the logic circuit is connected to the gate of the power transistor Q1 as shown in fig. 10, and is configured to transmit the Toff _ max pulse signal, and control the maximum off time of the Q1 power transistor through the signal.
Preferably, in this embodiment, the circuit for improving the dynamic response of the power system is integrated into one integrated block.
The circuit for improving the dynamic response of the power supply system generates a variable pulse signal controlled by a load signal which is an output signal of the load detection circuit.
Preferably, in this embodiment, the circuit for improving the dynamic response of the power supply system generates a minimum operating frequency of the switching power supply using the circuit.
Preferably, in this embodiment, the sample-and-hold circuit, the error amplifying circuit, the load detecting circuit, the clock dividing circuit, the dynamic response boosting circuit, and the logic driving circuit are integrated into an integrated package.
Preferably, the circuit for improving dynamic response of a power system of this embodiment can detect load changes of the power system, and by setting the maximum fast dynamic response time of the system, the minimum operating frequency of the switching system realizes fast dynamic response during load switching within a certain time range. The switching power supply includes a transformer and a control circuit. The control circuit judges the load state of the system by carrying out platform sampling on the voltage signal generated by the auxiliary winding unit of the transformer, and switches the minimum working frequency of the system according to the load state, so that the dynamic response speed of the power supply system is improved. The control circuit comprises the circuit for improving the dynamic response of the power supply system, and the switching power supply can realize the performance of quick dynamic response.
Preferably, in this embodiment, the parameters shown in fig. 1 to 8 have the following meanings: t1: transformer device
Vo: output voltage
Vin: input voltage
Do: output rectifier diode
Cout: output capacitor
VCC: chip supply voltage
FB: feedback signal of transformer auxiliary winding
RCS: transformer primary inductive current detection resistor
Rload: output load
Q1: power tube
VSH: sample and hold output signal
Tsp: pulse sampling signal in demagnetization time
Vea: error amplifier output signal
Vref1, Vref 2: reference voltage
And Vload: load detection circuit output signal
Fmin: minimum operating frequency of system
clk 1: fixed high frequency clock signal
clk2, clk 3: clk1 frequency divided signal
Tclk 1: cycle time of clk1 signal
Tclk 2: half cycle time of clk2 signal
Tclk 3: half cycle time of clk3 signal
Tsw: in the working period of the system, the power tube Q1 is switched on at a high level, and the power tube Q1 is switched off at a low level
VA: the output signal of the nor gate 310
Toff _ max: maximum off time of the system, reciprocal of minimum operating frequency Fmin
Δ Vout, Δ V1, Δ V2: variation value of output voltage
Vout: output voltage signal
As shown in fig. 1, FB is connected to the sample-and-hold circuit to detect the auxiliary coil stage voltage and output a VSH voltage signal, the VSH signal is input to the inverting input terminal of the error amplifying circuit, the non-inverting input terminal of the error amplifying circuit is connected to the Vref1 reference voltage, the two signals are subjected to error comparison and amplification and output a Vea signal and input to the inverting input terminal of the load detecting circuit, the non-inverting input terminal of the load detecting circuit is connected to the Vref2 reference voltage, and the two signals are compared and output a control signal load. The load signal is input to the dynamic response boost circuit; the clock frequency dividing circuit generates clock signals clk2 and clk3 to be input into the dynamic response lifting circuit; the dynamic response improving circuit changes the minimum working frequency through switching of clk2 and clk3 signals, and improves the dynamic response of the power supply system.
For a better understanding of the present embodiment, the following description is provided to further describe the operation principle of the present embodiment with reference to the circuit:
as shown in fig. 5, VSH is a voltage signal obtained by sampling the platform voltage of the auxiliary coil by the sample-and-hold circuit, the signal and the reference voltage Vref1 pass through a fixed gain error amplifier to obtain an output signal Vea, Vea is compared with the reference voltage Vref2 to obtain a load signal, the load state is determined according to the load waveform, and when the load signal is at a low level, the load is medium-heavy load; when the load signal is high, the load is light.
Fig. 6 shows a clock dividing signal diagram controlled by Tsw, when Tsw jumps from high level to low level, the clock dividing signal starts to divide after a fixed delay unit (203 shown in fig. 2) time delay, as long as the time that Tsw is low level is long enough, after 256 Tclk1, the clk2 signal jumps from low level to high level, and so on, after 1024 Tclk1, the clk3 jumps from low level to high level, and in this example, Tclk3 is selected to be 4 Tclk 2.
FIG. 7 is a diagram of the main working signals of the Tsw frequency divider circuit (circuit part in FIG. 3) controlled by the load signal, wherein when the load signal is at low level, the D flip-flops (301-307) are used for resetting the circuit of the frequency divider, and controlling VA to be at high level at this time; when load jumps from low level to high level, the D trigger starts working, VA keeps high level, and Toff _ max time is Tclk 2; after 80 Tsw cycles, VA transitions low and Toff _ max time switches to Tclk 3.
The obtained fast dynamic response transformation time is set as Tdyna：
Tdyna＝80×Tclk2＝80×256×Tclk1 (3)
The high level time of the Tsw time is ignored in equation (3). From equation (3) and FIG. 8, it can be seen that when the system is at TdynaWhen the load is changed within the time, the maximum output voltage drop is Toff _ max, the time is Tclk2, and at this time, the maximum change quantity delta V of the output voltage is assumed to be when the load is changed from 0A to 1A according to the formula (1)outΔ V1:
similarly, when Toff _ max is switched to Tclk3, there is Δ VoutΔ V2:
comparing the two formulae (4) and (5), formula (6) can be obtained:
as shown in formula (6), the present invention is represented by formula TdynaThe drop voltage is obviously reduced within a period of time, and the rapid dynamic response is realized. Therefore, the invention sets a fixed quick dynamic response detection time TdynaAnd the output frequency is changed in a mode of controlling the conversion of Toff _ max during the time, so that the fast dynamic response of the switching power supply is realized.
It is worth mentioning that the utility model protects a hardware structure, as for the control method does not require protection. The above is only a preferred embodiment of the present invention. However, the present invention is not limited to the above embodiments, and any equivalent changes and modifications made according to the present invention do not exceed the scope of the present invention, and all belong to the protection scope of the present invention.
Claims (8)
1. A circuit for improving dynamic response of a power supply system is characterized in that: the circuit comprises a sampling hold circuit, an error amplification circuit, a load detection circuit, a clock frequency division circuit and a dynamic response lifting circuit; the sampling and holding circuit is respectively electrically connected with a transformer feedback winding unit in a power supply system and the error amplifying circuit and is used for carrying out error comparison and amplification on a voltage VSH output after the feedback voltage FB is subjected to platform sampling and a reference voltage Vref1 input into the error amplifying circuit through the error amplifying circuit and outputting an error voltage signal Vea; the error amplifying circuit is electrically connected with the load detection circuit and is used for comparing the error voltage signal Vea with a reference voltage Vref2 input into the load detection circuit through the load detection circuit and then outputting a load judgment signal load; the load detection circuit is electrically connected with the dynamic response lifting circuit and is used for inputting the load judgment signal load to the dynamic response lifting circuit; the clock frequency division circuit is electrically connected with the dynamic response boost circuit and is used for inputting clock signals clk2 and clk3 to the dynamic response boost circuit, and the dynamic response boost circuit changes the minimum working frequency through switching the clk2 and clk3 signals so as to boost the dynamic response of the power supply system.
2. The circuit of claim 1, wherein the circuit further comprises: the sample-and-hold circuit comprises a controlled switch K1 and a first capacitor C1 electrically connected with the controlled switch K1; one end of the controlled switch K1 is connected with a feedback voltage FB, the other end of the controlled switch K1 is connected with the upper pole plate of the first capacitor C1, and a control end of the controlled switch K1 inputs a sampling control signal Tsp; the lower plate of the first capacitor is grounded, and the upper plate of the first capacitor outputs a voltage signal VSH.
3. The circuit of claim 1, wherein the circuit further comprises: the error amplification circuit adopts a fixed gain amplifier, the non-inverting input end of the fixed gain amplifier is connected with a reference voltage Vref1, the inverting input end of the fixed gain amplifier is connected with the output end of the sample-and-hold circuit and inputs a voltage VSH, and the output end of the fixed gain amplifier is used as the output end of the error amplification circuit and is connected with the input end of the load detection circuit and outputs a voltage Vea.
4. The circuit of claim 1, wherein the circuit further comprises:
the load detection circuit adopts a comparator, the non-inverting input end of the comparator is used as the input end of the load detection circuit, is connected with the output end of the error amplification circuit, and inputs voltage Vea; the inverting input end of the comparator is connected with a reference voltage Vref2, and the output end of the comparator is used as the output end of the load detection circuit, is connected with the dynamic response lifting circuit and outputs a load judgment signal load.
5. The circuit of claim 1, wherein the circuit further comprises:
the clock frequency division circuit comprises a first inverter, a second inverter, a first delay unit, a first NAND gate, a first OR gate, a first D trigger, a second D trigger, a third D trigger, a fourth D trigger, a fifth D trigger, a sixth D trigger, a seventh D trigger, an eighth D trigger, a ninth D trigger, a tenth D trigger and an eleventh D trigger; the input end of the first inverter inputs a power system working period Tsw signal, and the output of the first inverter is respectively connected with the first input end of the first NAND gate and the input end of the second inverter; the output end of the second inverter is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the second input end of the first nand gate, and the output end of the first nand gate is respectively connected with the reset end of the first D flip-flop and the reset ends of the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, the ninth D flip-flop, the tenth D flip-flop and the eleventh D flip-flop; a first input end of the first OR gate inputs a power supply system working period Tsw signal, a second input end of the first OR gate inputs a fixed high-frequency clock signal clk1, and an output end of the first OR gate is connected with a clk end of the first D flip-flop; the D end of the first D trigger is connected with the QN end of the first D trigger, and the Q end of the first D trigger is connected with the clk end of the second D trigger; the D end of the second D trigger is connected with the QN end of the second D trigger, and the Q end of the second D trigger is connected with the clk end of the third D trigger; the D end of the third D trigger is connected with the QN end of the third D trigger, and the Q end of the third D trigger is connected with the clk end of the fourth D trigger; a D end of the fourth D flip-flop is connected with a QN end thereof, and a Q end of the fourth D flip-flop is connected with a clk end of the fifth D flip-flop; a D end of the fifth D flip-flop is connected with a QN end thereof, and a Q end of the fifth D flip-flop is connected with a clk end of the sixth D flip-flop; a D end of the sixth D flip-flop is connected to a QN end thereof, and a Q end of the sixth D flip-flop is connected to a clk end of the seventh D flip-flop; a D end of the seventh D flip-flop is connected to a QN end thereof, and a Q end of the seventh D flip-flop is connected to a clk end of the eighth D flip-flop; a D end and a QN end of the eighth D flip-flop are connected, and a Q end of the eighth D flip-flop is connected to a clk end of the ninth D flip-flop; a D end of the ninth D flip-flop is connected to a QN end thereof, and a Q end of the ninth D flip-flop is connected to a clk end of the tenth D flip-flop; a D end of the tenth D flip-flop is connected to a QN end thereof, and a Q end of the tenth D flip-flop is connected to a clk end of the eleventh D flip-flop; the D end of the eleventh D trigger is connected with the QN end thereof; the Q end of the ninth D flip-flop outputs a frequency-divided signal clk2, and the Q end of the eleventh D flip-flop outputs a frequency-divided signal clk 3.
6. The circuit of claim 5, wherein the circuit further comprises:
the first delay circuit comprises a first bias current source, a delay capacitor C2, a Schmitt trigger, a second switch K2 and a third switch K3; the second switch K2 and the third switch K3 are used as input ends of the first delay unit and are controlled by the input end of the first delay unit; a power supply Vdd is respectively connected with one end of the delay capacitor C2, one end of the third switch K3 and the input end of the Schmitt trigger through a second switch K2; the other end of the third switch K3 is connected with one end of the first bias current source, and the other end of the first bias current source and the other end of the delay capacitor C2 are both grounded; and the output end of the Schmitt trigger is used as the output end of the first delay unit.
7. The circuit of claim 5, wherein the circuit further comprises: the dynamic response boost circuit comprises a twelfth D trigger, a thirteenth D trigger, a fourteenth D trigger, a fifteenth D trigger, a sixteenth D trigger, a seventeenth D trigger, an eighteenth D trigger, a third inverter, a first NOR gate, a second NOR gate, a third NOR gate, a first AND gate and a second OR gate; the reset end of the twelfth D trigger and the reset ends of the thirteenth D trigger, the fourteenth D trigger, the fifteenth D trigger, the sixteenth D trigger, the seventeenth D trigger and the eighteenth D trigger are connected with the input end of the third inverter and the output end of the load detection circuit comparator, and input a load judgment signal load for generating a variable pulse signal controlled by the load judgment signal load; a D end of the twelfth D flip-flop is connected with a QN end thereof, and a Q end of the twelfth D flip-flop is connected with a clk end of the thirteenth D flip-flop; a D end of the thirteenth D flip-flop is connected to a QN end thereof, and a Q end of the thirteenth D flip-flop is connected to a clk end of the fourteenth D flip-flop; a D end of the fourteenth D flip-flop is connected to a QN end thereof, and a Q end of the fourteenth D flip-flop is connected to a clk end of the fifteenth D flip-flop; a D end of the fifteenth D flip-flop is connected to a QN end thereof, and a Q end of the fifteenth D flip-flop is connected to a clk end of the sixteenth D flip-flop; the D end of the sixteenth D flip-flop is connected to the QN end of the sixteenth D flip-flop and the first input end of the first nor gate respectively; the Q end of the sixteenth D flip-flop is connected with the clk end of the seventeenth D flip-flop; a D end of the seventeenth D flip-flop is connected with a QN end of the seventeenth D flip-flop, and a Q end of the seventeenth D flip-flop is connected with a clk end of the eighteenth D flip-flop; the D end of the eighteenth D trigger is respectively connected with the QN end of the eighteenth D trigger and the second input end of the first NOR gate; the output end of the first NOR gate is connected with the first input end of the second NOR gate, and the second input end of the second NOR gate is connected with the output end of the third NOR gate; the output end of the third inverter is connected with the first input end of the third nor gate, the second input end of the third nor gate is respectively connected with the output end of the second nor gate and the first input end of the first and gate, and the second input end of the first and gate is connected with the Q end of the ninth D flip-flop and receives a signal clk 2; the output end of the first and gate is connected with the first input end of the second or gate, the second input end of the second or gate is connected with the Q end of the eleventh D flip-flop, and receives a signal clk 3; the output terminal of the second or gate outputs a Toff _ max pulse signal.
8. A switching power supply using the circuit for improving dynamic response of a power supply system according to claim 7, wherein: the transformer comprises a transformer, a peripheral circuit and a control circuit; the transformer and the peripheral circuit thereof are electrically connected with the control circuit; the transformer and the peripheral circuit thereof comprise a transformer T1, a transformer T1 feedback winding unit, a power tube Q1, a detection resistor RCS, a first diode Do, an output capacitor Cout and an output load Rload; the control circuit is connected with a feedback winding unit of the transformer T1 and used for generating a switching signal to adjust the pulse width and the frequency of the transformer;
the dotted terminal of the secondary winding on the primary side of the transformer T1 is connected with the feedback winding unit of the transformer T1; the synonym end of the secondary winding on the primary side of the transformer T1 is grounded; the dotted terminal of the primary side first winding of the transformer T1 is connected to the drain electrode of the power tube Q1; the source electrode of the power tube Q1 is connected with one end of the detection resistor RCS; the grid electrode of the power tube Q1 is connected with the control circuit; the other end of the detection resistor RCS is grounded; the synonym end of the primary side first winding of the transformer T1 is connected with the input voltage; the dotted end of the transformer T1 side winding is connected with the anode of the first diode Do; the cathode of the first diode Do is connected with one end of the output capacitor Cout and one end of the output load Rload respectively; the other end of the output capacitor Cout is respectively connected with the synonym end of the amplitude winding of the transformer T1 and the other end of the output load Rload and is grounded at the same time;
the transformer T1 is connected with a feedback winding unit and comprises a second diode D1, a voltage division resistor R and a third capacitor C3; one end of the divider resistor R is connected with one end of the third capacitor C3 and is grounded at the same time; the other end of the third capacitor C3 is connected with the cathode of the second diode D1; the anode of the second diode D1 is connected with the other end of the divider resistor R and is connected with the same-name end of the secondary winding on the primary side of the transformer T1;
the control circuit comprises the circuit for improving the dynamic response of the power supply system and a logic driving circuit according to claim 7; the circuit for improving the dynamic response of the power supply system is electrically connected with the logic driving circuit; the logic driving circuit is connected to the gate of the power transistor Q1, and is configured to transmit the Toff _ max pulse signal, and control the maximum off time of the power transistor Q1 according to the Toff _ max pulse signal.
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| CN114301263A (en) * | 2021-12-28 | 2022-04-08 | 漳州科华电气技术有限公司 | Control method and device for improving dynamic response of switching power supply circuit and terminal |
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| CN114301263A (en) * | 2021-12-28 | 2022-04-08 | 漳州科华电气技术有限公司 | Control method and device for improving dynamic response of switching power supply circuit and terminal |
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