CN117375605B - Process corner mismatch calibration circuit architecture and electronic device - Google Patents
Process corner mismatch calibration circuit architecture and electronic device Download PDFInfo
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- CN117375605B CN117375605B CN202311649962.5A CN202311649962A CN117375605B CN 117375605 B CN117375605 B CN 117375605B CN 202311649962 A CN202311649962 A CN 202311649962A CN 117375605 B CN117375605 B CN 117375605B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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Abstract
The invention relates to the technical field of calibration circuit architecture, in particular to a process corner mismatch calibration circuit architecture and an electronic device, wherein the circuit architecture comprises: a reference voltage generating circuit for generating and outputting a reference voltage; the current generation circuit is electrically connected with the output end of the reference voltage generation circuit and is used for generating and outputting current. The reference voltage is generated by the reference voltage generating circuit, the current is generated by the current generating circuit and flows through the switched capacitor integrating circuit to generate a high-bit-number high-precision code word, and the low-bit-number code word is output to the corresponding circuit module for use after the code word is mapped. Under the condition that the area of the resistor-capacitor array used for calibration by the circuit module is not increased, the calibration precision of the process angle is improved, and the process stability requirement of most of process-sensitive high-precision analog chips is met.
Description
Technical Field
The invention relates to the technical field of calibration circuit architecture, in particular to a process corner mismatch calibration circuit architecture and an electronic device.
Background
With the continuous development of the chip manufacturing process, each circuit module in the prior process chip can greatly deteriorate the performance (the fluctuation of resistance value is +/-15%, the fluctuation of capacitance value is +/-25%) along with the fluctuation of process angle, so that the corresponding circuit module is required to calibrate the influence caused by the process mismatch.
The existing technology for calibrating the process angle mismatch generally comprises calibrating the resistance and the capacitance and then directly sending the calibration result to a corresponding circuit module for use. However, generally, due to area or power consumption consideration, the number of bits of the resistor-capacitor array used by the actual circuit module is small, the adjustment range is limited, certain errors exist after process calibration, and the precision is not high enough.
Disclosure of Invention
Therefore, the present invention is directed to a process corner mismatch calibration circuit architecture and an electronic device, which can improve the calibration accuracy of a circuit process corner without increasing the area of a resistor-capacitor array of a circuit module.
In a first aspect, an embodiment of the present invention provides a process corner mismatch calibration circuit architecture, including:
a reference voltage generating circuit for generating and outputting a reference voltage;
the current generation circuit is electrically connected with the output end of the reference voltage generation circuit and is used for generating and outputting current;
the switch capacitance integrating circuit is respectively connected with the reference voltage generating circuit and the current generating circuit;
the input end of the codeword output and mapping circuit is electrically connected with the output end of the switched capacitor integration circuit, and the output end of the codeword output and mapping circuit is connected with the target circuit; the codeword output and mapping circuit is for outputting codewords for provision to a target circuit.
With reference to the first aspect, the reference voltage generating circuit includes: the band gap reference circuit, the second resistor and the third resistor;
the output end of the band gap reference circuit is sequentially connected with a second resistor and a third resistor and then grounded;
the bandgap reference circuit generates a first reference voltage VREF and then divides the first reference voltage VREF by the second resistor to obtain a second reference voltage VCOM.
With reference to the first aspect, the current generation circuit includes: the second operational amplifier, the first resistor, the first switching element, the first MOS tube and the second MOS tube;
the sources of the first MOS tube and the second MOS tube are respectively and electrically connected with a power supply VDD; the drain electrode of the first MOS tube is electrically connected with the first resistor and the first switching element and then grounded;
the positive electrode input end of the second operational amplifier is electrically connected with the drain electrode of the first MOS tube and the first resistor; the positive electrode input end of the second operational amplifier is electrically connected with a first reference voltage VREF generated by the band gap reference circuit; the output end of the second operational amplifier is electrically connected with the grid electrodes of the first MOS tube and the second MOS tube respectively;
the drain electrode of the second MOS tube is an output end of the current generating circuit and is used for outputting current.
With reference to the first aspect, the switched capacitor integration circuit includes: a first operational amplifier, first to second capacitors, second to seventh switches, and an inverter INV;
one side of the first capacitor is electrically connected with the second switch and the fourth switch, and the other side of the first capacitor is electrically connected with the third switch and the fifth switch;
one side of the second capacitor is electrically connected with a third switch, a sixth switch, the seventh switch and the negative input end of the first operational amplifier; the other side is electrically connected with the seventh switch and the output end of the first operational amplifier; the output end of the first operational amplifier is the output end of the switched capacitor integration circuit and is used for outputting voltage VO;
the positive input end of the first operational amplifier is electrically connected with the fifth switch, the fourth switch and the second reference voltage VCOM output by the reference voltage generating circuit.
With reference to the first aspect, the switched capacitor integration circuit further includes: an inverter;
the input end of the inverter is electrically connected with the second switch and the fifth switch, and the output end of the inverter is electrically connected with the fourth switch and the fifth switch.
With reference to the first aspect, the codeword output and mapping circuit includes: the comparator, the digital control module and the code word mapping module are connected in sequence; the digital control module is connected with the first to third input signals, and the third input signal is also electrically connected with the inverter.
With reference to the first aspect, an input end of the comparator is electrically connected with an output end of the switched capacitor integrator and the second reference voltage VCOM; the output end of the comparator is electrically connected with the digital control module to generate and output a CMP_OUT signal to the digital control module.
With reference to the first aspect, the digital control module is internally provided with a counter, and the input of the digital control module is electrically connected with the clock circuit;
the digital control module is used for outputting an enabling signal to control the first operational amplifier, the second operational amplifier, the comparator and the first switch to switch working states, and is also used for outputting a calibration control time sequence signal and a first bit digital CODE word CODE0.
With reference to the first aspect, an input end of the codeword mapping module is connected with an output end of the digital control module, and an output end of the codeword mapping module is electrically connected with a target circuit architecture;
the code word mapping module receives the first bit digital code word signal and a preset control signal, processes the first bit digital code word signal according to a preset rule, and outputs a target bit digital code word signal to a target circuit architecture.
In a second aspect the present application provides an electronic device comprising a chip on which a circuit architecture as described above is integrated.
The embodiment of the invention has the following beneficial effects: the invention provides a process corner mismatch calibration circuit architecture and an electronic device, wherein the circuit architecture comprises: a reference voltage generating circuit for generating and outputting a reference voltage; the current generation circuit is electrically connected with the output end of the reference voltage generation circuit and is used for generating and outputting current; the switch capacitance integrating circuit is respectively connected with the reference voltage generating circuit and the current generating circuit; the input end of the codeword output and mapping circuit is electrically connected with the output end of the switched capacitor integration circuit, and the output end of the codeword output and mapping circuit is connected with the target circuit; the codeword output and mapping circuit is for outputting codewords for provision to a target circuit. The reference voltage is generated by the reference voltage generating circuit, the current is generated by the current generating circuit and flows through the switched capacitor integrating circuit to generate a high-bit-number high-precision code word, and the low-bit-number code word is output to the corresponding circuit module for use after the code word is mapped. Under the condition that the area of the resistor-capacitor array used for calibration by the circuit module is not increased, the calibration precision of the process angle is improved, and the process stability requirement of most of process-sensitive high-precision analog chips is met.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a process corner mismatch calibration circuit architecture according to an embodiment of the present invention;
fig. 2 is a timing diagram of an embodiment of a process corner mismatch calibration circuit architecture according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to facilitate understanding of the present embodiment, technical terms designed in the present application will be briefly described below.
Enabling: is responsible for the input and output of control signals, and is commonly referred to as an "enable" signal, and the feed enable signal is a signal that enables the feed, that is, the motor can only rotate when the feed enable signal is active.
The switch capacitor integrating circuit uses a switch to continuously switch the charging and discharging states of the capacitor to simulate the action of a resistor; the equivalent resistance value can be set by the switching frequency, is used in the filter, and can conveniently adjust the cut-off frequency of the filter.
Band gap English is bandgap, and in daily use, we also call BG.
The main purpose of the bandgap reference circuit is to generate a temperature independent reference (or a reference that has little temperature dependence).
VREF (Voltage reference), the reference voltage, which refers to a voltage in the circuit that is constant throughout regardless of load, power supply, temperature drift, time, etc. The reference voltage may be used in voltage regulators of power supply systems, analog-to-digital converters and digital-to-analog converters, as well as many other measurement and control systems.
After technical terms related to the application are introduced, application scenes and design ideas of the embodiment of the application are briefly introduced.
The existing technology for calibrating the process angle mismatch generally comprises calibrating the resistance and the capacitance and then directly sending the calibration result to a corresponding circuit module for use. However, generally, due to area or power consumption consideration, the number of bits of the resistor-capacitor array used by the actual circuit module is small, the adjustment range is limited, certain errors exist after process calibration, and the precision is not high enough.
The circuit structure for calibrating the process corner mismatch is provided based on the application, so that the calibration precision of the circuit process corner is improved under the condition that the area of the resistor-capacitor array of the circuit module is not increased.
Example 1
Referring to fig. 1, the present application provides a process corner mismatch calibration circuit architecture, which includes: a reference voltage generating circuit 1, a current generating circuit 2, a switched capacitor integrating circuit 3 and a codeword output and mapping circuit 4.
The reference voltage generation circuit 1 is used for generating and outputting a reference voltage.
The current generating circuit 2 is electrically connected to the output terminal of the reference voltage generating circuit 1, and the current generating circuit 2 is used for generating and outputting a current.
The switched capacitor integrating circuit 3 is connected to the reference voltage generating circuit 1 and the current generating circuit 2, respectively.
The input end of the codeword output and mapping circuit 4 is electrically connected with the output end of the switched capacitor integration circuit 3, and the output end of the codeword output and mapping circuit 4 is connected with the target circuit; codeword output and mapping circuit 4 is used to output codewords for provision to a target circuit.
With reference to the first aspect, the reference voltage generating circuit includes: a bandgap reference circuit (in combination with BG in fig. 1), a second resistor (in combination with R2 in the figure), and a third resistor (in combination with R3 in the figure);
the output end of the band gap reference circuit is sequentially connected with the second resistor and the third resistor and then grounded.
The bandgap reference circuit generates a first reference voltage VREF and then divides the first reference voltage VREF by a second resistor to obtain a second reference voltage VCOM.
In combination with the first aspect, the current generation circuit 2 includes: the second operational amplifier (OP 2 in the combination diagram), the first resistor (R1 in the combination diagram), the first switching element (S1 in the combination diagram), the first MOS tube (M1 in the combination diagram) and the second MOS tube (M2 in the combination diagram).
The sources of the first MOS tube M1 and the second MOS tube M2 are respectively and electrically connected with a power supply VDD; the drain electrode of the first MOS transistor M1 is electrically connected to the first resistor R1 and the first switching element S1, and then grounded.
The positive electrode input end of the second operational amplifier OP2 is electrically connected with the drain electrode of the first MOS tube M1 and the first resistor R1; the positive input end of the second operational amplifier OP2 is electrically connected with a first reference voltage VREF generated by the band gap reference circuit BG; the output end of the second operational amplifier OP2 is electrically connected with the grid electrodes of the first MOS tube M1 and the second MOS tube M2 respectively.
The drain electrode of the second MOS tube M2 is an output end of the current generating circuit and is used for outputting current.
With reference to the first aspect, the switched capacitor integration circuit 3 includes: a first operational amplifier (OP 1 in the figure), first to second capacitors, and second to seventh switches;
one side of the first capacitor (C1 in the combination diagram) is electrically connected with the second switch (S1 in the combination diagram) and the fourth switch (S4 in the combination diagram), and the other side of the first capacitor is electrically connected with the third switch (S3 in the combination diagram) and the fifth switch (S5 in the combination diagram);
one side of the second capacitor (C2 in the combination diagram) is electrically connected with the negative input ends of the third switch S3, the sixth switch (S6 in the combination diagram), the seventh switch S7 and the first operational amplifier (OP 1 in the combination diagram); the other side is electrically connected with the seventh switch S7 and the output end of the first operational amplifier OP 1; the output end of the first operational amplifier OP1 is the output end of the switched capacitor integration circuit 3 and is used for outputting the voltage VO;
the positive input terminal of the first operational amplifier OP1 is electrically connected to the fifth switch S5, the fourth switch S4 and the second reference voltage VCOM output by the reference voltage generating circuit 1.
With reference to the first aspect, the switched capacitor integration circuit 3 further includes: an inverter (with INV in the figure).
The input end of the inverter INV is electrically connected with the second switch S2 and the fifth switch S5, and the output end of the inverter INV is electrically connected with the fourth switch S4 and the fifth switch S5.
In combination with the first aspect, the codeword output and mapping circuit 4 comprises: a comparator (CMP in conjunction with fig. 1), a digital control module 41 and a codeword mapping module 42 connected in sequence; the digital control module 41 is connected to the first to third input signals, and the third input signal is also electrically connected to an Inverter (INV).
With reference to the first aspect, an input end of the comparator CMP is electrically connected to an output end of the switched capacitor integrator 3 and the second reference voltage VCOM; the output terminal of the comparator CMP is electrically connected to the digital control module 41 to generate and output a cmp_out signal to the digital control module 41.
With reference to the first aspect, the digital control module 41 is internally provided with a counter, and the input of the digital control module 41 is electrically connected with a clock circuit (CLK in the combination diagram);
the digital control module 41 is configured to output an enable signal to control the first operational amplifier OP1, the second operational amplifier OP2, the comparator CMP and the first switch S1 to switch the working states, and the digital control module 41 is further configured to output a calibration control timing signal and the first bit digital CODE word CODE0.
With reference to the first aspect, an input end of the codeword mapping module 42 is connected to an output end of the digital control module 41, and an output end of the codeword mapping module 42 is electrically connected to the target circuit architecture;
the codeword mapping module 42 receives the first bit digital word signal and the preset control signal, processes the first bit digital word signal according to a preset rule, and outputs a target bit digital word signal to the target circuit architecture.
An embodiment of the present principles is shown in connection with fig. 1.
The principle of the present technology is described below using a formula derivation form.
As shown in conjunction with the timing diagram of fig. 2, EN0 is enabled high during the calibration phase, and the first OP1, second OP2, comparator CMP and first switch S1 are enabled on.
In the period of 0 to T1, phi 1,In the case of high level, phi 2 and phi 3 are low level, at this time, the third switch S3, the fourth switch S4 and the seventh switch S7 are turned on, the second switch S2, the fifth switch S5 and the sixth switch S6 are turned off, the first operational amplifier OP1 is connected to form a unit gain negative feedback form, the charge on the second capacitor C2 is emptied, and the first operational amplifier OP1 outputs the voltage V 0 The method comprises the following steps: v (V) 0 =V COM 。
In the period of T1-T2, the second capacitor C2 is conducted with phi 2,The high level is phi 1 and phi 3, the low level is phi 3, the third switch S3, the fourth switch S4 and the sixth switch S6 are conducted, the second switch S2 and the fifth switch S5 are connected,The seventh switch S7 is turned off, and the high-precision current I generated by the current generating circuit 2 REF Charging the second capacitor C2 through the sixth switch S6 for N clock cycles T of T1-T2 CLK Thereafter, the first operational amplifier OP1 outputs a voltage V 0 Drop voltage amplitude->。
In the period of T2-T3, phi 1 and phi 2 are low level, phi 3 is according to the period T CLK The second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the first capacitor C1, the second capacitor C2 and the first operational amplifier OP1 form an in-phase switched capacitor integrator, and the first operational amplifier OP1 outputs the voltage V in each clock period 0 Rising a voltage stepC2。
When the digital control module 41 turns over from phi 3, the counter in the digital control module 41 starts counting, V 0 Gradually increase to be equal to V COM At this time, the comparator CMP is turned over, the counter stops counting, and the count value at this time is easily known。
In the period of T3-T4, the first operational amplifier OP1 outputs the voltage V 0 The increase continues but the comparator CMP in the digital control module 41 has stopped counting.
After the T4 period, the calibration enable signal EN0 is low, and the calibration is ended.
In order to maintain high precision, the digital control module 41 outputs the codeword CODE0 with high bit number and large value, which cannot be directly used by the corresponding circuit module, and the codeword CODE0 needs to be processed by the codeword mapping module.
CODE0 is multiplied by a constant value a1 (0-1), and a CODE word CODE1 is obtained after linear reduction; then multiplying the CODE word with an externally adjustable variable a2, and scaling to obtain a CODE word CODE2; then, the CODE word CODE3 is obtained by making a difference with a fixed value b 1; finally, adding the CODE word RC_CODE with an externally adjustable variable b2 (which can be positive or negative) to obtain a CODE word RC_CODE, and finally, outputting the CODE word RC_CODE for a corresponding circuit module. Wherein, a1, a2, b1 and b2 are set according to the actual application scene.
In a second aspect, the present application provides an electronic device comprising a chip on which the above-described circuit architecture is integrated.
The computer program product provided by the embodiment of the present invention includes a computer readable storage medium storing program codes, where the instructions included in the program codes may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the method embodiment and will not be described herein.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood by those skilled in the art in specific cases.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention for illustrating the technical solution of the present invention, but not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that the present invention is not limited thereto: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (7)
1. A process corner mismatch calibration circuit architecture, comprising:
a reference voltage generating circuit for generating and outputting a reference voltage;
the current generation circuit is electrically connected with the output end of the reference voltage generation circuit and is used for generating and outputting current;
the switch capacitance integrating circuit is respectively connected with the reference voltage generating circuit and the current generating circuit;
the input end of the codeword output and mapping circuit is electrically connected with the output end of the switched capacitor integration circuit, and the output end of the codeword output and mapping circuit is connected with the target circuit; the codeword output and mapping circuit is used for outputting codewords to be provided to the target circuit;
wherein the reference voltage generating circuit includes: the band gap reference circuit, the second resistor and the third resistor; the output end of the band gap reference circuit is sequentially connected with a second resistor and a third resistor and then grounded; the band gap reference circuit generates a first reference voltage VREF and then divides the first reference voltage VREF through the second resistor to obtain a second reference voltage VCOM;
the current generation circuit includes: the second operational amplifier, the first resistor, the first switching element, the first MOS tube and the second MOS tube;
the sources of the first MOS tube and the second MOS tube are respectively and electrically connected with a power supply VDD; the drain electrode of the first MOS tube is electrically connected with the first resistor and the first switching element and then grounded;
the positive electrode input end of the second operational amplifier is electrically connected with the drain electrode of the first MOS tube and the first resistor; the negative input end of the second operational amplifier is electrically connected with a first reference voltage VREF generated by the band gap reference circuit; the output end of the second operational amplifier is electrically connected with the grid electrodes of the first MOS tube and the second MOS tube respectively;
the drain electrode of the second MOS tube is an output end of the current generating circuit and is used for outputting current;
the switched capacitor integrating circuit includes: a first operational amplifier, first to second capacitors, second to seventh switches, and an inverter INV;
one side of the first capacitor is electrically connected with the second switch and the fourth switch, and the other side of the first capacitor is electrically connected with the third switch and the fifth switch;
one side of the second capacitor is electrically connected with a third switch, a sixth switch, the seventh switch and the negative input end of the first operational amplifier; the other side is electrically connected with the seventh switch and the output end of the first operational amplifier; the output end of the first operational amplifier is the output end of the switched capacitor integration circuit and is used for outputting voltage VO; the sixth switch is connected with the output end of the current generation circuit;
the positive input end of the first operational amplifier is electrically connected with the fifth switch, the fourth switch and the second reference voltage VCOM output by the reference voltage generating circuit.
2. The circuit architecture of claim 1, wherein the switched-capacitor integrating circuit further comprises: an inverter;
the input end of the inverter is electrically connected with the second switch and the fifth switch, and the output end of the inverter is electrically connected with the fourth switch and the third switch.
3. The circuit architecture of claim 2, wherein the codeword output and mapping circuit comprises: the comparator, the digital control module and the code word mapping module are connected in sequence; the digital control module is connected with the first to third input signals, and the third input signal is also electrically connected with the inverter.
4. The circuit architecture of claim 3, wherein,
the input end of the comparator is electrically connected with the output end of the switch capacitor integration and the second reference voltage VCOM; the output end of the comparator is electrically connected with the digital control module to generate and output a CMP_OUT signal to the digital control module.
5. The circuit architecture of claim 4, wherein the digital control module has a counter therein, the digital control module input being electrically connected to the clock circuit;
the digital control module is used for outputting an enabling signal to control the first operational amplifier, the second operational amplifier, the comparator and the first switch to switch working states, and is also used for outputting a calibration control time sequence signal and a first bit digital word signal.
6. The circuit architecture of claim 5, wherein an input of the codeword mapping module is connected to an output of the digital control module, the output of the codeword mapping module being electrically connected to a target circuit architecture;
the code word mapping module receives the first bit digital code word signal and a preset control signal, processes the first bit digital code word signal according to a preset rule, and outputs a target bit digital code word signal to a target circuit architecture.
7. An electronic device comprising a chip having integrated thereon a circuit architecture as claimed in any one of claims 1-6.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004325140A (en) * | 2003-04-22 | 2004-11-18 | Asahi Kasei Electronics Co Ltd | Rotation angle sensor, and calibration device and calibration method therefor |
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| US8552797B2 (en) * | 2011-08-04 | 2013-10-08 | St-Ericsson Sa | High accuracy RC calibradion circuit |
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| CN117375605A (en) | 2024-01-09 |
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