CN114553193B - Clock generation circuit and apparatus insensitive to supply voltage and temperature - Google Patents
Clock generation circuit and apparatus insensitive to supply voltage and temperature Download PDFInfo
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- CN114553193B CN114553193B CN202210448512.9A CN202210448512A CN114553193B CN 114553193 B CN114553193 B CN 114553193B CN 202210448512 A CN202210448512 A CN 202210448512A CN 114553193 B CN114553193 B CN 114553193B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a clock generating circuit and device insensitive to power supply voltage and temperature, comprising: a reference current generating circuit for generating a reference current; an oscillation circuit; the frequency-current conversion circuit is used for receiving an output signal of the oscillation circuit and converting the frequency of the output signal of the oscillation circuit into a corresponding output current signal; and the input end of the control circuit is respectively and electrically connected with the output end of the reference current generating circuit and the output end of the frequency-current converting circuit, and is used for generating corresponding control signals according to the output current of the reference current generating circuit and the output current of the frequency-current converting circuit and outputting the control signals to the oscillating circuit so as to adjust the frequency of the output signals of the oscillating circuit. The invention aims to solve the problem that the clock frequency output by a clock generating circuit is greatly influenced by temperature and power supply voltage.
Description
Technical Field
The present invention relates to the field of clock circuits, and more particularly, to a clock generating circuit and apparatus insensitive to power supply voltage and temperature.
Background
The clock circuit is a very important module in a digital circuit or a hybrid circuit, and a precise crystal oscillator can provide a very precise clock frequency, but the crystal oscillator is not convenient to integrate on a chip. The on-chip reference clock is widely applied to low-power chips.
In a clock generation circuit that is commonly used today, a loop oscillator is used as a means for generating a clock signal, the frequency of the oscillator being related to the on-resistance of the transistors in the inverter and the parasitic capacitance of the output node. The on-resistance of the transistor and the parasitic capacitance of the output of each inverter are greatly affected by variations in the power supply voltage and temperature, and thus the clock frequency of the oscillator output also varies due to variations in the power supply voltage and temperature.
Disclosure of Invention
The invention mainly aims to provide a clock generation circuit and a device which are insensitive to power supply voltage and temperature, and aims to solve the problem that the clock frequency output by the clock generation circuit is greatly influenced by the temperature and the power supply voltage.
To achieve the above object, the present invention provides a clock generation circuit insensitive to supply voltage and temperature, comprising: a reference current generating circuit for generating a reference current;
an oscillation circuit;
the input end of the frequency-current conversion circuit is electrically connected with the output end of the oscillating circuit, and the frequency-current conversion circuit is used for receiving the output signal of the oscillating circuit and converting the frequency of the output signal of the oscillating circuit into a corresponding output current signal;
the input end of the control circuit is respectively electrically connected with the output end of the reference current generating circuit and the output end of the frequency-current converting circuit, the output end of the control circuit is electrically connected with the input end of the oscillating circuit, and the control circuit is used for generating corresponding control signals according to the output current of the reference current generating circuit and the output current of the frequency-current converting circuit and outputting the control signals to the oscillating circuit so as to adjust the frequency of the output signals of the oscillating circuit.
Optionally, the frequency-to-current conversion circuit comprises:
the input end of the non-overlapping clock generation circuit is electrically connected with the output end of the oscillating circuit and is used for converting the output signal of the oscillating circuit into a non-overlapping clock signal;
the controlled end of the switch circuit is electrically connected with the output end of the non-overlapping clock generation circuit, and the switch circuit is used for switching on/off a switch according to the non-overlapping clock signal;
and the input end of the current conversion circuit is electrically connected with the output end of the switch circuit, and the output end of the current conversion circuit is electrically connected with the input end of the control circuit and is used for generating corresponding output current according to the on/off frequency of the switch circuit.
Optionally, the non-overlap clock generating circuit is a two-phase non-overlap clock generating circuit, and is configured to generate a first phase clock signal and a second phase clock signal to control on/off of a switch in the switching circuit.
Optionally, the switch circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch and a fourth switch, a first end of the first switch is electrically connected to a first end of the second switch and an input end of the current converting circuit, respectively, a second end of the first switch is electrically connected to a first end of the third switch, a second end of the second switch is electrically connected to a first end of the fourth switch, a second end of the third switch and a second end of the fourth switch are grounded, the first capacitor is connected in parallel between two ends of the third switch, the second capacitor is connected in parallel between two ends of the fourth switch, the two-phase non-overlapping clock generating circuit is electrically connected to controlled ends of the first switch, the second switch, the third switch and the fourth switch, respectively, the first phase clock signal is used for controlling the first switch and the fourth switch, the second phase clock signal is used to control the second switch and the third switch.
Optionally, the capacitance values of the first and second capacitors are the same.
Optionally, the control circuit comprises:
the input end of the current comparison circuit is respectively and electrically connected with the output end of the reference current generation circuit and the output end of the frequency-current conversion circuit, and the current comparison circuit is used for generating and outputting corresponding charging current according to the output current of the reference current generation circuit and the output current of the frequency-current conversion circuit;
and the input end of the charging circuit is electrically connected with the output end of the current comparison circuit, and the output end of the charging circuit is electrically connected with the input end of the oscillating circuit and is used for charging according to the charging current and outputting a corresponding control signal so as to control the frequency of an output signal of the oscillating circuit.
Optionally, the reference current generating circuit includes a current constant current source and a first MOS transistor, one end of the current constant current source is electrically connected to the drain of the first MOS transistor, the gate of the first MOS transistor, and the input end of the control circuit, respectively, the other end of the current constant current source is electrically connected to the supply voltage, and the source of the first MOS transistor is grounded.
Optionally, the oscillation circuit includes a plurality of inverter units connected in series between the frequency-current conversion circuit and the control circuit.
Optionally, the number of the inverter cells is odd.
The invention proposes a supply voltage and temperature insensitive clock generation device comprising a supply voltage and temperature insensitive clock generation circuit as described above.
The clock generating circuit insensitive to the power supply voltage and temperature is provided with a reference current generating circuit, an oscillating circuit, a frequency-current converting circuit and a control circuit; the input end of the frequency-current conversion circuit is electrically connected with the output end of the oscillation circuit, the input end of the control circuit is respectively electrically connected with the output end of the reference current generation circuit and the output end of the frequency-current conversion circuit, and the output end of the control circuit is electrically connected with the input end of the oscillation circuit. The reference current generating circuit generates reference current, the frequency-current converting circuit receives an output signal of the oscillating circuit and converts the frequency of the output signal of the oscillating circuit into corresponding output current, and the control circuit generates corresponding control signals according to the output current of the reference current generating circuit and the output current of the frequency-current converting circuit and outputs the control signals to the oscillating circuit so as to adjust the frequency of the output signal of the oscillating circuit. When the oscillation circuit starts to start, the frequency of the output signal Vout is small, the output current Iout of the frequency-current conversion circuit is small, the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit is large, and the control signal VCTRL is large, so that the frequency of the output signal Vout of the oscillation circuit is large, and Iout is also large, so that the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit is small, and finally, when Iout = Iref, the control signal VCTRL is stabilized to a certain value, and the frequency of the output Vout of the oscillation circuit is also stabilized to a desired frequency point without being affected by the power supply voltage and temperature changes in the internal structure of the oscillation circuit. The invention solves the problem that the clock frequency output by the clock generating circuit is greatly influenced by temperature and power supply voltage.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of an embodiment of a supply voltage and temperature insensitive clock generation circuit of the present invention;
FIG. 2 is a circuit diagram of an embodiment of the frequency-to-current conversion circuit of FIG. 1;
FIG. 3 is a waveform diagram of output signals of the non-overlap clock generation circuit of FIG. 2 according to an embodiment;
FIG. 4 is a circuit diagram of an embodiment of the reference current generating circuit shown in FIG. 1;
FIG. 5 is a circuit diagram of an embodiment of the control circuit of FIG. 1;
fig. 6 is a circuit configuration diagram of an embodiment of the oscillating circuit in fig. 1.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | Reference current generating |
20 | |
| 21 | |
22 | |
| 30 | Oscillating |
40 | Frequency- |
| 41 | Non-overlapping |
42 | |
| 43 | Current conversion circuit | MP1-MP2 | First P type MOS tube-second P type MOS tube |
| A | Amplifier with a high-frequency amplifier | MN1-MN3 | First N type MOS tube-second N type MOS tube |
| C1-C4 | First capacitor-fourth capacitor | SW1-SW4 | First switch-fourth switch |
The objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
A clock generating circuit insensitive to power supply voltage and temperature is provided, aiming at solving the problem that the clock frequency output by the clock generating circuit is greatly influenced by the temperature and the power supply voltage.
In a clock generation circuit that is commonly used at present, in a clock signal generation device using a loop oscillator, on-resistance of a transistor and parasitic capacitance of an inverter output of each stage are greatly affected by variations in power supply voltage and temperature, and thus a clock frequency of an oscillator output also varies by variations in power supply voltage and temperature.
Referring to fig. 1, in an embodiment of the present invention, the clock generation circuit insensitive to power supply voltage and temperature includes:
a reference current generating circuit 10 for generating a reference current;
an oscillation circuit 30;
a frequency-current conversion circuit 40, an input end of the frequency-current conversion circuit 40 being electrically connected to an output end of the oscillation circuit 30, the frequency-current conversion circuit 40 being configured to receive an output signal of the oscillation circuit 30 and convert a frequency of the output signal of the oscillation circuit 30 into a corresponding output current;
the input end of the control circuit 20 is electrically connected to the output end of the reference current generating circuit 10 and the output end of the frequency-current converting circuit 40, respectively, the output end of the control circuit 20 is electrically connected to the input end of the oscillating circuit 30, and the control circuit 20 is configured to generate a corresponding control signal according to the output current of the reference current generating circuit 10 and the output current of the frequency-current converting circuit 40 and output the control signal to the oscillating circuit 30, so as to adjust the frequency of the output signal of the oscillating circuit 30.
Specifically, the frequency of the output signal Vout of the oscillation circuit 30 is controlled by the control signal VCTRL output from the control circuit 20, and when the control signal VCTRL output from the control circuit 20 is stabilized, the frequency of the output signal Vout of the oscillation circuit 30 is stabilized.
The control signal VCTRL output by the control circuit 20 is determined by the reference current Iref generated by the reference current generating circuit 10 and the output current Iout of the frequency-current converting circuit 40, and the larger the difference between the reference current Iref and the output current Iout of the frequency-current converting circuit 40, the larger the control signal VCTRL generated by the control circuit 20 becomes, and thus the frequency of the output signal Vout of the oscillation circuit 30 controlled by VCTRL becomes.
The frequency-current conversion circuit 40 converts the frequency of the received signal into a corresponding output current, and the frequency-current conversion circuit 40 receives the output signal Vout of the oscillating circuit 30 and converts the frequency of the output signal Vout of the oscillating circuit 30 into a corresponding output current Iout.
When the oscillation circuit 30 starts oscillating, the frequency of the output signal is small, the output current Iout of the frequency-current conversion circuit 40 is small, the difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 is large, the control signal VCTRL output by the control circuit 20 is also large, and thus the frequency of the output signal Vout of the oscillation circuit 30 controlled by VCTRL is large. As the frequency of the output signal Vout of the oscillation circuit 30 becomes larger, the output current Iout of the frequency-current conversion circuit 40 becomes larger, the difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 becomes smaller, and the amplitude of the frequency increase of the control signal VCTRL output by the control circuit 20 controlling the oscillation circuit 30 to generate the output signal also becomes smaller.
When the reference current Iref is equal to the output current Iout of the frequency-current conversion circuit 40, the control signal VCTRL output by the control circuit 20 does not control the frequency change of the output signal Vout of the oscillation circuit 30 any more, the frequency of the output signal Vout of the oscillation circuit 30 is stabilized, and the output current Iout of the frequency-current conversion circuit 40 is also not changed correspondingly, that is, the frequency of the output signal Vout of the oscillation circuit 30 and the frequency of the output signal VCTRL output by the control circuit 20 are not changed any more, and the frequency of the output signal Vout of the oscillation circuit 30 is stabilized.
The frequency stability of the output signal Vout of the oscillator circuit 30 is determined by the stability of the control signal VCTRL output from the control circuit 20, and is not affected by the internal circuit configuration of the oscillator circuit 30.
The working principle of this embodiment is that, during operation, the control circuit 20 receives the reference current Iref and the output current Iout of the frequency-current conversion circuit 40, a current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 is converted into a control signal VCTRL through the integrating capacitor, and the control signal VCTRL is used as the input of the oscillation circuit 30; then, the output signal Vout of the oscillating circuit 30 is fed back to the frequency-current converting circuit 40 to generate the current Iout, which is output to the control circuit 20, thereby forming a negative feedback loop, and the magnitude of the current Iout is proportional to the magnitude of the frequency Vout. When the oscillation circuit 30 starts to start, the frequency of the output signal Vout is small, the output current Iout of the frequency-current conversion circuit 40 is small, the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 is large, the control signal VCTRL controls the frequency of the output Vout of the oscillation circuit 30 to be large, and Iout to be also large, so that the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 is small, and finally, when ut = Iref, the control signal iovctrl is stabilized to be a certain value, the frequency of the output Vout of the oscillation circuit 30 is also stabilized to a desired frequency point without being affected by the power supply voltage and temperature variations in the internal structure of the oscillation circuit 30.
The clock generation circuit insensitive to the power supply voltage and the temperature in the invention is realized by arranging a reference current generation circuit 10, an oscillation circuit 30, a frequency-current conversion circuit 40 and a control circuit 20; an input end of the frequency-current conversion circuit 40 is electrically connected to an output end of the oscillation circuit 30, an input end of the control circuit 20 is electrically connected to an output end of the reference current generation circuit 10 and an output end of the current conversion circuit 43, respectively, and an output end of the control circuit 20 is electrically connected to an input end of the oscillation circuit 30. The reference current generating circuit 10 generates a reference current, the frequency-current converting circuit 40 receives the output signal of the oscillating circuit 30 and converts the frequency of the output signal of the oscillating circuit 30 into a corresponding output current, and the control circuit 20 generates a corresponding control signal according to the output current of the reference current generating circuit 10 and the output current of the current converting circuit 43 and outputs the control signal to the oscillating circuit 30 to adjust the frequency of the output signal of the oscillating circuit 30. When the oscillation circuit 30 starts to start up, the frequency of the output signal Vout is small, the output current Iout of the frequency-current conversion circuit 40 is small, the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 is large, and the control signal VCTRL is also large, so that the frequency of the output signal Vout of the VCTRL control oscillation circuit 30 becomes large, and Iout also becomes large, so that the current difference between the reference current Iref and the output current Iout of the frequency-current conversion circuit 40 becomes small, and finally when Iout = Iref, the control signal VCTRL is stabilized to a certain value, and the frequency of the output Vout of the oscillation circuit 30 is also stabilized to a desired frequency point without being affected by variations in the power supply voltage and temperature in the internal structure of the oscillation circuit 30. The invention solves the problem that the clock frequency output by the clock generating circuit is greatly influenced by temperature and power supply voltage.
Referring to fig. 2, in an embodiment, the frequency-current conversion circuit 40 includes:
a non-overlap clock generation circuit 41, an input terminal of the non-overlap clock generation circuit 41 being electrically connected to an output terminal of the oscillation circuit 30, for converting an output signal of the oscillation circuit 30 into a non-overlap clock signal;
a switch circuit 42, a controlled terminal of the switch circuit 42 being electrically connected to an output terminal of the non-overlap clock generating circuit 41, the switch circuit 42 being configured to turn on/off a switch according to the non-overlap clock signal;
and the input end of the current conversion circuit 43 is electrically connected with the output end of the switch circuit 42, and the output end of the current conversion circuit 43 is electrically connected with the input end of the control circuit 20, and is used for generating corresponding output current according to the on/off frequency of the switch circuit 42.
In this embodiment, the switch circuit 42 can be regarded as a resistor, the non-overlap clock signal is generated from the output signal Vout of the oscillator circuit 30 via the non-overlap clock generating circuit 41 to control the on/off of the switch in the switch circuit 42, and the capacitors C1 and C2 in the switch circuit 42 are periodically charged and discharged by controlling the on/off of the switch in the switch circuit 42, so that the switch circuit 42 can be regarded as a resistor related to the frequency of the output signal Vout of the oscillator circuit 30.
The positive electrode input end of the amplifier a in the current conversion circuit 43 is connected with a voltage value fixed by Vref, the current flowing through the third N-type MOS transistor MN3 is the voltage value of Vref divided by the equivalent resistance value of the switch circuit 42, the current of the third N-type MOS transistor MN3 is changed by changing the resistance value of the switch circuit 42, and the current flowing through the third N-type MOS transistor MN3 generates a mirror current, i.e., an output current Iout of the current conversion circuit 43, by flowing through the second P-type MOS transistor MP 2.
Referring to fig. 2 and 3, in an embodiment, the non-overlap clock generating circuit 41 is a two-phase non-overlap clock generating circuit 41 for generating a first phase clock signal and a second phase clock signal to control on/off of a switch in the switching circuit 42.
In the present embodiment, the output signal Vout of the oscillating circuit 30 passes through the two-phase non-overlapping clock generating circuit 41 to generate the first phase clock signal sa and the second phase clock signal sb, and controls the first switch SW1 to the fourth switch SW 4.
In a period T, a half period sa is high level, and sb is low level; the other half period sa is low and sb is high. The first switch SW1 and the fourth switch SW4 are turned on when sa is high level and turned off when sa is low level; the second switch SW2 and the fourth switch SW3 are turned on when sb is high, and turned off when sb is low.
Referring to fig. 2, in an embodiment, the switch circuit 42 includes a first capacitor C1, a second capacitor C2, a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4, a first end of the first switch SW1 is electrically connected to a first end of the second switch SW2 and an input end of the current converting circuit 43, a second end of the first switch SW1 is electrically connected to a first end of the third switch SW3, a second end of the second switch SW2 is electrically connected to a first end of the fourth switch SW4, a second end of the third switch SW3 and a second end of the fourth switch SW4 are grounded, the first capacitor C1 is connected between two ends of the third switch SW3 in parallel, the second capacitor C2 is connected between two ends of the fourth switch SW4 in parallel, and the two-phase non-clock generating circuit 41 is respectively overlapped with the first switch SW1 and the second switch SW2, The controlled terminals of the third switch SW3 and the fourth switch SW4 are electrically connected, the first phase clock signal is used for controlling the first switch SW1 and the fourth switch SW4, and the second phase clock signal is used for controlling the second switch SW2 and the third switch SW 3.
In the present embodiment, the frequency-current converting circuit 40 receives the output signal Vout of the oscillating circuit 30 and converts the frequency of the output signal Vout of the oscillating circuit 30 into the corresponding output current Iout, and the frequency of the output signal Vout of the oscillating circuit 30 affects the output current Iout.
Assuming that the period of the output signal Vout of the oscillation circuit 30 is T and the frequency is f, the switch circuit 42 formed by the first switch SW 1-the fourth switch SW4, the first capacitor C1 and the second capacitor C2 can be regarded as a resistor, assuming that the capacitance values of the first capacitor C1 and the second capacitor C2 are the same as C, the resistance value of the switch circuit 42 is T/2C, and the voltage value of the current flowing through the third N-type MOS transistor MN3 is Vref divided by the resistance value of the switch circuit 42, that is, Iout is 2C Vref/T.
When the frequency of the output signal Vout of the oscillator circuit 30 is stable, Iout = Iref, i.e., 1/T = Iref/2C × Vref, and the frequency f = Iref/2C × Vref of the output signal Vout of the current conversion circuit 43, therefore, the frequency of the output signal Vout of the oscillator circuit 30 is only related to the capacitance values of the first capacitor C1 and the second capacitor C2, the voltage Vref at the input terminal of the amplifier a, and the reference current Iref.
Referring to fig. 2, in an embodiment, the capacitance values of the first capacitor C1 and the second capacitor C2 are the same.
In the embodiment, the switch circuit 42 composed of the first switch SW 1-the fourth switch SW4, the first capacitor C1 and the second capacitor C2 is formed as a symmetrical structure, the sizes of the first switch SW 1-the fourth switch SW4 are the same, the capacitance values of the first capacitor and the second capacitor are the same, and when the current Iout output by the current conversion circuit 43 is the same as the reference current Iref, that is, Iout = Iref, the duty ratio of the output signal Vout of the oscillation circuit 30 is 50%.
Referring to fig. 5, in one embodiment, the control circuit 20 includes:
the input end of the current comparison circuit 21 is electrically connected with the output end of the reference current generation circuit 10 and the output end of the current conversion circuit 43 respectively, and is used for generating and outputting corresponding charging current according to the output current of the reference current generation circuit 10 and the output current of the current conversion circuit 43;
and the input end of the charging circuit 22 is electrically connected with the output end of the current comparison circuit 21, and the output end of the charging circuit 22 is electrically connected with the input end of the oscillating circuit 30, and is used for charging the capacitor according to the charging current and outputting a corresponding control signal so as to control the frequency of an output signal of the oscillating circuit 30.
In the embodiment, the current comparing circuit 21 compares the reference current Iref with the output current Iout of the frequency-current converting circuit 40, the second N-type MOS transistor MN2 receives the comparison reference current Iref, the first P-type MOS transistor MP1 receives the output current Iout of the frequency-current converting circuit 40, and the difference current flows into the charging circuit 22 and is converted into the voltage VCTRL, which is used as the control signal of the oscillating circuit 30 to control the frequency of the output signal Vout of the oscillating circuit 30.
Referring to fig. 4 and 5, in an embodiment, the reference current generating circuit 10 includes a current constant source IREF and a first N-type MOS transistor MN1, wherein one end of the current constant source IREF is electrically connected to the drain of the first N-type MOS transistor MN1 and the gate of the first N-type MOS transistor MN1, respectively, and is electrically connected to the input end of the control circuit, the other end of the current constant source IREF is electrically connected to a power supply voltage, and the source of the first N-type MOS transistor is grounded.
In the embodiment, the current value of the current constant current source IREF is the reference current IREF, the current value flowing through the first N-type MOS transistor MN1 is the reference current IREF, the current flowing through the second N-type MOS transistor NM2 is the mirror image of the first N-type MOS transistor MN1, and the reference current IREF is input to the control circuit 20 through the second N-type MOS transistor NM 2.
Referring to fig. 6, in an embodiment, the oscillation circuit 30 includes a plurality of inverter units connected in series between the frequency-current conversion circuit 40 and the control circuit 20.
The oscillating circuit 30 is composed of a plurality of inverter units connected in series to form a closed-loop negative feedback loop. The output end of each phase inverter unit is connected with the input end of the corresponding next-stage phase inverter, and the output end of the last-stage phase inverter is connected with the input end of the first-stage phase inverter. The frequency of the output signal Vout of the oscillation circuit 30 is controlled by a control signal VCTRL output from the control circuit 20, and the control signal VCTRL is connected to each inverter unit.
Referring to fig. 6, in one embodiment, the number of the inverter units is an odd number.
In the present embodiment, the oscillation circuit 30 changes the input after the delay, the original high level changes to the low level, the original low level changes to the high level, and the oscillation is formed, and the number of the inverter units can be an odd number such as 3, 5, 7, etc. to meet the requirement.
The present invention proposes a supply voltage and temperature insensitive clock generating device comprising a supply voltage and temperature insensitive clock generating circuit as described above. Since the clock generation device insensitive to the power supply voltage and the temperature of the present invention adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (5)
1. A supply voltage and temperature insensitive clock generation circuit comprising: a reference current generating circuit for generating a reference current;
an oscillation circuit;
the input end of the frequency-current conversion circuit is electrically connected with the output end of the oscillating circuit, and the frequency-current conversion circuit is used for receiving the output signal of the oscillating circuit and converting the frequency of the output signal of the oscillating circuit into a corresponding output current signal;
the input end of the control circuit is respectively and electrically connected with the output end of the reference current generating circuit and the output end of the frequency-current converting circuit, the output end of the control circuit is electrically connected with the input end of the oscillating circuit, and the control circuit is used for generating corresponding control signals according to the output current of the reference current generating circuit and the output current of the frequency-current converting circuit and outputting the control signals to the oscillating circuit so as to adjust the frequency of the output signals of the oscillating circuit;
wherein the frequency-to-current conversion circuit comprises:
a two-phase non-overlapping clock generation circuit for generating a first phase clock signal and a second phase clock signal which are complementarily interleaved;
a switch circuit, a controlled terminal of the switch circuit being connected to the output terminals of the two-phase non-overlapping clock generating circuit, the switch circuit including a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor, the first capacitor and the second capacitor having the same capacitance value, the first switch, the second switch, the third switch and the fourth switch having the same size, a first terminal of the first switch being electrically connected to a first terminal of the second switch and an input terminal of the current converting circuit, respectively, a second terminal of the first switch being electrically connected to a first terminal of the third switch, a second terminal of the second switch being electrically connected to a first terminal of the fourth switch, a second terminal of the third switch and a second terminal of the fourth switch being grounded, the first capacitor being connected in parallel between two terminals of the third switch, the second capacitor being connected in parallel between two terminals of the fourth switch, the two-phase non-overlapping clock generation circuit is respectively electrically connected with the controlled ends of the first switch, the second switch, the third switch and the fourth switch, the first phase clock signal is used for controlling the first switch and the fourth switch, and the second phase clock signal is used for controlling the second switch and the third switch;
the input end of the current conversion circuit is electrically connected with the output end of the switch circuit, and the output end of the current conversion circuit is electrically connected with the input end of the control circuit and used for generating corresponding output current according to the on/off frequency of the switch circuit;
the control circuit includes:
the input end of the current comparison circuit is respectively and electrically connected with the output end of the reference current generation circuit and the output end of the current conversion circuit, and the current comparison circuit is used for generating and outputting corresponding charging current according to the output current of the reference current generation circuit and the output current of the current conversion circuit;
the input end of the charging circuit is electrically connected with the output end of the current comparison circuit, the output end of the charging circuit is electrically connected with the input end of the oscillating circuit, the charging circuit is used for charging according to the charging current and outputting a corresponding control signal so as to control the frequency of the output signal of the oscillating circuit, the control signal output by the charging circuit is a voltage signal, and the frequency of the output signal of the oscillating circuit is controlled to be higher when the voltage output by the charging circuit is higher;
when the current output by the current conversion circuit is the same as the reference current, the oscillation circuit outputs a clock signal with a stable frequency and a duty ratio of 50%.
2. The supply voltage and temperature insensitive clock generation circuit of claim 1 wherein the reference current generation circuit includes a current constant source and a first N-type MOS transistor, wherein one end of the current constant source is electrically connected to the drain of the first N-type MOS transistor, the gate of the first N-type MOS transistor and the input of the control circuit, respectively, the other end of the current constant source is electrically connected to the supply voltage, and the source of the first N-type MOS transistor is grounded.
3. The supply voltage and temperature insensitive clock generation circuit of claim 1 wherein the oscillation circuit includes a plurality of inverter cells connected in series between the frequency-to-current conversion circuit and the control circuit.
4. A supply voltage and temperature insensitive clock generation circuit as claimed in claim 3 wherein the number of inverter cells is an odd number.
5. A supply voltage and temperature insensitive clock generating device comprising a supply voltage and temperature insensitive clock generating circuit as claimed in any one of claims 1 to 4.
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| JP4952936B2 (en) * | 2007-10-23 | 2012-06-13 | サンケン電気株式会社 | Switching type DCDC converter |
| CN106384144B (en) * | 2016-10-11 | 2019-01-22 | 卓捷创芯科技（深圳）有限公司 | A kind of half-duplex RF ID oscillating maintaining circuit generating pulse by comparator |
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| CN102783029A (en) * | 2009-12-30 | 2012-11-14 | 桑迪士克科技股份有限公司 | Temperature-stable oscillator circuit having frequency-to-current feedback |
| CN103066952A (en) * | 2012-12-28 | 2013-04-24 | 杭州士兰微电子股份有限公司 | Built-in oscillation circuit |
| CN103166604A (en) * | 2013-01-29 | 2013-06-19 | 嘉兴联星微电子有限公司 | On-chip clock generating circuit with lower power consumption |
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| CN114553193A (en) | 2022-05-27 |
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