JP2013526745A - Integration circuit combining an inverting integrator and a non-inverting integrator - Google Patents

Abstract

  An integrating circuit including a capacitor, a charging / discharging circuit coupled to the capacitor so as to charge and discharge the capacitor, an inverting integrating circuit coupled to the charging / discharging circuit, and a non-inverting integrating circuit coupled to the charging / discharging circuit; Disclosed. At least a part of the integration time interval of the inverting integration circuit does not overlap with the integration time interval of the non-inverting integration circuit.

Description

  The present invention relates to an integration circuit, and more particularly to an integration circuit that is resistant to noise.

  A display device such as a liquid crystal display device and an organic light emitting display device, a portable transmission device, and other information processing devices perform functions using various input devices. Recently, a touch screen device is widely used as such an input device in a mobile phone, a smartphone, a palm size PC (Palm-Size PC), an ATM (Automated Teller Machine) device, and the like.

  The touch screen touches the screen with a finger or a touch pen (touch pen, styles) to write a character or draw a picture and execute an icon to execute a desired command. The touch screen device may sense whether or not a screen such as a finger or a touch pen can be touched and contact position information.

  Such touch screens can be roughly classified into a resistive type and a capacitive type according to a method of sensing touch.

  A resistive film type touch screen has a structure in which a resistance component substance is coated on glass or a transparent plastic and is covered with a polyester film. The resistive film type touch screen detects a touch point by detecting a change in resistance value that changes when the screen is touched. The resistive film type touch screen has a disadvantage that it cannot be sensed if the pressure is weak.

  On the other hand, a capacitive touch screen has two electrodes that change when an electrode such as a finger touches the screen after electrodes are formed on both or one side of glass or transparent plastic and a voltage is applied between the two electrodes. The touch point is detected by analyzing the amount of capacitance change between them.

  In order to sense a touch point on a capacitive touch screen, a circuit for measuring a capacitance formed between one or two electrodes is required. Such capacitance measuring circuits have been mainly used to measure the capacitance of various circuits or devices, but recently various portable devices provide touch input interfaces to detect user contact and proximity. The applicability of the capacitance measurement circuit to be obtained is being expanded.

  Conventionally, a capacitance measuring circuit used for a touch screen such as a mobile phone has a problem of causing malfunction due to various noises caused by changes in the surrounding environment.

  Through the present invention, an integrator circuit resistant to noise is provided. In addition, by applying the integration circuit according to the present invention to a sensor block that senses an input of a touch screen, an input sensing error due to noise generated from the touch input is reduced.

  The scope of the present invention is not limited by the problems described above.

  An integrating circuit according to one embodiment of the present invention for solving the above-described problems is provided. The integrating circuit includes a first operational amplifier OA1, a second operational amplifier OA2, and a capacitor Cij, and the inverting input terminals of the first operational amplifier and the second operational amplifier are respectively connected via a first switch S1 and a second switch S2. The second terminal of the capacitor is connected to the first potential and the second potential through the third switch S1 ′ and the fourth switch S2 ′. The inverting input terminal and the output terminal of the first operational amplifier are connected to each other through a first feedback capacitor Cfb1, and the inverting input terminal and the output terminal of the second operational amplifier are connected to each other. 2 are connected to each other via a feedback capacitor Cfb2, and the non-inverting input of the first operational amplifier and the second operational amplifier Terminals adapted to be connected to a third potential, respectively.

  At this time, the third potential may be the same as the second potential.

  At this time, switches S3 and S3 'may be connected in parallel between the inverting input terminal and the output terminal of the first operational amplifier and between the inverting input terminal and the output terminal of the second operational amplifier, respectively.

  At this time, the first switch and the third switch may be driven by a first clock, and the second switch and the fourth switch may be driven by a second clock.

  At this time, the on period of the first clock and the second clock may appear alternately on the time axis. At this time, a part of the on period of the first clock and a part of the on period of the second clock may exist at the same time. Alternatively, when one of the first clock and the second clock is on, the other one may be off.

  According to another aspect of the present invention, there is provided a circuit adapted to sense an input of a capacitive touch screen in which an operation pattern and a sensing pattern are formed. The circuit includes a first operational amplifier and a second operational amplifier, and the sensing pattern is connected to an inverting input terminal of the first operational amplifier and an inverting input terminal of the second operational amplifier through the first switch and the second switch. The operation pattern is connected to the first potential and the second potential via the third switch and the fourth switch, and the inverting input terminal of the first operational amplifier The output terminal is connected to each other through a first feedback capacitor, and the inverting input terminal and the output terminal of the second operational amplifier are connected to each other through a second feedback capacitor, The non-inverting input terminals of the first operational amplifier and the second operational amplifier are each connected to a third potential.

  At this time, the first switch and the third switch may be driven by a first clock, and the second switch and the fourth switch may be driven by a second clock.

  A switched capacitor integrator circuit according to yet another aspect of the present invention is provided. The circuit includes an inverting switched capacitor integrator circuit and a non-inverted switched capacitor integrator circuit connected to the inverting switched capacitor integrator circuit, and the non-inverted switched capacitor integrator circuit. The sampling capacitor of the switched capacitor integrating circuit and the sampling capacitor of the non-inverting switched capacitor integrating circuit are the same capacitor.

  At this time, the inverting switched capacitor integrating circuit integrates the voltage charged in the sampling capacitor and outputs a negative voltage, and the non-inverting switched capacitor integrating circuit is charged in the sampling capacitor. The voltage may be integrated to output a positive value.

  At this time, at least a part of the integration time interval of the inverting switched capacitor integrating circuit may not overlap the integration time interval of the non-inverting switched capacitor integrating circuit.

  At this time, the sampling capacitor may be formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.

  At this time, among the two terminals of the sampling capacitor, a noise source (noise) that flows in a wired or wireless manner is connected to a terminal of the amplifier of the inverting switched capacitor integrator and an amplifier of the non-inverting switched capacitor integrator. source) may be linked.

  An integration circuit according to yet another aspect of the present invention is provided. The circuit includes a capacitor, a charge / discharge circuit coupled to the capacitor so as to charge and discharge the capacitor, an inversion integration circuit coupled to the charge / discharge circuit, and a non-inversion integration circuit coupled to the charge / discharge circuit. .

  At this time, the inverting integration circuit integrates the voltage charged in the capacitor and outputs a negative voltage, and the non-inverting integration circuit integrates the voltage charged in the capacitor to obtain a positive voltage. A value may be output.

  In this case, the capacitor may be formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.

  At this time, a noise source that is introduced in a wired or wireless manner may be connected to one terminal connected to the inverting integration circuit and the non-inverting integration circuit among both terminals of the capacitor.

  At this time, at least a part of the integration time interval of the inverting integration circuit may not overlap with the integration time interval of the non-inverting integration circuit.

  In this case, the capacitor may be formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.

  At this time, one terminal connected to the first operational amplifier and the second operational amplifier among both terminals of the capacitor may correspond to the sensing pattern.

  At this time, the sensing pattern may be arranged outside the touch screen from the operation pattern.

  At this time, one of the terminals of the capacitor connected to the first operational amplifier and the second operational amplifier may be connected to a noise source that is introduced in a wired or wireless manner.

  An integration circuit according to yet another aspect of the present invention is provided. The integration circuit includes a first operational amplifier, a second operational amplifier, and a capacitor. At this time, the inverting input terminals of the first operational amplifier and the second operational amplifier are connected to the first terminal of the capacitor, and the inverting input terminal and the output terminal of the first operational amplifier are connected in series. The inverting input terminal and the output terminal of the second operational amplifier are connected to each other via a second switch and a second feedback capacitor connected in series. The second terminals of the capacitors are connected to the first potential and the second potential through a third switch and a fourth switch, and the first operational amplifier and the second potential are connected to each other. Each non-inverting input terminal of the second operational amplifier is connected to a third potential.

  At this time, the third potential may be the same as the second potential.

  At this time, switches S3 and S3 'may be connected in parallel between the inverting input terminal and the output terminal of the first operational amplifier and between the inverting input terminal and the output terminal of the second operational amplifier, respectively.

  As described above, the means for solving the problems are intended to assist the understanding of the present invention with the contents described in parentheses, and are not intended to limit the scope of the present invention.

  The present invention can provide an integration circuit that is resistant to noise. In addition, by applying this integration circuit to a sensing unit that senses input on the touch screen, input sensing errors due to noise generated from touch input can be reduced.

  The scope of the present invention is not limited by the effects described above.

It is a figure which shows the example of the structure of the touch screen apparatus with which one Example of this invention can be applied. It is a figure which shows the example of the structure of the touch screen apparatus with which one Example of this invention can be applied. It is a figure which shows the example of the structure of the touch screen apparatus with which one Example of this invention can be applied. It is a figure which shows the example of the structure of the touch screen apparatus with which one Example of this invention can be applied. FIG. 6 is a schematic diagram illustrating a driving circuit that can be used to drive a touch screen according to an exemplary embodiment of the present invention. It is a figure which shows the structure of the integrator by one Example of this invention. It is a timing diagram which shows the state by time in each node of the integrator by one Example of this invention. It is a figure which shows the structure of the integrator by one Example of this invention. It is a figure which shows the structure of the integrator by one Example of this invention. It is a figure which shows the structure of the integrator by one Example of this invention. It is a figure explaining the principle by which the noise which may be flowed into the integrator by one Example of this invention is removed. It is a figure explaining the principle by which the noise which may be flowed into the integrator by one Example of this invention is removed. It is a figure explaining the principle by which the noise which may be flowed into the integrator by one Example of this invention is removed. It is a figure explaining the principle by which the noise which may be flowed into the integrator by one Example of this invention is removed. It is a figure which shows the frequency response with respect to the noise of the integrator by one Example of this invention. It is a figure which shows an example of the inverting integration circuit which can be used for one Example of this invention. It is a figure which shows an example of the non-inverting integration circuit which can be used for one Example of this invention. It is a figure explaining the integration circuit by the other Example of this invention. It is a figure explaining the integration circuit by the other Example of this invention. It is a figure which shows the result of having simulated the operation | movement of the integrator by one Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the embodiments. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. The terminology used below is merely for the purpose of reference to particular embodiments and is not intended to limit the invention. Also, the singular form used below includes the plural form unless the context clearly indicates the contrary.

  FIG. 1 is a diagram illustrating a touch screen device to which an embodiment of the present invention can be applied.

  As shown in FIG. 1, the touch screen device may include a touch panel 100, a capacitance measurement circuit 200, and a touch determination unit 300.

  The touch panel 100 may include a plurality of operation signal lines (X1, X2, X3,..., Xn) and a plurality of sensing signal lines (Y1, Y2, Y3,. In FIG. 1, the operation signal lines and the sensing signal lines are shown as lines for convenience, but may actually be implemented as electrode patterns. In the present specification, the sense signal line may be mixed with terms such as a sense line, a sense line, and a sense electrode, and the operation signal line may be mixed with terms such as a line, an operation line, and a work electrode. In FIG. 1, a large number of operation signal lines and a large number of sensing signal lines are shown to be insulated from each other and intersect, but the present invention is not limited to this, and the operation signal lines and the sensing signal lines do not intersect. Also good.

  The sensing node 110 indicating the touch point is defined by one sensing signal line and one operation signal line, and each sensing node 110 may include a node capacitor 112. The node capacitor 112 may be formed by an operation signal line and a sense signal line that are insulated and separated from each other. In FIG. 1, the capacitance of the node capacitor 112 formed by the i-th operation signal line and the j-th sensing signal line is indicated by Cij.

  The capacitance measuring circuit 200 is electrically connected to a number of operation signal lines (X1, X2, X3,..., Xn) and a number of sensing signal lines (Y1, Y2, Y3,..., Yn). The capacitance Cij is measured.

  The touch determination unit 300 detects the touch point input by the user by analyzing the change amount of the capacitance based on the capacitance of each node capacitor measured by the capacitance measurement circuit 200.

  FIG. 2 is a diagram illustrating an example of the concept of the touch screen device of FIG.

  FIG. 2 is a conceptual structural diagram for explaining the operation of the touch screen panel in which direct touch is performed in addition to the operation circuit and the additional device in the entire touch screen device for determining whether or not an object is touched. . The sensing pattern 100 and the operation pattern 101 may be formed of a conductive material, and the sensing pattern 100 and the operation pattern 101 may be directly connected to the touch screen operation circuit and an additional device by using electrodes to determine whether there is a touch. Also good. Therefore, various touch screen panels can be formed according to the patterns of the sensing pattern 100 and the operation pattern 101. A dielectric 102 may exist between the sensing pattern 100 and the operation pattern 101. Accordingly, the sensing pattern 100 and the operation pattern 101 formed of a conductive material form a capacitor (capacitor) having the dielectric 102 therebetween. A window 103 may be present on the sensing pattern 100 to protect the touch screen panel including the sensing pattern 100, the operation pattern 101 and the dielectric 102. If there is an object to touch on the protection window 103, a change may occur in the capacitance between the sensing pattern 100 and the operation pattern 101 of the touch screen panel.

  FIG. 3 is a diagram illustrating a conceptual structural diagram of the touch screen device of FIG. 2 as a plan view.

  3A shows the sensing pattern 100 and the operation pattern 101 at the same time, FIG. 3B shows the sensing pattern 100, and FIG. 3C shows the operation pattern 101.

  In the touch screen device, a large number of operation patterns 101 having a wide rectangular shape are formed. When a voltage is applied to the operation pattern 101, an electric field is generated between the sensing pattern 100 and the operation pattern 101. The sensing pattern 100 may be a relatively thin pattern compared to the operation pattern 101. Therefore, when a voltage is applied to the operation pattern 101, the sensing pattern 100 has a smaller area than the operation pattern 101, so that the sensing pattern 100 cannot cover the operation pattern 101. The electric field described above comes out in the direction of the sensing pattern 100 from the operation pattern 101, but this electric field flows into the sensing pattern 100 when no touch occurs, but flows into the touched object when the touch occurs. The electric field formed between 100 and the operation pattern 101 changes. This change results in a change in capacitance formed between the sensing pattern 100 and the operation pattern 101, and the presence / absence of touch can be determined by sensing the value of such capacitance with a sensing device.

  The pattern according to FIG. 3 illustrates one of various touch screen electrode patterns to help understand the present invention, and it should be understood that the scope of the present invention is not limited by this illustration. is there.

  FIG. 4 is a diagram showing a vertical structure along the cut line 203 in FIG.

  Referring to FIG. 4, when a voltage is applied to the operation pattern 101, it is determined whether or not there is a touch. A portion where an electric field indicated by a dotted line appears on the protection window 103, that is, the sensing pattern 100 operates. When touch input is performed in a region where the electric field emitted from the pattern 101 cannot be covered, the sensing pattern 100 is changed to the operation pattern 101 by changing the path of the electric field that passes through this region and enters the sensing pattern 100. The amount of charge accumulated in the formed capacitor is reduced, and it is determined that the object is touched.

  So far, one of the principles for detecting whether or not touch input has been performed on the touch screen has been described. In the following, embodiments of the present invention that can be used to measure the change in capacitance described above will be described.

  FIG. 5 is a schematic diagram illustrating a driving circuit that can be used to drive a touch screen according to an embodiment of the present invention.

  As shown in FIG. 5, the drive circuit 10 may include a charge / discharge circuit 11, a sensing unit 12, and a capacitor Cij. Since the sensing unit 12 has a function of performing an integration function, it may be referred to as an “integration unit” in this specification. The charge / discharge circuit 11 is electrically connected to both terminals of the capacitor Cij, and is a circuit for charging the capacitor Cij with the power supply voltage Vcc and discharging it to the ground voltage GND. Hereinafter, the capacitor Cij may be referred to as a sampling capacitor.

  Here, when this driving circuit is used to drive the touch screen, the capacitor Cij of FIG. 5 may correspond to the node capacitor 112 described above. That is, the capacitor Cij is electrically connected to the operation signal line Xi and the sensing signal line Yj, and the charge / discharge circuit 11 can repeat the charging and discharging operations a plurality of times (N times).

  In the drive circuit of FIG. 5, noise can flow in through the sensing signal line Yj, but this noise may be integrated and undesirably affect the output of the sensing unit 12. Hereinafter, the structure of an integration device that is resistant to noise according to an embodiment of the present invention will be described.

  FIG. 6 is a diagram showing the structure of an integrating device according to an embodiment of the present invention.

  Referring to FIG. 6, the integration circuit includes a first operational amplifier OA1, a second operational amplifier OA2, and a capacitor Cij. The inverting input terminals of the first operational amplifier OA1 and the second operational amplifier OA2 are connected to the first terminal Yj of the capacitor Cij through the first switch S1 and the second switch S2, respectively. The second terminal Xi of the capacitor Cij is It is connected to the first potential Vcc and the second potential GND through the third switch S1 ′ and the fourth switch S2 ′. Hereinafter, for convenience of explanation, it is assumed that the second potential GND has a value of 0. The inverting input terminal and the output terminal of the first operational amplifier OA1 are connected to each other via a first feedback capacitor Cfb1, and the inverting input terminal and the output terminal of the second operational amplifier OA2 are connected to each other via a second feedback capacitor Cfb2. The non-inverting input terminals of the first operational amplifier OA1 and the second operational amplifier OA2 may be coupled to the second potential GND, respectively.

  Further, the reset switches S3 and S3 'may connect the non-inverting input terminal and the output terminal of the first operational amplifier OA1 and the second operational amplifier OA2, respectively. When the reset switches S3 and S3 'are turned on, the charges charged in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 are all discharged, and the voltage at both ends thereof can be made zero. Depending on the embodiment, the reset switch S3 and the reset switch S3 'may operate at the same timing.

  The switches S1 and S1 'and the switches S2 and S2' can be switched at timings such as a clock 1CLK1 in FIG. 7A and a clock 2CLK2 in FIG. However, it is not limited to that.

  FIG. 7 is a timing chart showing a state according to time in each node of the integrator shown in FIG.

  7A and 7B show the on / off timings of the switches S1 and S1 ′ and the switches S2 and S2 ′, FIG. 7C shows the potential of the second terminal Xi, FIG. 7D shows the output voltage Vo1 of the first operational amplifier OA1, and FIG. 7E shows the output voltage Vo2 of the second operational amplifier OA2.

  Referring to FIGS. 7A and 7B, the switches S1 and S1 'and the switches S2 and S2' may be alternately turned on for a non-overlapping time. That is, the switches S1 and S2 'can be turned on in the time intervals [t1, t2] and [t1', t2 '], and can be turned off in the time intervals [t2, t1']. In contrast, the switches S1 and S2 'can be turned on in the time intervals [t3, t4] and [t3', t4 '] and can be turned off in the time intervals [t4, t3']. The operating states of the switches S1, S1 'and the switches S2, S2' in the time interval [t1, t1 '] can be repeated continuously. In FIG. 7, the lengths of the time interval [t2, t3] and the time interval [t4, t1 '] are non-zero values, but may be set to be substantially close to 0 depending on the embodiment.

  Hereinafter, immediately before time t is referred to as “t−”, and immediately after time t is referred to as “t +”. For example, the time immediately before time t1 may be referred to as “t1−” and the time immediately after “t1 +”. Hereinafter, in order to explain the operation of the integrator at each time shown in FIG. 7, the operation state diagrams of the integrator shown in FIGS.

  8 shows the state of the integrator at time t1 + in FIG. 7, FIG. 9 shows the state of the integrator at times t2 + and t4 + in FIG. 7, and FIG. 10 shows the state of the integrator at time t3 + in FIG. At this time, it is assumed that Cfb1, Cfb2, and Cij are all discharged at an initial condition at time t1-.

  7 and 8, at time t1 +, the switches S1 and S1 'are in the on state, and the switches S2 and S2' are in the off state. The first terminal Yj of the capacitor Cij is connected to the inverting input terminal of the first operational amplifier OA1. At this time, since the non-inverting input terminal of the first operational amplifier OA1 is connected to the second potential GND, the potential of the first terminal Yj is the same as the second potential. At this time, since the potential of the second terminal Xi of the capacitor Cij becomes the first potential Vcc, the potential difference between both ends of the capacitor Cij has the same value as the first potential Vcc.

  At this time, the current flowing through the capacitor Cij flows through the first feedback capacitor Cfb1, and at this time, the potential (Vo1, 1) of the output terminal o1 of the first operational amplifier OA1 is expressed by the following Expression 1.

(Formula 1)

  At this time, the potential of the first terminal Yj is maintained at the second potential GND, and the potential of the output terminal of the second operational amplifier OA2 is also maintained at the second potential GND.

  Hereinafter, assuming that one integration cycle is completed by N integrations, the k (k = 1, 2, 3,..., N) -th integration is completed after a new integration cycle starts. The potential of the output terminal o1 of one operational amplifier OA1 can be expressed as Vol, k.

  7 and 9, at time t2 +, the switches S1, S1 'and the switches S2, S2' are all in the off state. The potential difference between both ends of the capacitor Cij is maintained at a magnitude like the first potential Vcc. At this time, although the potentials of the first terminal Yj and the second terminal Xi are in a floating state, in FIG. 7C and FIG. 7D, the potential of the first terminal Yj is changed to the second potential GND. It showed in.

  Referring to FIGS. 7 and 10, at time t3 +, the switches S1 and S1 'are in the off state, and the switches S2 and S2' are in the on state. The potential of the second terminal Xi becomes the second potential GND, and the potential of the first terminal Yj instantaneously becomes -Vcc. Since the first terminal Yj is connected to the inverting input terminal of the first operational amplifier, it immediately rises to the second potential GND. In order to charge the second feedback capacitor Cfb2 by supplying a current from the output terminal of the second operational amplifier in a time interval in which the potential of the first terminal Yj changes instantaneously, the potential (at the output terminal o2 of the second operational amplifier ( Vo2,1) is as shown in Equation 2.

(Formula 2)

  Further referring to FIGS. 7 and 9, at time t4 +, the switches S1, S1 'and the switches S2, S2' are all in the off state. The potential difference between both ends of the capacitor Cij is zero. At this time, the potentials of the first terminal Yj and the second terminal Xi are in a floating state. For convenience, the potential of the first terminal Yj is indicated by the second potential GND in FIGS. 7C and 7D. .

  If the time interval [t1, t1 '] in which the operation described with reference to FIGS. 8 to 10 occurs is defined as one cycle, such a cycle can be generated N times. At this time, since the charges charged in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 are not discharged, the potential Vo1 of the output terminal o1 of the first operational amplifier and the potential Vo2 of the output terminal o2 of the second operational amplifier are as shown in FIG. As shown in (e) of FIG. 7 and (f) of FIG. 7, it increases or decreases stepwise. When the progress of N cycles is completed, ΔV that is a value obtained by subtracting the potentials Vo1 and N from the potentials Vo2 and N can be given by Equation 3.

(Formula 3)

  However, at this time, it is assumed that the values of the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 are the same value Cfb.

  According to Equation 3, since the value Cfb of the first feedback capacitor and the second feedback capacitor is a constant value that can be understood, ΔV is proportional to the value of the capacitor Cij.

  When the integrating device according to FIG. 6 is applied to the touch screen driving circuit, the value of the capacitor Cij changes depending on the touch input to the touch screen. Therefore, the value of the capacitor Cij can be measured by measuring ΔV. Can know.

  Once N integration cycles have been completed and ΔV is measured, the reset switches S3 and S3 ′ are turned on as shown in FIG. 11 to discharge all the charges of the first feedback capacitor and the second feedback capacitor. obtain. As described above, if the time required to charge / discharge the capacitor Cij N times is defined as one integration cycle, after the reset switches S3 and S3 ′ are turned on, another new integration cycle is started. obtain.

  The operation principle of the integrator according to the embodiment of the present invention has been described above with reference to FIGS. However, as described with reference to FIG. 5, there is a possibility that noise may flow through the first terminal Yj of the integrator.

  Typically, this integration device is used as the touch screen driving device described above. That is, the sensing pattern 100 described above hits the first terminal Yj of the capacitor Cij. At this time, when an object such as a finger is brought close to the sensing pattern 100 for touch input, noise can flow from there to the first terminal Yj. There is sex.

  According to the embodiment of the present invention shown in FIG. 6, the noise that flows in can be efficiently removed as described above. Hereinafter, the principle will be described with reference to FIGS.

  FIG. 11 to FIG. 14 are diagrams for explaining the principle of removing noise that may flow into the integrator according to an embodiment of the present invention.

  Basically, noise introduced through the first terminal Yj can be additionally integrated into the output voltages of the first operational amplifier OA1 and the second operational amplifier OA2. However, the first operational amplifier OA1 integrates noise only when the switches S1 and S1 'are on, and the second operational amplifier OA2 integrates noise only when the switches S2 and S2' are on.

  FIG. 11 is a diagram illustrating a case where noise having only a direct current component is introduced.

  Referring to FIG. 11, noise flowing in the ON period including the time point (n1, k = 1, 2, 3,..., N) in the clock 1CLK1 is additionally integrated into the output potential Vo1 of the first operational amplifier OA1. The At this time, if the magnitude of noise in which the output potential Vo1 is additionally integrated in each ON period is defined as A1, nk (k = 1, 2, 3,... N), the first operational amplifier during one integration cycle. The noise magnitude A1 additionally integrated into the output potential Vo1 of OA1 can be given by Equation 4.

(Formula 4)

  Similarly, noise flowing in the ON period including the time point (n2, k = 1, 2, 3,..., N) in the clock 2CLK2 is additionally integrated into the output potential Vo2 of the second operational amplifier OA2. At this time, if the magnitude of noise additionally integrated into the output potential Vo2 in each ON section is referred to as A2, nk (k = 1, 2, 3,..., N), the second calculation is performed during one integration cycle. The noise magnitude A2 additionally integrated into the output potential Vo2 of the amplifier OA2 can be given by Equation 5.

(Formula 5)

  Considering the above-mentioned noise integration effect together, Equation 3 can be changed to Equation 6. That is, after N cycles are completed, ΔV, which is a value obtained by subtracting the potentials Vo1 and N from the potentials Vo2 and N, can be given by Equation 6.

(Formula 6)

At this time, when the noise has only a DC component as shown in FIG. 11, Equation 6 can be expressed as Equation 7 because A _{2 nk} = A _{1 nk} is substantially satisfied.
(Formula 7)

  Therefore, the noise of the DC component can be removed by using the integration circuit according to an embodiment of the present invention.

  Next, FIG. 12 is a diagram illustrating a case where low frequency noise is introduced.

  The operation period and the operation frequency of the clock 1CLK1 and the clock 2CLK2 can be referred to as T and f (= 1 / T), respectively. In FIG. 12, the period of the noise shows a case where it is very slow compared to the operating frequency f. At this time, the noise is less than the number of integrations N = 14 of the integration circuit per integration cycle. In this case, only one cycle is advanced per integration cycle.

）。従って、クロック１及びクロック２の動作周波数より非常に小さい周波数を有する雑音は、一般にその影響がΔＶに殆ど反映されないということが分かる。 Also in the case of FIG. 12, ΔV, which is a value obtained by subtracting the potentials Vo1 and N from the potentials Vo2 and N, can be given by Equation 6. In the case where the noise is not a DC component as shown in FIG. 12, A _{2, nk} = A _{1, nk} is not satisfied in Equation 6, but the noise additionally integrated into the output potential Vo1 of the first operational amplifier OA1 over one integration cycle. It can be seen that the magnitude A1 can be almost canceled with the noise magnitude A2 additionally integrated into the output potential Vo2 of the second operational amplifier OA2.

). Therefore, it can be seen that noise having a frequency much lower than the operating frequency of the clock 1 and the clock 2 generally has almost no influence on ΔV.

  FIG. 13 is a diagram for explaining a case where noise having the same frequency as the operating frequency of clocks 1CLK1 and 2CLK2 is introduced. That is, the integration number N = 14 of the integration circuit per integration cycle, and the noise is a case where 14 cycles are repeated per integration cycle.

Also in the case of FIG. 13, ΔV, which is a value obtained by subtracting the potentials Vo1 and N from the potentials Vo2 and N, can be given by Equation 6. Incidentally, the noise magnitude A2 _{, nk} additionally integrated into the output potential Vo2 of the second operational amplifier OA1 in the section including the time points n2, k in the clock 2CLK2 is the section including the time points n1, k in the clock 1CLK1. It can be easily understood that the magnitude is the same as the magnitude of the noise A _{1, nk} additionally integrated into the output potential Vo1 of the first operational amplifier OA1, but has the opposite sign. That is, it can be seen that A _{2, nk} = −A _{1, nk} holds. Accordingly, in the case of FIG. 13, it can be seen that Equation 6 can be changed to Equation 8.

(Formula 8)

  That is, when noise as shown in FIG. 13 is introduced, the noise is not removed.

  Next, FIG. 14 is a diagram showing the case where the number of integrations N = 14 of the integration circuit per integration cycle and the noise is repeated 15 cycles per integration cycle.

）。一般に、本発明の一実施例による積分回路を使用すると、そして一つの積分サイクル当たり積分する回数がＮとすると、一つの積分サイクル当たりｋ（但し、ｋはＮを除いた負ではない整数）回反復される正弦波雑音が一端子Ｙｊを介して流入されるとその雑音は実質的に除去されるということが分かる。 Even in the case of FIG. 14, ΔV, which is a value obtained by subtracting the potentials Vo1 and N from the potentials Vo2 and N, can be given by Equation 6. In the case as shown in FIG. 14, A _{2, nk} = −A _{1, nk} is not satisfied in Equation 6, but the noise magnitude A1 additionally integrated into the output potential Vo1 of the first operational amplifier OA1 over one integration cycle is It can be seen that the noise magnitude A2 additionally integrated into the output potential Vo2 of the second operational amplifier OA2 can be almost canceled (

). In general, when an integration circuit according to an embodiment of the present invention is used and the number of integrations per integration cycle is N, k is a non-negative integer excluding N times per integration cycle. It can be seen that when repeated sinusoidal noise is introduced through one terminal Yj, the noise is substantially eliminated.

  FIG. 15 shows that in the circuit region P2 configured as shown in FIG. 6, the input portion is the first terminal Yj, and the output is the potential Vo1 of the output terminal of the first operational amplifier OA1 from the potential Vo2 of the output terminal of the second operational amplifier OA2. It is a figure which shows the frequency response at the time of defining to the subtracted value. If FIG. 11 to FIG. 14 are diagrams illustrating noise removal characteristics according to an embodiment of the present invention in the time domain, FIG. 15 is a diagram illustrating such characteristics in the frequency domain.

  FIG. 15 is a diagram illustrating a case where the number of integrations N = 10 per integration cycle. Referring to FIG. 15, it can be seen that there are ten frequencies having a null magnitude response, including DC, before the peak frequency (50,000 Hz) of the magnitude response curve according to frequency.

  As can be seen from FIG. 15, when the drive frequency f is set sufficiently high (f = 50,000 Hz in the case of FIG. 15), the large noise passing region in the circuit region P2 shown in FIG. Since it is far away from the frequency of noise, it is advantageous to remove such noise. Generally, there is HUM noise of 60 Hz of 100 V or higher and its harmonic component as main noise.

As described above, if A _{2, nk} = A _{1, nk} is satisfied in Expression 6, the value of the capacitor Cij can be calculated from Expression 6 as in Expression 9.
(Formula 9)

  When the value of the capacitor Cij calculated by Equation 9 is changed, it can be determined whether or not touch input has been performed.

  Hereinafter, it will be described that the circuit configuration of FIG. 6 according to an embodiment of the present invention is a combination of an inverting integration circuit and a non-inverting integration circuit.

  FIG. 16 is a diagram showing an example of an inverting integration circuit that can be used in one embodiment of the present invention. FIG. 16A is the same as FIG. 6 except that the second operational amplifier OA2 is removed. In FIG. 6, if the switch S2 is connected to the inverting input terminal of the second operational amplifier OA2 and consequently connected to the second potential GND, the switch S2 is directly connected to the second potential GND in FIG. From the point of being connected, it can be seen that FIG. 6 includes substantially the same inverting integration circuit as FIG.

  16B, 16C, and 16D are time t1 +, t2 +, and t4 + when the inverting integration circuit of FIG. 16A has switch timings of the clock 1CLK1 and the clock 2CLK2 of FIG. , T3 + shows the operating state. When comparing each of FIGS. 16B, 16C, and 16D with FIGS. 8 to 10, it can be confirmed that FIG. 6 includes an inversion integration circuit substantially the same as FIG.

  The circuit according to FIG. 16 can be referred to as an inverted switched capacitor integrator circuit.

  FIG. 17 is a diagram showing an example of a non-inverting integration circuit that can be used in one embodiment of the present invention. FIG. 17A is the same as FIG. 6 except that the first operational amplifier OA1 is removed. In FIG. 6, if the switch S1 is connected to the inverting input terminal of the first operational amplifier OA1 and consequently connected to the second potential GND, the switch S1 is directly connected to the second potential GND in FIG. From the point, it can be seen that FIG. 6 includes substantially the same non-inverting integration circuit as FIG.

  FIGS. 17B, 17C, and 17D show the time t1 +, t2 + and t2 + when the non-inverting integration circuit according to FIG. The operation states at t4 + and t3 + are respectively shown. When comparing each of FIGS. 17B, 17C, and 17D with FIGS. 8 to 10, it can be confirmed that FIG. 6 includes the non-inverting integration circuit substantially the same as FIG.

  The circuit according to FIG. 17 can be referred to as a non-inverted switched capacitor integrator circuit.

  6, 16, and 17, the integrating circuit according to an embodiment of the present invention includes a non-inverting integrating circuit and an inverting integrating circuit that include a capacitor Cij and a charging / discharging circuit for charging / discharging the capacitor Cij. You can see that they are shared and combined.

  In FIG. 6, the charge / discharge circuit may correspond to the circuit region P1, and in FIGS. 16 and 17, the charge / discharge circuit may correspond to the circuit region P3 and the circuit region P4, respectively.

  FIG. 18 is a diagram illustrating an integration circuit according to another embodiment of the present invention.

  FIG. 18A shows the integration circuit shown in FIG. 16 as a module for each circuit area. The charging / discharging circuit 1 11-1 corresponds to the circuit region P3 in FIG. 16, and the integrating unit 1 12-1 corresponds to the coupling structure of the first operational amplifier OA1, the first feedback capacitor Cfb1, and the third switch S3 in FIG. .

  FIG. 18B shows the integration circuit shown in FIG. 17 as a module for each circuit area. The charge / discharge circuit 2 11-2 corresponds to the circuit region P4 of FIG. 17, and the integration unit 2 12-2 corresponds to the coupling structure of the second operational amplifier OA2, the second feedback capacitor Cfb2, and the third switch S3 ′ of FIG. To do.

  FIG. 18C is a combination of FIG. 18A and FIG. 18B. The charge / discharge circuit 11 corresponds to the circuit region P1 of FIG. 6 corresponds to the coupling structure of the first operational amplifier OA1, the first feedback capacitor Cfb1, and the third switch S3, and the integrating unit 212-2 includes the second operational amplifier OA2, the second feedback capacitor Cfb2, and the third switch of FIG. This corresponds to the bond structure of S3 ′.

  FIG. 19 is a diagram illustrating an integration circuit according to another embodiment of the present invention.

  FIG. 19 shows a circuit according to FIG. 18C implemented in a manner different from that shown in FIG. However, it can be easily understood that when the switches S1, S1 ′ and S2, S2 ′ of FIG. 19 are driven by the clocks 1CLK1 and 2CLK2 of FIG. 8 or 11, the same operation as that of FIG. 6 is performed. .

  6 and 19, the switch S1 is arranged so that the first operational amplifier OA1 is separated from the capacitor Cij when the switch S2 'is in the ON state. Conversely, the switch S2 is arranged so that the second operational amplifier OA2 is separated from the capacitor Cij when the switch S1 'is in the ON state.

  FIGS. 16 and 17 are diagrams illustrating an example of the inverting amplifier and the non-inverting amplifier. The inverting amplifier and the non-inverting amplifier which are not disclosed in this specification but have different configurations are combined to form the configuration of FIG. It can be seen that an integration circuit having this can be made. Accordingly, the scope of the invention is not limited by the specific circuitry disclosed in this specification.

  20 is output as a result of a simulation in which the clock 1CLK1 and the clock 2CLK2 as shown in FIG. 11 are applied to the circuit having the configuration of FIG. 6, for example, and noise is applied to the first terminal Yj. It is a figure which shows the value of ΔV. In such a noise environment, the potentials Vo1 and N of the output terminal o1 of the first operational amplifier are given as in Expression 10, and the potentials Vo2 and N of the output terminal o2 of the second operational amplifier are given as in Expression 11. obtain. At this time, the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 are set to have the same value Cfb.

（式１１）

(Formula 10)

(Formula 11)

  20 (a) shows the potential Vo1 of the output terminal o1 of the first operational amplifier by time, and FIG. 20 (b) shows the potential Vo2 of the output terminal o2 of the second operational amplifier by time. In FIG. 20, (c) shows a value obtained by subtracting the potential Vo1 from the potential Vo2.

  In FIG. 20, the inflowing noise is a noise close to a sine wave repeated about 5 to 6 times during one integration cycle, and the number N of integrations during one integration cycle is much more than 5-6. Is set to have a large value. It can be confirmed that the noise-removed waveform is obtained by the structure according to the present invention as shown in FIG.

  If only one integrator is used without using the circuit structure according to the present invention in which two integrators are combined, only the output voltage according to Equation 10 or Equation 11 is obtained. In this case, for example, when the output voltage of Expression 10 is obtained, the value of the capacitor Cij is given by Expression 12.

(Formula 12)

  At this time, the value of the capacitor Cij cannot be measured accurately due to an error value due to noise.

  It can be seen that the circuit structure according to the present invention can be applied not only to the touch screen but also to other application fields to which the idea of the present invention can be applied. Therefore, it can be seen that the application field of the present invention is not limited to the touch screen driving circuit.

  In the present invention, an operational amplifier is an example of a differential amplifier. As long as the idea of the present invention is not violated, the operational amplifier of the present invention can be replaced by a differential amplifier.

  Since the capacitance measuring circuit according to the embodiment of the present invention uses a switched capacitor including a switch, a feedback capacitor (integrating capacitor), and an operational amplifier, the FIR (Finite Impulse Response) filter is basically used. It has the following characteristics.

  6, 8, 9, 10, 16, 17, and 19 of the drawings attached to the present invention, the non-inverting terminal of each operational amplifier is connected to the operation signal line Xi through the switch S 2 ′. Although it is connected to the same potential as the connected ground voltage GND, the effect of the present invention is different even when the non-inverting terminal of each operational amplifier is connected to another voltage different from the ground voltage GND. You can see that

  Although the preferred embodiments of the present invention have been described above, it is considered that those belonging to the technical field of the present invention can easily carry out various changes and modifications without departing from the essential characteristics of the present invention.

  Accordingly, the disclosed embodiments are to be considered from an illustrative rather than a limited viewpoint, and the true scope of the present invention is indicated by the following claims rather than the foregoing description and is equivalent thereto. All differences that fall within the scope are to be construed as included in the present invention.

Claims (25)

A first operational amplifier, a second operational amplifier, and a capacitor;
The inverting input terminals of the first operational amplifier and the second operational amplifier are connected to the first terminal of the capacitor via the first switch and the second switch, respectively.
The second terminal of the capacitor is connected to the first potential and the second potential through a third switch and a fourth switch, respectively.
The inverting input terminal and the output terminal of the first operational amplifier are connected to each other via a first feedback capacitor, and the inverting input terminal and the output terminal of the second operational amplifier are connected to each other via a second feedback capacitor. Are connected to each other,
The non-inverting input terminals of the first operational amplifier and the second operational amplifier are connected to a third potential, respectively.     The first switch and the third switch are driven by a first clock, and the second switch and the fourth switch are driven by a second clock. Integration circuit.     The integration circuit according to claim 2, wherein the ON periods of the first clock and the second clock appear to cross each other on a time axis.     The integration circuit according to claim 1, wherein the capacitor is formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.     The integration circuit according to claim 4, wherein one terminal connected to the first operational amplifier and the second operational amplifier among both terminals of the capacitor corresponds to the sensing pattern.     The integration circuit according to claim 5, wherein the sensing pattern is arranged outside the touch screen from the operation pattern.     2. The integrating circuit according to claim 1, wherein one of the terminals of the capacitor connected to the first operational amplifier and the second operational amplifier is connected to a noise source that is input in a wired or wireless manner. The integration circuit according to claim 1, wherein the third potential is the same as the second potential. A circuit configured to sense an input of a capacitive touch screen in which an operation pattern and a sensing pattern are formed,
A first operational amplifier;
A second operational amplifier;
Including
The sensing pattern is connected to the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier through the first switch and the second switch, respectively.
The operation pattern is connected to the first potential and the second potential through the third switch and the fourth switch, respectively.
The inverting input terminal and the output terminal of the first operational amplifier are connected to each other via a first feedback capacitor, and the inverting input terminal and the output terminal of the second operational amplifier are connected to each other via a second feedback capacitor. Are connected to each other,
The capacitive touch screen input sensing circuit, wherein the non-inverting input terminals of the first operational amplifier and the second operational amplifier are respectively connected to a third potential.     10. The capacitive touch screen according to claim 9, wherein the first switch and the third switch are driven by a first clock, and the second switch and the fourth switch are driven by a second clock. Input sensing circuit. 10. The capacitive touch screen input sensing circuit according to claim 9, wherein the third potential is the same as the second potential. An inverted switched capacitor integrator circuit;
Connected to the inverting switched capacitor integrating circuit, and a non-inverting switched capacitor integrating circuit;
Including
The switched capacitor integrating circuit, wherein the sampling capacitor of the inverting switched capacitor integrating circuit and the sampling capacitor of the non-inverting switched capacitor integrating circuit are the same capacitor.     The inverting switched capacitor integrating circuit integrates the voltage charged in the sampling capacitor and outputs a negative voltage, and the non-inverting switched capacitor integrating circuit outputs the voltage charged in the sampling capacitor. The switched capacitor integrating circuit according to claim 12, which is integrated to output a positive value.     The switched capacitor integration circuit according to claim 12, wherein at least a part of an integration time interval of the inverting switched capacitor integration circuit does not overlap with an integration time interval of the non-inverting switched capacitor integration circuit.     The switched capacitor integrating circuit according to claim 12, wherein the sampling capacitor is formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.     A noise source that is input in a wired or wireless manner is connected to an amplifier of the inverting switched capacitor integrator and an amplifier of the non-inverting switched capacitor integrator among the two terminals of the sampling capacitor. Item 13. The switched capacitor integration circuit according to item 12.     The switched capacitor integrating circuit according to claim 12, wherein the third potential is the same as the second potential. A capacitor;
A charge / discharge circuit coupled to the capacitor to charge and discharge the capacitor;
Connected to the charge / discharge circuit, an inverting integration circuit;
Connected to the charge / discharge circuit, and a non-inverting integration circuit;
Including integration circuit.     The inverting integration circuit integrates the voltage charged in the capacitor and outputs a negative voltage, and the non-inverting integration circuit integrates the voltage charged in the capacitor and outputs a positive value. The integrating circuit according to claim 18, wherein the integrating circuit is configured as follows.     19. The integration circuit according to claim 18, wherein the capacitor is formed by a sensing pattern and an operation pattern formed on a capacitive touch screen.     19. The integration circuit according to claim 18, wherein a noise source that is input in a wired or wireless manner is connected to one terminal connected to the inverting integration circuit and the non-inverting integration circuit among both terminals of the capacitor.     19. The integration circuit according to claim 18, wherein at least a part of the integration time interval of the inverting integration circuit does not overlap with the integration time interval of the non-inverting integration circuit.     The integration circuit according to claim 18, wherein the third potential is the same as the second potential. A first operational amplifier, a second operational amplifier, and a capacitor;
The inverting input terminals of the first operational amplifier and the second operational amplifier are connected to the first terminal of the capacitor,
The inverting input terminal and the output terminal of the first operational amplifier are connected to each other through a first switch and a first feedback capacitor connected in series, and the inverting input terminal and the output terminal of the second operational amplifier are connected. Are connected to each other via a second switch and a second feedback capacitor connected in series,
The second terminal of the capacitor is connected to the first potential and the second potential through a third switch and a fourth switch, respectively.
The non-inverting input terminals of the first operational amplifier and the second operational amplifier are connected to a third potential, respectively.     The integration circuit according to claim 24, wherein the third potential is the same as the second potential.

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