WO2015170547A1 - Amplifier circuit, integration circuit, and a/d converter - Google Patents

Amplifier circuit, integration circuit, and a/d converter Download PDF

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Publication number
WO2015170547A1
WO2015170547A1 PCT/JP2015/061096 JP2015061096W WO2015170547A1 WO 2015170547 A1 WO2015170547 A1 WO 2015170547A1 JP 2015061096 W JP2015061096 W JP 2015061096W WO 2015170547 A1 WO2015170547 A1 WO 2015170547A1
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terminal
transistor
switch
voltage
inverter circuit
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PCT/JP2015/061096
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French (fr)
Japanese (ja)
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雅則 古田
板倉　哲朗
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株式会社 東芝
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Publication of WO2015170547A1 publication Critical patent/WO2015170547A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Definitions

  • Embodiments of the present invention relate to an amplifier circuit, an integration circuit, and an AD converter.
  • CMOS inverter circuit is used as an amplifier circuit.
  • a method for amplifying the gain of a CMOS inverter circuit a method has been proposed in which the CMOS inverter circuit has a cascode configuration, the drain voltage of the input-side transistor is amplified by a grounded source circuit, and is fed back to the gate terminal of the output-side transistor.
  • a CMOS inverter circuit has a problem in that power consumption increases because a source grounding circuit is used.
  • JSSC2013 "A 0.8-V 230-W 98-dB DR Inverter-Based Modulator for Audio Applications Applications Modulator for Audio Applications, JSSC2013 JSSC2003 ”A 10-b 30-MS / s Low-Power Pipelined CMOS A / D Converter Using a Pseudo differential Architecture”
  • An amplifier circuit includes a first transistor, a second transistor, a first inverter circuit, a first capacitor, a first switch, a first voltage source, a second switch, and a third transistor. And a fourth transistor, a second inverter circuit, a third capacitor, a third switch, a second voltage source, and a fourth switch.
  • the first transistor is the first conductivity type.
  • the second transistor has a first terminal connected to the first terminal of the first transistor.
  • the first inverter circuit has an input terminal connected to the first terminal of the first transistor and an output terminal connected to the control terminal of the second transistor.
  • the first capacitive element is connected between the first terminal of the first transistor and the input terminal of the first inverter circuit.
  • the second capacitive element is connected between the control terminal of the second transistor and the output terminal of the first inverter circuit.
  • the first switch connects the input terminal and the output terminal of the first inverter circuit.
  • the first voltage source supplies a predetermined first voltage.
  • the second switch connects the first voltage source and the control terminal of the second transistor.
  • the third transistor is of the second conductivity type.
  • the fourth transistor has a first terminal connected to the first terminal of the third transistor.
  • the second inverter circuit has an input terminal connected to the first terminal of the third transistor and an output terminal connected to the control terminal of the fourth transistor.
  • the third capacitive element is connected between the first terminal of the third transistor and the input terminal of the second inverter circuit.
  • the fourth capacitive element is connected between the control terminal of the fourth transistor and the output terminal of the second inverter circuit.
  • the third switch connects the input terminal and the output terminal of the second inverter circuit.
  • the second voltage source supplies a predetermined second voltage.
  • the fourth switch connects the second voltage source and the control terminal of the fourth transistor.
  • the figure which shows an example of an inverter circuit. 3 is a timing chart showing the operation of the amplifier circuit according to the first embodiment.
  • the figure which shows the amplifier circuit which concerns on 3rd Embodiment. 9 is a timing chart showing the operation of the amplifier circuit according to the third embodiment.
  • the drain-source voltage of each transistor Mi is referred to as Vdsi
  • the gate-source voltage is referred to as Vgsi
  • the overdrive voltage is referred to as Vovi
  • the threshold voltage is referred to as Vthi.
  • FIG. 1 is a diagram illustrating an amplifier circuit according to the present embodiment.
  • the amplifier circuit according to this embodiment includes a transistor M1, a transistor M2, an inverter circuit Inv1, a capacitive element C1, a capacitive element C2, a switch S1, a voltage source V1, and a switch S2.
  • the transistors M1 to M4 constitute an inverter circuit Inv10 having a cascode configuration, amplifies the input voltage Vin, and outputs an output voltage Vout.
  • the transistor M1 (first transistor) is an N-channel (first conductivity type) MOS transistor (hereinafter referred to as “NMOS transistor”), which receives an input voltage Vin from a gate terminal (control terminal) and grounds a source terminal.
  • the drain terminal (first terminal) is connected to the source terminal of the transistor M2.
  • the gate terminal of the transistor M1 becomes an input terminal of the inverter circuit Inv10.
  • the transistor M2 (second transistor) is an NMOS transistor, the source terminal (first terminal) is connected to the drain terminal (first terminal) of the transistor M1, and the drain terminal (second terminal) is connected to the drain terminal of the transistor M4. It is connected.
  • the gate terminal (control terminal) of the transistor M2 is connected to the output terminal of the inverter circuit Inv1 through the capacitive element C2, and is connected to the voltage source V1 through the switch S2.
  • the voltage at the drain terminal of the transistor M2 is output as the output voltage Vout of the amplifier circuit according to this embodiment. That is, the drain terminal of the transistor M2 becomes an output terminal of the inverter circuit Inv10.
  • the inverter circuit Inv1 (first inverter circuit) is an internal amplifier circuit for performing negative feedback.
  • the input terminal is connected to the drain terminal (first terminal) of the transistor M1 via the capacitive element C1, and the output terminal is connected to the gate terminal (control terminal) of the transistor M2 via the capacitive element C2.
  • FIG. 2 is a diagram illustrating an example of the inverter circuit Inv1.
  • the inverter circuit Inv1 in FIG. 2 is a CMOS inverter circuit including a transistor M11 and a transistor M12 whose drain terminals are connected to each other.
  • the transistor M11 is an NMOS transistor, and the source terminal is grounded.
  • the transistor M12 is a P-channel (second conductivity type) MOS transistor (hereinafter referred to as “PMOS transistor”), and has a source terminal connected to the power supply Vdd.
  • the gate terminals of the transistors M11 and M12 are input terminals, and the drain terminals are output terminals.
  • the configuration of the inverter circuit Inv1 is not limited to this, and may be an inverter circuit having a cascode configuration.
  • the capacitive element C1 (first capacitive element) is connected between the drain terminal (first terminal) of the transistor M1 and the input terminal of the inverter circuit Inv1.
  • the capacitive element C2 (second capacitive element) is connected between the gate terminal (control terminal) of the transistor M2 and the output terminal of the inverter circuit Inv1.
  • the switch S1 (first switch) is provided in parallel with the inverter circuit Inv1, and connects or opens the input terminal and the output terminal of the inverter circuit Inv1. Opening and closing of the switch S1 is controlled by a control signal ⁇ 1.
  • the switch S1 is turned on (closed state) when the control signal ⁇ 1 is High, and is turned off (open state) when the control signal ⁇ 1 is Low.
  • a MOS transistor is used as the switch S1.
  • the voltage source V1 (first voltage source) is a constant voltage source that supplies a predetermined bias voltage V1 (first voltage) to the gate terminal of the transistor M2.
  • the bias voltage V1 is set in advance so that the transistors M1 and M2 operate in a saturation region, that is, Vds1 ⁇ Vov1 and Vds2 ⁇ Vov2. Since the minimum value of the voltage at the gate terminal of the transistor M2 in which the transistors M1 and M2 operate in the saturation region is Vov1 + Vov2 + Vth2, the bias voltage V1 can be arbitrarily set within the range of V1 ⁇ Vov1 + Vov2 + Vth2.
  • the switch S2 (second switch) is provided between the voltage source V1 and the gate terminal (control terminal) of the transistor M2, and connects or opens between them. Opening and closing of the switch S2 is controlled by a control signal ⁇ 1.
  • the switch S2 is turned on (closed state) when the control signal ⁇ 1 is High, and is turned off (open state) when the control signal ⁇ 1 is Low.
  • a MOS transistor is used as the switch S2.
  • the transistor M3 (third transistor) is a PMOS transistor, which receives an input voltage Vin from a gate terminal (control terminal), has a source terminal connected to the power supply Vdd, and has a drain terminal (first terminal) the source terminal of the transistor M4. It is connected to the.
  • the gate terminal of the transistor M3 becomes an input terminal of the inverter circuit Inv10.
  • the transistor M4 (fourth transistor) is a PMOS transistor, the source terminal (first terminal) is connected to the drain terminal (first terminal) of the transistor M3, and the drain terminal (second terminal) is connected to the drain terminal (transistor M2). 2nd terminal).
  • the gate terminal (control terminal) of the transistor M4 is connected to the output terminal of the inverter circuit Inv2 through the capacitive element C4, and is connected to the voltage source V2 through the switch S4.
  • the voltage at the drain terminal of the transistor M4 is output as the output voltage Vout of the amplifier circuit according to this embodiment. That is, the drain terminal of the transistor M4 is an output terminal of the inverter circuit Inv10.
  • the inverter circuit Inv2 (second inverter circuit) is an internal amplifier circuit for performing negative feedback.
  • the input terminal is connected to the drain terminal (first terminal) of the transistor M3 via the capacitive element C3, and the output terminal is connected to the gate terminal (control terminal) of the transistor M4 via the capacitive element C4.
  • the inverter circuit Inv2 may be a CMOS inverter circuit (see FIG. 2) including an NMOS transistor M21 and a PMOS transistor M22 whose drain terminals are connected to each other, or an inverter circuit having a cascode configuration. May be.
  • the capacitive element C3 (third capacitive element) is connected between the drain terminal (first terminal) of the transistor M3 and the input terminal of the inverter circuit Inv2.
  • the capacitive element C4 (fourth capacitive element) is connected between the gate terminal (control terminal) of the transistor M4 and the output terminal of the inverter circuit Inv2.
  • the switch S3 (third switch) is provided in parallel with the inverter circuit Inv2, and connects or opens the input terminal and the output terminal of the inverter circuit Inv2. Opening and closing of the switch S3 is controlled by a control signal ⁇ 1.
  • the switch S3 is turned on (closed state) when the control signal ⁇ 1 is High, and is turned off (open state) when the control signal ⁇ 1 is Low.
  • a MOS transistor is used as the switch S3.
  • the voltage source V2 (second voltage source) is a constant voltage source that supplies a predetermined bias voltage V2 (second voltage) to the gate terminal of the transistor M4.
  • the bias voltage V2 is set in advance so that the transistors M3 and M4 operate in the saturation region, that is, Vds3 ⁇ Vov3 and Vds4 ⁇ Vov4. Since the maximum value of the voltage at the gate terminal of the transistor M4 in which the transistors M3 and M4 operate in the saturation region is Vdd-Vov3-Vov2-Vth2, the bias voltage V2 is in the range of V2 ⁇ Vdd-Vov3-Vov2-Vth2. It can be set arbitrarily.
  • the switch S4 (fourth switch) is provided between the voltage source V2 and the gate terminal (control terminal) of the transistor M4, and connects or opens between them. Opening and closing of the switch S4 is controlled by a control signal ⁇ 1.
  • the switch S4 is turned on (closed state) when the control signal ⁇ 1 is High, and is turned off (open state) when the control signal ⁇ 1 is Low.
  • a MOS transistor is used as the switch S4.
  • FIG. 3 is a timing chart showing the operation of the amplifier circuit according to this embodiment.
  • the amplifier circuit according to this embodiment performs a discrete time amplification operation. That is, there are two operation states of an amplification phase that amplifies the input voltage Vin and a storage phase that does not amplify the input voltage Vin, and the two phases are alternately repeated.
  • the storage phase is a period in which the amplifier circuit does not perform an amplification operation, and the control signal ⁇ 1 is High, that is, the switches S1 to S4 are turned on.
  • the voltage at the terminal on the transistor M1 side of the capacitive element C1 is a predetermined voltage corresponding to Vds1 when the operating point voltage of the input voltage Vin is applied to the gate terminal of the transistor M1, that is, the operating point voltage of the input voltage Vin. Voltage.
  • the voltage source V1 and the capacitive element C2 are connected when the switch S2 is turned on, the voltage at the terminal on the transistor M2 side of the capacitive element C2 becomes the bias voltage V1.
  • the amplification phase is a period in which the amplification circuit performs an amplification operation, and the control signal ⁇ 1 is Low, that is, the switches S1 to S4 are off.
  • the amplifier circuit amplifies the input voltage Vin with a predetermined gain and outputs an output voltage Vout.
  • the inverter circuit Inv10 that performs the amplification operation has a cascode configuration, and negative feedback is applied by the inverter circuits Inv1 and 2, so that the input voltage Vin is amplified with a high gain. Can do.
  • the internal amplifier circuits used for the negative feedback are the inverter circuits Inv1 and Inv2, a bias current for driving the internal amplifier circuit during the negative feedback becomes unnecessary. Therefore, power consumption required for the amplifying operation can be reduced as compared with the conventional amplifying circuit in which negative feedback is performed by the common source circuit.
  • the voltage at the terminal on the transistor M2 side of the capacitive element C2 can be set to an arbitrary bias voltage V1, so that the transistors M1 to M4 can be reliably operated in the saturation region and the output voltage
  • the operating range of Vin can be widened.
  • the operation range here is a range of the output voltage Vin in which the input voltage Vin can be amplified and output by the amplifier circuit.
  • the output voltage of the inverter circuit Inv1 is directly applied to the gate terminal of the transistor M2.
  • the inverter circuit Inv1 has the configuration shown in FIG. 2, the operating point voltage of the inverter circuit Inv1 is about Vdd / 2, and the voltage at the gate terminal of the transistor M2 is also about Vdd / 2. Since this voltage is larger than the minimum value Vov1 + Vov2 + Vth2 of the voltage at the gate terminal for the transistors M1 and M2 to operate in the saturation region, the operating range of the output voltage is narrowed.
  • the output voltage of the inverter circuit Inv1 and the gate voltage of the transistor M2 can be separated by the capacitive element C2, and the gate voltage can be set to an arbitrary value. That is, the gate voltage can be set to a voltage smaller than Vdd / 2 within the range of the minimum voltage Vov1 + Vov2 + Vth2.
  • the lower limit voltage of the operating range of the output voltage Vout can be lowered.
  • the upper limit voltage of the operating range of the output voltage Vout can be increased by providing the capacitor C4 in the amplifier circuit. Therefore, the operating range of the output voltage Vout can be widened.
  • the inverter circuit Inv10 has a two-stage cascode configuration, but may have a three-stage or more cascode configuration.
  • FIG. 4 is a diagram illustrating an amplifier circuit according to the present embodiment.
  • the amplifier circuit according to the present embodiment includes a transistor M5, a switch S5, a transistor M6, and a switch S6.
  • the transistors M5 and M6 constitute an inverter circuit Inv20.
  • Other configurations are the same as those of the amplifier circuit according to the first embodiment.
  • the transistor M5 (fifth transistor) is an NMOS transistor, the gate terminal (control terminal) is connected to the gate terminal (control terminal) of the transistor M1, the source terminal is grounded, and the drain terminal (first terminal) is the switch S5. It is connected to the.
  • the transistor M5 receives the input voltage Vin from the gate terminal.
  • the gate terminal of the transistor M5 becomes an input terminal of the inverter circuit Inv20.
  • the switch S5 (fifth switch) is provided between the drain terminal (first terminal) of the transistor M1 and the drain terminal (first terminal) of the transistor M5, and connects or opens between them. Opening and closing of the switch S5 is controlled by a control signal ⁇ BST .
  • the switch S5 is turned on (closed state) when the control signal ⁇ BST is High, and is turned off (open state) when the control signal ⁇ BST is Low.
  • a MOS transistor is used as the switch S5.
  • the transistor M6 (sixth transistor) is a PMOS transistor, the gate terminal (control terminal) is connected to the gate terminal (control terminal) of the transistor M3, the source terminal is connected to the power supply Vdd, and the drain terminal (first terminal). Is connected to the switch S6.
  • the transistor M6 receives the input voltage Vin from the gate terminal.
  • the gate terminal of the transistor M6 becomes an input terminal of the inverter circuit Inv20.
  • the switch S6 (sixth switch) is provided between the drain terminal (first terminal) of the transistor M3 and the drain terminal (first terminal) of the transistor M6, and connects or opens between them. Opening and closing of the switch S6 is controlled by a control signal ⁇ BST .
  • the switch S6 is turned on (closed state) when the control signal ⁇ BST is High, and is turned off (open state) when the control signal ⁇ BST is Low.
  • a MOS transistor is used as the switch S6.
  • FIG. 5 is a simplified diagram of the amplifier circuit of FIG. In FIG. 5, the configurations of the inverter circuits Inv1, 2 and the like are omitted.
  • the amplifier circuit according to this embodiment has a configuration in which an inverter circuit Inv20 is connected in parallel to an inverter circuit Inv10 that performs an amplification operation.
  • the inverter circuit Inv20 With such a configuration, current can be driven by the inverter circuit Inv20, so that the current drive capability of the amplifier circuit can be improved.
  • the added inverter circuit Inv20 is not a cascode configuration but a simple configuration including two transistors M5 and M6, the device size of the transistors M5 and M6 is adjusted to easily adjust the magnitude of the drive current. be able to.
  • FIG. 6 is a timing chart illustrating the operation of the amplifier circuit according to the present embodiment, and a diagram illustrating the output voltage Vout corresponding to the timing chart.
  • the solid line indicates the output voltage Vout of the amplifier circuit according to this embodiment
  • the broken line indicates the output voltage Vout of the amplifier circuit according to the first embodiment.
  • the control signal ⁇ BST becomes High when the control signal ⁇ 1 becomes Low, and becomes Low after a predetermined time. That is, the switches S5 and S6 are turned on when the switches S1 to S4 are turned off, and are turned off after a predetermined time.
  • the period during which the switches S5 and S6 are on is set shorter than the duration of the amplification phase.
  • the current drive capability of the amplifier circuit is improved at a predetermined time in the initial stage of the amplification phase, and the period until the output voltage Vout is amplified with a desired gain is shortened. Therefore, the amplification operation can be speeded up.
  • FIG. 7 is a diagram illustrating an amplifier circuit according to the present embodiment.
  • the amplifier circuit according to the present embodiment includes a voltage source V3, a switch S7, and a switch S8.
  • Other configurations are the same as those of the amplifier circuit according to the first embodiment.
  • the voltage source V3 (third voltage source) is a constant voltage source that supplies a predetermined bias voltage V3 (third voltage) to the gate terminals (control terminals) of the transistors M1 and M3.
  • the bias voltage V3 is set so that the transistor M1 or the transistor M3 is turned off.
  • a ground or a power supply Vdd can be used as the voltage source V3, for example, a ground or a power supply Vdd can be used.
  • the switch S7 is provided between the gate terminals (control terminals) of the transistors M1 and M3 and the voltage source V3, and connects or opens between them. Opening and closing of the switch S7 is controlled by a control signal ⁇ 2.
  • the switch S7 is turned on (closed state) when the control signal ⁇ 2 is High, and is turned off (open state) when the control signal ⁇ 2 is Low.
  • a MOS transistor is used as the switch S7.
  • the switch S8 is provided between the gate terminals (control terminals) of the transistors M1 and M3 and the drain terminals (second terminals) of the transistors M2 and M4, and connects or opens between them. Opening and closing of the switch S8 is controlled by a control signal ⁇ 1.
  • the switch S8 is turned on (closed state) when the control signal ⁇ 1 is High, and turned off (opened state) when the control signal ⁇ 1 is Low.
  • a MOS transistor is used as the switch S8.
  • FIG. 8 is a timing chart showing the operation of the amplifier circuit according to this embodiment.
  • the amplifier circuit according to the present embodiment has three operation states of a storage phase, an amplification phase, and a cutoff phase, and the three phases are sequentially repeated.
  • control signal ⁇ 1 is High and the control signal ⁇ 2 is Low. That is, the switches S1 to S4 and S8 are on and the switch S7 is off.
  • the output terminal voltage of the inverter circuit Inv10 that is, the operating point voltage of the drain terminals of the transistors M1 and M4 is set to the operating point voltage of the input voltage Vin.
  • FIG. 9 is a diagram showing input / output characteristics of a general CMOS inverter circuit.
  • the horizontal axis is the input voltage Vin
  • the vertical axis is the output voltage Vout.
  • a CMOS inverter circuit receives an input voltage Vin in which a signal component (AC component) is superimposed on an operating point voltage, and outputs an output voltage Vout in which an amplified signal component (AC component) is superimposed on the operating point voltage.
  • the amplification phase is started.
  • the control signal ⁇ 1 is low and the control signal ⁇ 2 is low. That is, the switches S1 to S4, S7, and S8 are turned off.
  • the amplification operation in the amplification phase is the same as in the first embodiment.
  • the blocking phase is started.
  • the control signal ⁇ 1 is low and the control signal ⁇ 2 is high. That is, the switches S1 to S4 and S7 are turned off and the switch S8 is turned on.
  • the control signal ⁇ 1 becomes High after a predetermined time delay, and the storage phase is started again.
  • FIG. 10 is a diagram illustrating an integration circuit according to the present embodiment.
  • the integrating circuit according to the present embodiment includes an amplifier circuit, a switch S9, a switch S10, a capacitive element C5, a switch S11, a switch S12, and a capacitive element C6.
  • the configuration of the amplifier circuit is omitted except for the inverter circuit Inv10 and the switch S8.
  • the switch S9 is provided between a current source (not shown) of the input current Iin to be integrated by the integration circuit and one terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S9 is controlled by a control signal ⁇ 3.
  • the switch S9 is turned on (closed state) when the control signal ⁇ 3 is High, and is turned off (open state) when the control signal ⁇ 3 is Low.
  • a MOS transistor is used as the switch S9.
  • the switch S10 is provided between the ground and one terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S10 is controlled by a control signal ⁇ 4.
  • the switch S10 is turned on (closed state) when the control signal ⁇ 4 is High, and is turned off (open state) when the control signal ⁇ 4 is Low.
  • a MOS transistor is used as the switch S10.
  • the capacitor element C5 has one terminal connected to the switches S9 and S10 and the other terminal connected to the switches S11 and S12. When the switch S9 and the switch S11 are turned on, the capacitor C5 has one terminal connected to the current source and the other terminal grounded, and accumulates electric charge according to the input current Iin. When the switch S10 and the switch S12 are turned on, the capacitor C5 has one terminal grounded, the other terminal connected to the input terminal of the amplifier circuit, and transfers the accumulated charge to the capacitor C6.
  • the capacitive element C5 functions as a pre-integration capacitor of this integration circuit.
  • the switch S11 is provided between the ground and the other terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S11 is controlled by a control signal ⁇ 3.
  • the switch S11 is turned on (closed state) when the control signal ⁇ 3 is High, and is turned off (open state) when the control signal ⁇ 3 is Low.
  • a MOS transistor is used as the switch S11.
  • the switch S12 is provided between the other terminal of the capacitive element C5 and the input terminal of the inverter circuit Inv10, and connects or opens between them. Opening and closing of the switch S12 is controlled by a control signal ⁇ 4.
  • the switch S12 is turned on (closed state) when the control signal ⁇ 4 is High, and is turned off (open state) when the control signal ⁇ 4 is Low.
  • a MOS transistor is used as the switch S12.
  • the capacitor element C6 has one terminal connected to the input terminal of the amplifier circuit and the other terminal connected to the output terminal of the amplifier circuit. That is, the capacitive element C6 is connected in parallel with the amplifier circuit.
  • the switch S10 and the switch S12 are turned on, the charge accumulated in the capacitive element C5 is transferred by the negative feedback of the amplifier circuit, and the transferred charge is accumulated in the capacitive element C6.
  • the voltage at the other terminal of the capacitive element C6 becomes the output voltage Vout of this integrating circuit.
  • FIG. 11 is a timing chart showing the operation of the integrating circuit according to this embodiment. As shown in FIG. 11, this integration circuit has two operation states of a sampling phase and a transfer phase when attention is paid to the operation of the switches S9 to S12.
  • the control signal ⁇ 3 is High and the control signal ⁇ 4 is Low. That is, the switches S9 and S11 are turned on and the switches S10 and S12 are turned off. Therefore, in the sampling phase, charges corresponding to the input current Iin are accumulated in the capacitive element C5.
  • the amplifier circuit and the capacitive element C6 are electrically separated from the capacitive element C5, and the amplifier circuit performs the above-described shut-off phase and storage phase operation.
  • the storage phase is performed during an arbitrary period during the sampling phase, and the blocking phase is performed during the remaining period. Thereby, the power consumption of the integration circuit can be reduced.
  • control signal ⁇ 3 becomes Low and the sampling phase ends, the control signal ⁇ 4 becomes High with a predetermined time delay, and the transfer phase is started.
  • the control signal ⁇ 4 becomes High from the timing when the control signal ⁇ 3 becomes Low, it is possible to prevent a short circuit of the integrating circuit.
  • control signal ⁇ 3 is Low and the control signal ⁇ 4 is High. That is, the switches S10 and S12 are turned on and the switches S9 and S11 are turned off.
  • the amplifier circuit performs the operation of the above-described amplification phase, and amplifies the input voltage Vin with a predetermined gain.
  • the charge accumulated in the capacitive element C5 is transferred to the capacitive element C6, and the voltage at the other terminal of the capacitive element C6 is output as the output voltage Vout.
  • Vout (C5 / C6) ⁇ Vin.
  • Vout (t) (C5 / C6) (1-exp ( ⁇ 1 / ⁇ )) ⁇ Vin
  • the output voltage Vout approaches (C5 / C6) ⁇ Vin over time.
  • the duration of the transfer phase is determined according to C5, C6, ⁇ and the required integration accuracy.
  • the integration circuit according to the present embodiment can suppress the power consumption of the amplifier circuit during the sampling period. Further, since the amplifier circuit has a high gain, the integration operation can be performed with high accuracy. Furthermore, since the current source and the integration circuit are electrically separated during the transfer phase, it is possible to prevent the occurrence of an integration error that occurs when the input current Iin is input during the transfer phase.
  • the integrating circuit includes the amplifier circuit according to the first and second embodiments.
  • the integration circuit includes the amplifier circuit according to the second embodiment, the current driving capability of the amplifier circuit is improved, so that the time constant ⁇ is reduced. Therefore, the transfer phase can be shortened and the integration operation can be speeded up.
  • FIG. 12 is a diagram illustrating the AD converter according to the present embodiment.
  • the AD converter according to the present embodiment is a pipeline AD converter including a plurality of pipeline stages.
  • FIG. 13 is a diagram showing an example of the pipeline stage of the AD converter. In this pipeline stage, 1-bit AD conversion is performed. As shown in FIG. 13, the pipeline stage includes an integration circuit according to the fourth embodiment, an AD conversion circuit ADC, and a DA conversion circuit DAC.
  • the AD converter circuit ADC outputs 1 when the input voltage corresponding to the input current Iin is equal to or higher than the reference voltage Vref, and outputs 0 when it is lower than the reference voltage Vref. Thereby, 1-bit AD conversion is performed.
  • the DA conversion circuit DAC DA converts the output signal of the AD conversion circuit ADC.
  • the DA conversion circuit DAC outputs a current corresponding to the reference voltage Vref when the output signal of the AD conversion circuit ADC is 1, and does not output a current when the output signal is 0.
  • the AD converter includes the integration circuit according to the fourth embodiment, the AD converter has low power consumption and can perform AD conversion with high accuracy.
  • the AD converter may be configured to be fully differential, or configured to perform AD conversion of a plurality of bits or AD conversion having redundant bits such as 1.5 bits at each pipeline stage. It is also possible.
  • the amplifier circuit and the integration circuit according to each of the embodiments described above can be applied to any AD converter other than the pipeline AD converter.
  • the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.
  • various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.
  • C1 to C6 Capacitance elements
  • S1 to S12 Switches
  • Inv1, Inv2, Inv10, Inv20 Inverter circuits
  • V1 to V3 Voltage sources
  • ⁇ 1 to ⁇ 4 Control signals
  • ADC AD conversion circuit
  • DAC DA conversion circuit

Abstract

[Problem] To provide an amplifier circuit having low power consumption, an integrator, and an A/D converter. [Solution] An amplifier circuit according to one embodiment of the present invention is provided with: first to fourth transistors (M1-M4); first and second inverter circuits (Inv1, Inv2); first to fourth capacitance elements (C1-C4); first to fourth switches (S1-S4); and first and second voltage sources (V1, V2). The first and second (third and fourth) transistors have a first (second) conductivity type. The second (fourth) transistor has the first terminal thereof connected to the first terminal of the first (third) transistor. The first (second) inverter circuit has the input terminal thereof connected to the first terminal of the first (third) transistor, and has the output terminal thereof connected to the control terminal of the second (fourth) transistor. The first (third) capacitance element is connected between the first terminal of the first (third) transistor and the input terminal of the first (second) inverter circuit. The second (fourth) capacitance element is connected between the control terminal of the second (fourth) transistor and the output terminal of the first (second) inverter circuit.

Description

増幅回路、積分回路及びＡＤ変換器Amplification circuit, integration circuit, and AD converter
　本発明の実施形態は、増幅回路、積分回路及びＡＤ変換器に関する。 Embodiments of the present invention relate to an amplifier circuit, an integration circuit, and an AD converter.
　従来、増幅回路として、ＣＭＯＳインバータ回路が用いられている。ＣＭＯＳインバータ回路の利得を増幅する方法として、ＣＭＯＳインバータ回路をカスコード構成とし、入力側のトランジスタのドレイン電圧をソース接地回路で増幅し、出力側のトランジスタのゲート端子に帰還させる方法が提案されている。しかしながら、このようなＣＭＯＳインバータ回路では、ソース接地回路を利用するため消費電力が増大するという問題があった。 Conventionally, a CMOS inverter circuit is used as an amplifier circuit. As a method for amplifying the gain of a CMOS inverter circuit, a method has been proposed in which the CMOS inverter circuit has a cascode configuration, the drain voltage of the input-side transistor is amplified by a grounded source circuit, and is fed back to the gate terminal of the output-side transistor. . However, such a CMOS inverter circuit has a problem in that power consumption increases because a source grounding circuit is used.
　低消費電力な増幅回路、積分器、及びＡＤ変換器を提供する。 Supplied low-power amplifier circuit, integrator, and AD converter.
　一実施形態に係る増幅回路は、第１トランジスタと、第２トランジスタと、第１インバータ回路と、第１容量素子と、第１スイッチと、第１電圧源と、第２スイッチと、第３トランジスタと、第４トランジスタと、第２インバータ回路と、第３容量素子と、第３スイッチと、第２電圧源と、第４スイッチとを備える。 An amplifier circuit according to an embodiment includes a first transistor, a second transistor, a first inverter circuit, a first capacitor, a first switch, a first voltage source, a second switch, and a third transistor. And a fourth transistor, a second inverter circuit, a third capacitor, a third switch, a second voltage source, and a fourth switch.
　第１トランジスタは、第１導電型である。第２トランジスタは、第１端子を第１トランジスタの第１端子に接続される。第１インバータ回路は、入力端子を第１トランジスタの第１端子に接続され、出力端子を第２トランジスタの制御端子に接続される。第１容量素子は、第１トランジスタの第１端子と第１インバータ回路の入力端子との間に接続される。第２容量素子は、第２トランジスタの制御端子と第１インバータ回路の出力端子との間に接続される。第１スイッチは、第１インバータ回路の入力端子と出力端子とを接続する。第１電圧源は、所定の第１電圧を供給する。第２スイッチは、第１電圧源と第２トランジスタの制御端子とを接続する。 The first transistor is the first conductivity type. The second transistor has a first terminal connected to the first terminal of the first transistor. The first inverter circuit has an input terminal connected to the first terminal of the first transistor and an output terminal connected to the control terminal of the second transistor. The first capacitive element is connected between the first terminal of the first transistor and the input terminal of the first inverter circuit. The second capacitive element is connected between the control terminal of the second transistor and the output terminal of the first inverter circuit. The first switch connects the input terminal and the output terminal of the first inverter circuit. The first voltage source supplies a predetermined first voltage. The second switch connects the first voltage source and the control terminal of the second transistor.
　第３トランジスタは、第２導電型である。第４トランジスタは、第１端子を第３トランジスタの第１端子に接続される。第２インバータ回路は、入力端子を第３トランジスタの第１端子に接続され、出力端子を第４トランジスタの制御端子に接続される。第３容量素子は、第３トランジスタの第１端子と第２インバータ回路の入力端子との間に接続される。第４容量素子は、第４トランジスタの制御端子と第２インバータ回路の出力端子との間に接続される。第３スイッチは、第２インバータ回路の入力端子と出力端子とを接続する。第２電圧源は、所定の第２電圧を供給する。第４スイッチは、第２電圧源と第４トランジスタの制御端子とを接続する。 The third transistor is of the second conductivity type. The fourth transistor has a first terminal connected to the first terminal of the third transistor. The second inverter circuit has an input terminal connected to the first terminal of the third transistor and an output terminal connected to the control terminal of the fourth transistor. The third capacitive element is connected between the first terminal of the third transistor and the input terminal of the second inverter circuit. The fourth capacitive element is connected between the control terminal of the fourth transistor and the output terminal of the second inverter circuit. The third switch connects the input terminal and the output terminal of the second inverter circuit. The second voltage source supplies a predetermined second voltage. The fourth switch connects the second voltage source and the control terminal of the fourth transistor.
第１実施形態に係る増幅回路を示す図。The figure which shows the amplifier circuit which concerns on 1st Embodiment. インバータ回路の一例を示す図。The figure which shows an example of an inverter circuit. 第１実施形態に係る増幅回路の動作を示すタイミングチャート。3 is a timing chart showing the operation of the amplifier circuit according to the first embodiment. 第２実施形態に係る増幅回路を示す図。The figure which shows the amplifier circuit which concerns on 2nd Embodiment. 第２実施形態に係る増幅回路を簡略化して示す図。The figure which shows simply the amplifier circuit which concerns on 2nd Embodiment. 第２実施形態に係る増幅回路の動作を示すタイミングチャート。The timing chart which shows the operation | movement of the amplifier circuit which concerns on 2nd Embodiment. 第３実施形態に係る増幅回路を示す図。The figure which shows the amplifier circuit which concerns on 3rd Embodiment. 第３実施形態に係る増幅回路の動作を示すタイミングチャート。9 is a timing chart showing the operation of the amplifier circuit according to the third embodiment. ＣＭＯＳインバータ回路の入出力特性を示す図。The figure which shows the input-output characteristic of a CMOS inverter circuit. 第４実施形態に係る積分回路を示す図。The figure which shows the integration circuit which concerns on 4th Embodiment. 第４実施形態に係る積分回路の動作を示すタイミングチャート。The timing chart which shows the operation | movement of the integration circuit which concerns on 4th Embodiment. 第５実施形態に係るＡＤ変換器を示す図。The figure which shows the AD converter which concerns on 5th Embodiment. パイプラインステージの一例を示す図。The figure which shows an example of a pipeline stage.
　以下、増幅回路、積分回路、及びＡＤ変換器の実施形態について図面を参照して説明する。なお、以下の説明において、各トランジスタＭｉのドレイン－ソース間電圧をＶｄｓｉ、ゲート－ソース間電圧をＶｇｓｉ、オーバドライブ電圧をＶｏｖｉ、閾値電圧をＶｔｈｉと称する。 Hereinafter, embodiments of an amplifier circuit, an integration circuit, and an AD converter will be described with reference to the drawings. In the following description, the drain-source voltage of each transistor Mi is referred to as Vdsi, the gate-source voltage is referred to as Vgsi, the overdrive voltage is referred to as Vovi, and the threshold voltage is referred to as Vthi.
（第１実施形態）
　まず、第１実施形態に係る増幅回路について、図１～図３を参照して説明する。図１は、本実施形態に係る増幅回路を示す図である。図１に示すように、本実施形態に係る増幅回路は、トランジスタＭ１と、トランジスタＭ２と、インバータ回路Ｉｎｖ１と、容量素子Ｃ１と、容量素子Ｃ２と、スイッチＳ１と、電圧源Ｖ１と、スイッチＳ２と、トランジスタＭ３と、トランジスタＭ４と、インバータ回路Ｉｎｖ２と、容量素子Ｃ３と、容量素子Ｃ４と、スイッチＳ３と、電圧源Ｖ２と、スイッチＳ４とを備える。トランジスタＭ１～Ｍ４は、カスコード構成を有するインバータ回路Ｉｎｖ１０を構成しており、入力電圧Ｖｉｎを増幅し、出力電圧Ｖｏｕｔを出力する。 (First embodiment)
First, the amplifier circuit according to the first embodiment will be described with reference to FIGS. FIG. 1 is a diagram illustrating an amplifier circuit according to the present embodiment. As shown in FIG. 1, the amplifier circuit according to this embodiment includes a transistor M1, a transistor M2, an inverter circuit Inv1, a capacitive element C1, a capacitive element C2, a switch S1, a voltage source V1, and a switch S2. A transistor M3, a transistor M4, an inverter circuit Inv2, a capacitor C3, a capacitor C4, a switch S3, a voltage source V2, and a switch S4. The transistors M1 to M4 constitute an inverter circuit Inv10 having a cascode configuration, amplifies the input voltage Vin, and outputs an output voltage Vout.
　トランジスタＭ１（第１トランジスタ）は、Ｎチャネル（第１導電型）のＭＯＳトランジスタ（以下、「ＮＭＯＳトランジスタ」という）であり、ゲート端子（制御端子）から入力電圧Ｖｉｎを入力され、ソース端子を接地され、ドレイン端子（第１端子）をトランジスタＭ２のソース端子に接続されている。トランジスタＭ１のゲート端子は、インバータ回路Ｉｎｖ１０の入力端子となる。 The transistor M1 (first transistor) is an N-channel (first conductivity type) MOS transistor (hereinafter referred to as “NMOS transistor”), which receives an input voltage Vin from a gate terminal (control terminal) and grounds a source terminal. The drain terminal (first terminal) is connected to the source terminal of the transistor M2. The gate terminal of the transistor M1 becomes an input terminal of the inverter circuit Inv10.
　トランジスタＭ２（第２トランジスタ）は、ＮＭＯＳトランジスタであり、ソース端子（第１端子）をトランジスタＭ１のドレイン端子（第１端子）に接続され、ドレイン端子（第２端子）をトランジスタＭ４のドレイン端子に接続されている。トランジスタＭ２のゲート端子（制御端子）は、容量素子Ｃ２を介してインバータ回路Ｉｎｖ１の出力端子に接続されるとともに、スイッチＳ２を介して電圧源Ｖ１に接続されている。トランジスタＭ２のドレイン端子の電圧は、本実施形態に係る増幅回路の出力電圧Ｖｏｕｔとして出力される。すなわち、トランジスタＭ２のドレイン端子は、インバータ回路Ｉｎｖ１０の出力端子となる。 The transistor M2 (second transistor) is an NMOS transistor, the source terminal (first terminal) is connected to the drain terminal (first terminal) of the transistor M1, and the drain terminal (second terminal) is connected to the drain terminal of the transistor M4. It is connected. The gate terminal (control terminal) of the transistor M2 is connected to the output terminal of the inverter circuit Inv1 through the capacitive element C2, and is connected to the voltage source V1 through the switch S2. The voltage at the drain terminal of the transistor M2 is output as the output voltage Vout of the amplifier circuit according to this embodiment. That is, the drain terminal of the transistor M2 becomes an output terminal of the inverter circuit Inv10.
　インバータ回路Ｉｎｖ１（第１インバータ回路）は、負帰還を行うための内部増幅回路である。入力端子は、容量素子Ｃ１を介してトランジスタＭ１のドレイン端子（第１端子）に接続され、出力端子は容量素子Ｃ２を介してトランジスタＭ２のゲート端子（制御端子）に接続されている。ここで、図２は、インバータ回路Ｉｎｖ１の一例を示す図である。 The inverter circuit Inv1 (first inverter circuit) is an internal amplifier circuit for performing negative feedback. The input terminal is connected to the drain terminal (first terminal) of the transistor M1 via the capacitive element C1, and the output terminal is connected to the gate terminal (control terminal) of the transistor M2 via the capacitive element C2. Here, FIG. 2 is a diagram illustrating an example of the inverter circuit Inv1.
　図２のインバータ回路Ｉｎｖ１は、ドレイン端子同士を接続されたトランジスタＭ１１とトランジスタＭ１２とからなるＣＭＯＳインバータ回路である。トランジスタＭ１１はＮＭＯＳトランジスタでありソース端子を接地されている。トランジスタＭ１２は、Ｐチャネル（第２導電型）のＭＯＳトランジスタ（以下、「ＰＭＯＳトランジスタ」という）であり、ソース端子を電源Ｖｄｄに接続されている。このインバータ回路Ｉｎｖ１では、トランジスタＭ１１，Ｍ１２のゲート端子が入力端子となり、ドレイン端子が出力端子となる。なお、インバータ回路Ｉｎｖ１の構成はこれに限られず、カスコード構成のインバータ回路であってもよい。 The inverter circuit Inv1 in FIG. 2 is a CMOS inverter circuit including a transistor M11 and a transistor M12 whose drain terminals are connected to each other. The transistor M11 is an NMOS transistor, and the source terminal is grounded. The transistor M12 is a P-channel (second conductivity type) MOS transistor (hereinafter referred to as “PMOS transistor”), and has a source terminal connected to the power supply Vdd. In the inverter circuit Inv1, the gate terminals of the transistors M11 and M12 are input terminals, and the drain terminals are output terminals. The configuration of the inverter circuit Inv1 is not limited to this, and may be an inverter circuit having a cascode configuration.
　容量素子Ｃ１（第１容量素子）は、トランジスタＭ１のドレイン端子（第１端子）と、インバータ回路Ｉｎｖ１の入力端子との間に接続されている。 The capacitive element C1 (first capacitive element) is connected between the drain terminal (first terminal) of the transistor M1 and the input terminal of the inverter circuit Inv1.
　容量素子Ｃ２（第２容量素子）は、トランジスタＭ２のゲート端子（制御端子）と、インバータ回路Ｉｎｖ１の出力端子との間に接続されている。 The capacitive element C2 (second capacitive element) is connected between the gate terminal (control terminal) of the transistor M2 and the output terminal of the inverter circuit Inv1.
　スイッチＳ１（第１スイッチ）は、インバータ回路Ｉｎｖ１と並列に設けられ、インバータ回路Ｉｎｖ１の入力端子と出力端子とを接続又は開放する。スイッチＳ１の開閉は制御信号φ１により制御される。スイッチＳ１は、制御信号φ１がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ１として、例えば、ＭＯＳトランジスタが用いられる。 The switch S1 (first switch) is provided in parallel with the inverter circuit Inv1, and connects or opens the input terminal and the output terminal of the inverter circuit Inv1. Opening and closing of the switch S1 is controlled by a control signal φ1. The switch S1 is turned on (closed state) when the control signal φ1 is High, and is turned off (open state) when the control signal φ1 is Low. For example, a MOS transistor is used as the switch S1.
　電圧源Ｖ１（第１電圧源）は、所定のバイアス電圧Ｖ１（第１電圧）をトランジスタＭ２のゲート端子に供給する定電圧源である。バイアス電圧Ｖ１は、トランジスタＭ１，Ｍ２が飽和領域で動作する、すなわち、Ｖｄｓ１≧Ｖｏｖ１かつＶｄｓ２≧Ｖｏｖ２となるように予め設定される。トランジスタＭ１，Ｍ２が飽和領域で動作するトランジスタＭ２のゲート端子の電圧の最低値は、Ｖｏｖ１＋Ｖｏｖ２＋Ｖｔｈ２であるから、バイアス電圧Ｖ１は、Ｖ１≧Ｖｏｖ１＋Ｖｏｖ２＋Ｖｔｈ２の範囲で任意に設定可能である。 The voltage source V1 (first voltage source) is a constant voltage source that supplies a predetermined bias voltage V1 (first voltage) to the gate terminal of the transistor M2. The bias voltage V1 is set in advance so that the transistors M1 and M2 operate in a saturation region, that is, Vds1 ≧ Vov1 and Vds2 ≧ Vov2. Since the minimum value of the voltage at the gate terminal of the transistor M2 in which the transistors M1 and M2 operate in the saturation region is Vov1 + Vov2 + Vth2, the bias voltage V1 can be arbitrarily set within the range of V1 ≧ Vov1 + Vov2 + Vth2.
　スイッチＳ２（第２スイッチ）は、電圧源Ｖ１とトランジスタＭ２のゲート端子（制御端子）との間に設けられ、これらの間を接続又は開放する。スイッチＳ２の開閉は制御信号φ１により制御される。スイッチＳ２は、制御信号φ１がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ２として、例えば、ＭＯＳトランジスタが用いられる。 The switch S2 (second switch) is provided between the voltage source V1 and the gate terminal (control terminal) of the transistor M2, and connects or opens between them. Opening and closing of the switch S2 is controlled by a control signal φ1. The switch S2 is turned on (closed state) when the control signal φ1 is High, and is turned off (open state) when the control signal φ1 is Low. For example, a MOS transistor is used as the switch S2.
　トランジスタＭ３（第３トランジスタ）は、ＰＭＯＳトランジスタであり、ゲート端子（制御端子）から入力電圧Ｖｉｎを入力され、ソース端子を電源Ｖｄｄに接続され、ドレイン端子（第１端子）をトランジスタＭ４のソース端子に接続されている。トランジスタＭ３のゲート端子は、インバータ回路Ｉｎｖ１０の入力端子となる。 The transistor M3 (third transistor) is a PMOS transistor, which receives an input voltage Vin from a gate terminal (control terminal), has a source terminal connected to the power supply Vdd, and has a drain terminal (first terminal) the source terminal of the transistor M4. It is connected to the. The gate terminal of the transistor M3 becomes an input terminal of the inverter circuit Inv10.
　トランジスタＭ４（第４トランジスタ）は、ＰＭＯＳトランジスタであり、ソース端子（第１端子）をトランジスタＭ３のドレイン端子（第１端子）に接続され、ドレイン端子（第２端子）をトランジスタＭ２のドレイン端子（第２端子）に接続されている。トランジスタＭ４のゲート端子（制御端子）は、容量素子Ｃ４を介してインバータ回路Ｉｎｖ２の出力端子に接続されるとともに、スイッチＳ４を介して電圧源Ｖ２に接続されている。トランジスタＭ４のドレイン端子の電圧は、本実施形態に係る増幅回路の出力電圧Ｖｏｕｔとして出力される。すなわち、トランジスタＭ４のドレイン端子は、インバータ回路Ｉｎｖ１０の出力端子となる。 The transistor M4 (fourth transistor) is a PMOS transistor, the source terminal (first terminal) is connected to the drain terminal (first terminal) of the transistor M3, and the drain terminal (second terminal) is connected to the drain terminal (transistor M2). 2nd terminal). The gate terminal (control terminal) of the transistor M4 is connected to the output terminal of the inverter circuit Inv2 through the capacitive element C4, and is connected to the voltage source V2 through the switch S4. The voltage at the drain terminal of the transistor M4 is output as the output voltage Vout of the amplifier circuit according to this embodiment. That is, the drain terminal of the transistor M4 is an output terminal of the inverter circuit Inv10.
　インバータ回路Ｉｎｖ２（第２インバータ回路）は、負帰還を行うための内部増幅回路である。入力端子は、容量素子Ｃ３を介してトランジスタＭ３のドレイン端子（第１端子）に接続され、出力端子は、容量素子Ｃ４を介してトランジスタＭ４のゲート端子（制御端子）に接続されている。インバータ回路Ｉｎｖ２は、インバータ回路Ｉｎｖ１と同様、ドレイン端子同士を接続されたＮＭＯＳトランジスタＭ２１とＰＭＯＳトランジスタＭ２２とからなるＣＭＯＳインバータ回路（図２参照）であってもよいし、カスコード構成のインバータ回路であってもよい。 The inverter circuit Inv2 (second inverter circuit) is an internal amplifier circuit for performing negative feedback. The input terminal is connected to the drain terminal (first terminal) of the transistor M3 via the capacitive element C3, and the output terminal is connected to the gate terminal (control terminal) of the transistor M4 via the capacitive element C4. Similarly to the inverter circuit Inv1, the inverter circuit Inv2 may be a CMOS inverter circuit (see FIG. 2) including an NMOS transistor M21 and a PMOS transistor M22 whose drain terminals are connected to each other, or an inverter circuit having a cascode configuration. May be.
　容量素子Ｃ３（第３容量素子）は、トランジスタＭ３のドレイン端子（第１端子）と、インバータ回路Ｉｎｖ２の入力端子との間に接続されている。 The capacitive element C3 (third capacitive element) is connected between the drain terminal (first terminal) of the transistor M3 and the input terminal of the inverter circuit Inv2.
　容量素子Ｃ４（第４容量素子）は、トランジスタＭ４のゲート端子（制御端子）と、インバータ回路Ｉｎｖ２の出力端子との間に接続されている。 The capacitive element C4 (fourth capacitive element) is connected between the gate terminal (control terminal) of the transistor M4 and the output terminal of the inverter circuit Inv2.
　スイッチＳ３（第３スイッチ）は、インバータ回路Ｉｎｖ２と並列に設けられ、インバータ回路Ｉｎｖ２の入力端子と出力端子とを接続又は開放する。スイッチＳ３の開閉は制御信号φ１により制御される。スイッチＳ３は、制御信号φ１がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ３として、例えば、ＭＯＳトランジスタが用いられる。 The switch S3 (third switch) is provided in parallel with the inverter circuit Inv2, and connects or opens the input terminal and the output terminal of the inverter circuit Inv2. Opening and closing of the switch S3 is controlled by a control signal φ1. The switch S3 is turned on (closed state) when the control signal φ1 is High, and is turned off (open state) when the control signal φ1 is Low. For example, a MOS transistor is used as the switch S3.
　電圧源Ｖ２（第２電圧源）は、所定のバイアス電圧Ｖ２（第２電圧）を、トランジスタＭ４のゲート端子に供給する定電圧源である。バイアス電圧Ｖ２は、トランジスタＭ３，Ｍ４が飽和領域で動作する、すなわち、Ｖｄｓ３≧Ｖｏｖ３かつＶｄｓ４≧Ｖｏｖ４となるように予め設定される。トランジスタＭ３，Ｍ４が飽和領域で動作するトランジスタＭ４のゲート端子の電圧の最高値は、Ｖｄｄ－Ｖｏｖ３－Ｖｏｖ２－Ｖｔｈ２であるから、バイアス電圧Ｖ２は、Ｖ２≦Ｖｄｄ－Ｖｏｖ３－Ｖｏｖ２－Ｖｔｈ２の範囲で任意に設定可能である。 The voltage source V2 (second voltage source) is a constant voltage source that supplies a predetermined bias voltage V2 (second voltage) to the gate terminal of the transistor M4. The bias voltage V2 is set in advance so that the transistors M3 and M4 operate in the saturation region, that is, Vds3 ≧ Vov3 and Vds4 ≧ Vov4. Since the maximum value of the voltage at the gate terminal of the transistor M4 in which the transistors M3 and M4 operate in the saturation region is Vdd-Vov3-Vov2-Vth2, the bias voltage V2 is in the range of V2 ≦ Vdd-Vov3-Vov2-Vth2. It can be set arbitrarily.
　スイッチＳ４（第４スイッチ）は、電圧源Ｖ２とトランジスタＭ４のゲート端子（制御端子）との間に設けられ、これらの間を接続又は開放する。スイッチＳ４の開閉は制御信号φ１により制御される。スイッチＳ４は、制御信号φ１がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ４として、例えば、ＭＯＳトランジスタが用いられる。 The switch S4 (fourth switch) is provided between the voltage source V2 and the gate terminal (control terminal) of the transistor M4, and connects or opens between them. Opening and closing of the switch S4 is controlled by a control signal φ1. The switch S4 is turned on (closed state) when the control signal φ1 is High, and is turned off (open state) when the control signal φ1 is Low. For example, a MOS transistor is used as the switch S4.
　次に、本実施形態に係る増幅回路の動作について、図３を参照して説明する。図３は、本実施形態に係る増幅回路の動作を示すタイミングチャートである。図３に示すように、本実施形態に係る増幅回路は、離散時間増幅動作を行う。すなわち、入力電圧Ｖｉｎを増幅する増幅フェーズと、入力電圧Ｖｉｎを増幅しない記憶フェーズと、の２つの動作状態を有し、２つのフェーズが交互に繰り返される。 Next, the operation of the amplifier circuit according to this embodiment will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the amplifier circuit according to this embodiment. As shown in FIG. 3, the amplifier circuit according to this embodiment performs a discrete time amplification operation. That is, there are two operation states of an amplification phase that amplifies the input voltage Vin and a storage phase that does not amplify the input voltage Vin, and the two phases are alternately repeated.
　記憶フェーズは、増幅回路が増幅動作を行わない期間であり、制御信号φ１がＨｉｇｈ、すなわち、スイッチＳ１～Ｓ４がオンになっている。 The storage phase is a period in which the amplifier circuit does not perform an amplification operation, and the control signal φ1 is High, that is, the switches S1 to S4 are turned on.
　記憶フェーズにおいて、スイッチＳ１がオンになることにより、インバータ回路Ｉｎｖ１の入出力端子間が短絡し、インバータ回路Ｉｎｖ１の入出力端子の電圧は、インバータ回路Ｉｎｖ１のショート電圧となる。これにより、容量素子Ｃ１，Ｃ２のインバータ回路Ｉｎｖ１側の端子の電圧もショート電圧となる。 In the storage phase, when the switch S1 is turned on, the input / output terminals of the inverter circuit Inv1 are short-circuited, and the voltage of the input / output terminals of the inverter circuit Inv1 becomes the short circuit voltage of the inverter circuit Inv1. Thereby, the voltage at the terminal on the inverter circuit Inv1 side of the capacitive elements C1 and C2 also becomes a short voltage.
　また、容量素子Ｃ１のトランジスタＭ１側の端子の電圧は、入力電圧Ｖｉｎの動作点電圧がトランジスタＭ１のゲート端子に印加された場合のＶｄｓ１、すなわち、入力電圧Ｖｉｎの動作点電圧に応じた所定の電圧となる。 The voltage at the terminal on the transistor M1 side of the capacitive element C1 is a predetermined voltage corresponding to Vds1 when the operating point voltage of the input voltage Vin is applied to the gate terminal of the transistor M1, that is, the operating point voltage of the input voltage Vin. Voltage.
　さらに、スイッチＳ２がオンになることにより、電圧源Ｖ１と容量素子Ｃ２が接続されるため、容量素子Ｃ２のトランジスタＭ２側の端子の電圧は、バイアス電圧Ｖ１となる。 Further, since the voltage source V1 and the capacitive element C2 are connected when the switch S2 is turned on, the voltage at the terminal on the transistor M2 side of the capacitive element C2 becomes the bias voltage V1.
　これに対して、増幅フェーズは、増幅回路が増幅動作を行う期間であり、制御信号φ１がＬｏｗ、すなわち、スイッチＳ１～Ｓ４がオフになっている。増幅フェーズにおいて、増幅回路は、入力電圧Ｖｉｎを所定の利得で増幅し、出力電圧Ｖｏｕｔを出力する。 On the other hand, the amplification phase is a period in which the amplification circuit performs an amplification operation, and the control signal φ1 is Low, that is, the switches S1 to S4 are off. In the amplification phase, the amplifier circuit amplifies the input voltage Vin with a predetermined gain and outputs an output voltage Vout.
　以上説明した通り、本実施形態に係る増幅回路は、増幅動作を行うインバータ回路Ｉｎｖ１０がカスコード構成であるとともに、インバータ回路Ｉｎｖ１，２により負帰還がかかるため、高い利得で入力電圧Ｖｉｎを増幅することができる。 As described above, in the amplifier circuit according to the present embodiment, the inverter circuit Inv10 that performs the amplification operation has a cascode configuration, and negative feedback is applied by the inverter circuits Inv1 and 2, so that the input voltage Vin is amplified with a high gain. Can do.
　また、負帰還に用いられる内部増幅回路がインバータ回路Ｉｎｖ１，２であるため、負帰還の際に内部増幅回路を駆動するためのバイアス電流が不要となる。したがって、ソース接地回路により負帰還を行っていた従来の増幅回路に比べて、増幅動作に要する消費電力を低減することができる。 Also, since the internal amplifier circuits used for the negative feedback are the inverter circuits Inv1 and Inv2, a bias current for driving the internal amplifier circuit during the negative feedback becomes unnecessary. Therefore, power consumption required for the amplifying operation can be reduced as compared with the conventional amplifying circuit in which negative feedback is performed by the common source circuit.
　さらに、記憶フェーズにおいて、容量素子Ｃ２のトランジスタＭ２側の端子の電圧を任意のバイアス電圧Ｖ１に設定することができるため、トランジスタＭ１～Ｍ４を確実に飽和領域で動作させることができる上、出力電圧Ｖｉｎの動作範囲を広くすることができる。ここでいう動作範囲とは、増幅回路により入力電圧Ｖｉｎを増幅して出力することができる出力電圧Ｖｉｎの範囲のことである。 Furthermore, in the storage phase, the voltage at the terminal on the transistor M2 side of the capacitive element C2 can be set to an arbitrary bias voltage V1, so that the transistors M1 to M4 can be reliably operated in the saturation region and the output voltage The operating range of Vin can be widened. The operation range here is a range of the output voltage Vin in which the input voltage Vin can be amplified and output by the amplifier circuit.
　例えば、増幅回路が容量素子Ｃ２を備えない場合、トランジスタＭ２のゲート端子は、インバータ回路Ｉｎｖ１の出力電圧を直接印加される。インバータ回路Ｉｎｖ１が図２の構成の場合、インバータ回路Ｉｎｖ１の動作点電圧は約Ｖｄｄ／２となるため、トランジスタＭ２のゲート端子の電圧も約Ｖｄｄ／２となる。この電圧は、トランジスタＭ１，Ｍ２が飽和領域で動作するためのゲート端子の電圧の最低値Ｖｏｖ１＋Ｖｏｖ２＋Ｖｔｈ２よりも大きいため、出力電圧の動作範囲が狭くなる。 For example, when the amplifier circuit does not include the capacitive element C2, the output voltage of the inverter circuit Inv1 is directly applied to the gate terminal of the transistor M2. When the inverter circuit Inv1 has the configuration shown in FIG. 2, the operating point voltage of the inverter circuit Inv1 is about Vdd / 2, and the voltage at the gate terminal of the transistor M2 is also about Vdd / 2. Since this voltage is larger than the minimum value Vov1 + Vov2 + Vth2 of the voltage at the gate terminal for the transistors M1 and M2 to operate in the saturation region, the operating range of the output voltage is narrowed.
　これに対して、本実施形態によれば、容量素子Ｃ２により、インバータ回路Ｉｎｖ１の出力電圧とトランジスタＭ２のゲート電圧とを分離し、ゲート電圧を任意の値に設定することができる。すなわち、ゲート電圧を、最低電圧Ｖｏｖ１＋Ｖｏｖ２＋Ｖｔｈ２以上の範囲で、Ｖｄｄ／２より小さい電圧とすることができる。 On the other hand, according to the present embodiment, the output voltage of the inverter circuit Inv1 and the gate voltage of the transistor M2 can be separated by the capacitive element C2, and the gate voltage can be set to an arbitrary value. That is, the gate voltage can be set to a voltage smaller than Vdd / 2 within the range of the minimum voltage Vov1 + Vov2 + Vth2.
　これにより、出力電圧Ｖｏｕｔの動作範囲の下限電圧を低下させることができる。また、同様の理由で、増幅回路が容量素子Ｃ４を備えることにより、出力電圧Ｖｏｕｔの動作範囲の上限電圧を上昇させることができる。したがって、出力電圧Ｖｏｕｔの動作範囲を広くすることができる。 Thereby, the lower limit voltage of the operating range of the output voltage Vout can be lowered. For the same reason, the upper limit voltage of the operating range of the output voltage Vout can be increased by providing the capacitor C4 in the amplifier circuit. Therefore, the operating range of the output voltage Vout can be widened.
　なお、本実施形態において、インバータ回路Ｉｎｖ１０は、２段のカスコード構成を有するが、３段以上のカスコード構成とすることも可能である。 In the present embodiment, the inverter circuit Inv10 has a two-stage cascode configuration, but may have a three-stage or more cascode configuration.
（第２実施形態）
　次に、第２実施形態に係る増幅回路について、図４～図６を参照して説明する。図４は、本実施形態に係る増幅回路を示す図である。図４に示すように、本実施形態に係る増幅回路は、トランジスタＭ５と、スイッチＳ５と、トランジスタＭ６と、スイッチＳ６とを備える。トランジスタＭ５，Ｍ６は、インバータ回路Ｉｎｖ２０を構成している。他の構成は、第１実施形態に係る増幅回路と同様である。 (Second Embodiment)
Next, an amplifier circuit according to a second embodiment will be described with reference to FIGS. FIG. 4 is a diagram illustrating an amplifier circuit according to the present embodiment. As shown in FIG. 4, the amplifier circuit according to the present embodiment includes a transistor M5, a switch S5, a transistor M6, and a switch S6. The transistors M5 and M6 constitute an inverter circuit Inv20. Other configurations are the same as those of the amplifier circuit according to the first embodiment.
　トランジスタＭ５（第５トランジスタ）は、ＮＭＯＳトランジスタであり、ゲート端子（制御端子）をトランジスタＭ１のゲート端子（制御端子）に接続され、ソース端子を接地され、ドレイン端子（第１端子）をスイッチＳ５に接続されている。トランジスタＭ５は、ゲート端子から入力電圧Ｖｉｎを入力される。トランジスタＭ５のゲート端子は、インバータ回路Ｉｎｖ２０の入力端子となる。 The transistor M5 (fifth transistor) is an NMOS transistor, the gate terminal (control terminal) is connected to the gate terminal (control terminal) of the transistor M1, the source terminal is grounded, and the drain terminal (first terminal) is the switch S5. It is connected to the. The transistor M5 receives the input voltage Vin from the gate terminal. The gate terminal of the transistor M5 becomes an input terminal of the inverter circuit Inv20.
　スイッチＳ５（第５スイッチ）は、トランジスタＭ１のドレイン端子（第１端子）とトランジスタＭ５のドレイン端子（第１端子）との間に設けられ、これらの間を接続又は開放する。スイッチＳ５の開閉は制御信号φＢＳＴにより制御される。スイッチＳ５は、制御信号φＢＳＴがＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ５として、例えば、ＭＯＳトランジスタが用いられる。 The switch S5 (fifth switch) is provided between the drain terminal (first terminal) of the transistor M1 and the drain terminal (first terminal) of the transistor M5, and connects or opens between them. Opening and closing of the switch S5 is controlled by a control signal φ BST . The switch S5 is turned on (closed state) when the control signal φBST is High, and is turned off (open state) when the control signal φBST is Low. For example, a MOS transistor is used as the switch S5.
　トランジスタＭ６（第６トランジスタ）は、ＰＭＯＳトランジスタであり、ゲート端子（制御端子）をトランジスタＭ３のゲート端子（制御端子）に接続され、ソース端子を電源Ｖｄｄに接続され、ドレイン端子（第１端子）をスイッチＳ６に接続されている。トランジスタＭ６は、ゲート端子から入力電圧Ｖｉｎを入力される。トランジスタＭ６のゲート端子は、インバータ回路Ｉｎｖ２０の入力端子となる。 The transistor M6 (sixth transistor) is a PMOS transistor, the gate terminal (control terminal) is connected to the gate terminal (control terminal) of the transistor M3, the source terminal is connected to the power supply Vdd, and the drain terminal (first terminal). Is connected to the switch S6. The transistor M6 receives the input voltage Vin from the gate terminal. The gate terminal of the transistor M6 becomes an input terminal of the inverter circuit Inv20.
　スイッチＳ６（第６スイッチ）は、トランジスタＭ３のドレイン端子（第１端子）とトランジスタＭ６のドレイン端子（第１端子）との間に設けられ、これらの間を接続又は開放する。スイッチＳ６の開閉は制御信号φＢＳＴにより制御される。スイッチＳ６は、制御信号φＢＳＴがＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ６として、例えば、ＭＯＳトランジスタが用いられる。 The switch S6 (sixth switch) is provided between the drain terminal (first terminal) of the transistor M3 and the drain terminal (first terminal) of the transistor M6, and connects or opens between them. Opening and closing of the switch S6 is controlled by a control signal φ BST . The switch S6 is turned on (closed state) when the control signal φBST is High, and is turned off (open state) when the control signal φBST is Low. For example, a MOS transistor is used as the switch S6.
　ここで、図５は、図４の増幅回路を簡略化して示す図である。図５において、インバータ回路Ｉｎｖ１，２などの構成は省略されている。本実施形態に係る増幅回路は、図５に示すように、増幅動作を行うインバータ回路Ｉｎｖ１０に、インバータ回路Ｉｎｖ２０が並列に接続された構成となっている。 Here, FIG. 5 is a simplified diagram of the amplifier circuit of FIG. In FIG. 5, the configurations of the inverter circuits Inv1, 2 and the like are omitted. As shown in FIG. 5, the amplifier circuit according to this embodiment has a configuration in which an inverter circuit Inv20 is connected in parallel to an inverter circuit Inv10 that performs an amplification operation.
　このような構成により、インバータ回路Ｉｎｖ２０による電流の駆動が可能となるため、増幅回路の電流駆動能力を向上させることができる。また、追加するインバータ回路Ｉｎｖ２０がカスコード構成ではなく、２つのトランジスタＭ５，Ｍ６からなる単純な構成のため、トランジスタＭ５，Ｍ６のデバイスサイズを調整することにより、駆動電流の大きさを容易に調整することができる。 With such a configuration, current can be driven by the inverter circuit Inv20, so that the current drive capability of the amplifier circuit can be improved. In addition, since the added inverter circuit Inv20 is not a cascode configuration but a simple configuration including two transistors M5 and M6, the device size of the transistors M5 and M6 is adjusted to easily adjust the magnitude of the drive current. be able to.
　次に、本実施形態に係る増幅回路の動作について、図６を参照して説明する。図６は、本実施形態に係る増幅回路の動作を示すタイミングチャートと、タイミングチャートと対応した出力電圧Ｖｏｕｔを示す図である。図６において、実線は本実施形態に係る増幅回路の出力電圧Ｖｏｕｔを示しており、破線は第１実施形態に係る増幅回路の出力電圧Ｖｏｕｔを示している。 Next, the operation of the amplifier circuit according to this embodiment will be described with reference to FIG. FIG. 6 is a timing chart illustrating the operation of the amplifier circuit according to the present embodiment, and a diagram illustrating the output voltage Vout corresponding to the timing chart. In FIG. 6, the solid line indicates the output voltage Vout of the amplifier circuit according to this embodiment, and the broken line indicates the output voltage Vout of the amplifier circuit according to the first embodiment.
　図６に示すように、制御信号φＢＳＴは、制御信号φ１がＬｏｗになったタイミングでＨｉｇｈになり、所定時間後にＬｏｗになる。すなわち、スイッチＳ５，Ｓ６は、スイッチＳ１～Ｓ４がオフになったタイミングでオンになり、所定時間後にオフになる。スイッチＳ５，Ｓ６がオンの期間は、増幅フェーズの継続期間より短く設定される。 As shown in FIG. 6, the control signal φ BST becomes High when the control signal φ 1 becomes Low, and becomes Low after a predetermined time. That is, the switches S5 and S6 are turned on when the switches S1 to S4 are turned off, and are turned off after a predetermined time. The period during which the switches S5 and S6 are on is set shorter than the duration of the amplification phase.
　このような動作により、増幅フェーズの初期の所定時間に増幅回路の電流駆動能力が向上し、出力電圧Ｖｏｕｔが所望の利得で増幅されるまでの期間が短縮する。したがって、増幅動作を高速化することができる。 By such an operation, the current drive capability of the amplifier circuit is improved at a predetermined time in the initial stage of the amplification phase, and the period until the output voltage Vout is amplified with a desired gain is shortened. Therefore, the amplification operation can be speeded up.
（第３実施形態）
　次に、第３実施形態に係る増幅回路について、図７～図９を参照して説明する。図７は、本実施形態に係る増幅回路を示す図である。図７に示すように、本実施形態に係る増幅回路は、電圧源Ｖ３と、スイッチＳ７と、スイッチＳ８とを備える。他の構成は、第１実施形態に係る増幅回路と同様である。 (Third embodiment)
Next, an amplifier circuit according to a third embodiment will be described with reference to FIGS. FIG. 7 is a diagram illustrating an amplifier circuit according to the present embodiment. As shown in FIG. 7, the amplifier circuit according to the present embodiment includes a voltage source V3, a switch S7, and a switch S8. Other configurations are the same as those of the amplifier circuit according to the first embodiment.
　電圧源Ｖ３（第３電圧源）は、所定のバイアス電圧Ｖ３（第３電圧）を、トランジスタＭ１，Ｍ３のゲート端子（制御端子）に供給する定電圧源である。バイアス電圧Ｖ３は、トランジスタＭ１又はトランジスタＭ３がオフになるように設定される。電圧源Ｖ３として、例えば、グラウンドや電源Ｖｄｄを用いることができる。 The voltage source V3 (third voltage source) is a constant voltage source that supplies a predetermined bias voltage V3 (third voltage) to the gate terminals (control terminals) of the transistors M1 and M3. The bias voltage V3 is set so that the transistor M1 or the transistor M3 is turned off. As the voltage source V3, for example, a ground or a power supply Vdd can be used.
　スイッチＳ７は、トランジスタＭ１，Ｍ３のゲート端子（制御端子）と電圧源Ｖ３との間に設けられ、これらの間を接続又は開放する。スイッチＳ７の開閉は制御信号φ２により制御される。スイッチＳ７は、制御信号φ２がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ７として、例えば、ＭＯＳトランジスタが用いられる。 The switch S7 is provided between the gate terminals (control terminals) of the transistors M1 and M3 and the voltage source V3, and connects or opens between them. Opening and closing of the switch S7 is controlled by a control signal φ2. The switch S7 is turned on (closed state) when the control signal φ2 is High, and is turned off (open state) when the control signal φ2 is Low. For example, a MOS transistor is used as the switch S7.
　スイッチＳ８は、トランジスタＭ１，Ｍ３のゲート端子（制御端子）とトランジスタＭ２，Ｍ４のドレイン端子（第２端子）との間に設けられ、これらの間を接続又は開放する。スイッチＳ８の開閉は制御信号φ１により制御される。スイッチＳ８は、制御信号φ１がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ８として、例えば、ＭＯＳトランジスタが用いられる。 The switch S8 is provided between the gate terminals (control terminals) of the transistors M1 and M3 and the drain terminals (second terminals) of the transistors M2 and M4, and connects or opens between them. Opening and closing of the switch S8 is controlled by a control signal φ1. The switch S8 is turned on (closed state) when the control signal φ1 is High, and turned off (opened state) when the control signal φ1 is Low. For example, a MOS transistor is used as the switch S8.
　次に、本実施形態に係る増幅回路の動作について、図８及び図９を参照して説明する。図８は、本実施形態に係る増幅回路の動作を示すタイミングチャートである。図８に示すように、本実施形態に係る増幅回路は、記憶フェーズと、増幅フェーズと、遮断フェーズと、の３つの動作状態を有し、３つのフェーズが順次繰り返される。 Next, the operation of the amplifier circuit according to this embodiment will be described with reference to FIGS. FIG. 8 is a timing chart showing the operation of the amplifier circuit according to this embodiment. As shown in FIG. 8, the amplifier circuit according to the present embodiment has three operation states of a storage phase, an amplification phase, and a cutoff phase, and the three phases are sequentially repeated.
　記憶フェーズでは、制御信号φ１がＨｉｇｈかつ制御信号φ２がＬｏｗである。すなわち、スイッチＳ１～Ｓ４，Ｓ８がオンに、スイッチＳ７がオフになっている。 In the storage phase, the control signal φ1 is High and the control signal φ2 is Low. That is, the switches S1 to S4 and S8 are on and the switch S7 is off.
　スイッチＳ８がオンになることにより、インバータ回路Ｉｎｖ１０の出力端子電圧、すなわち、トランジスタＭ１，Ｍ４のドレイン端子の動作点電圧が、入力電圧Ｖｉｎの動作点電圧に設定される。 When the switch S8 is turned on, the output terminal voltage of the inverter circuit Inv10, that is, the operating point voltage of the drain terminals of the transistors M1 and M4 is set to the operating point voltage of the input voltage Vin.
　ここで、図９は、一般的なＣＭＯＳインバータ回路の入出力特性を示す図である。図９において、横軸は入力電圧Ｖｉｎであり、縦軸は出力電圧Ｖｏｕｔである。破線は、Ｖｉｎ＝Ｖｏｕｔとなる直線を示す。 Here, FIG. 9 is a diagram showing input / output characteristics of a general CMOS inverter circuit. In FIG. 9, the horizontal axis is the input voltage Vin, and the vertical axis is the output voltage Vout. A broken line indicates a straight line where Vin = Vout.
　一般に、ＣＭＯＳインバータ回路は、信号成分（交流成分）が動作点電圧に重畳された入力電圧Ｖｉｎを入力され、増幅された信号成分（交流成分）が動作点電圧に重畳された出力電圧Ｖｏｕｔを出力する。入力電圧Ｖｉｎの動作点電圧に対応する出力電圧Ｖｏｕｔの動作点電圧は、図９に示すような入出力特性によって決まり、出力電圧Ｖｏｕｔの動作範囲は、Ｖｉｎ＝Ｖｏｕｔのときに最大となる。 Generally, a CMOS inverter circuit receives an input voltage Vin in which a signal component (AC component) is superimposed on an operating point voltage, and outputs an output voltage Vout in which an amplified signal component (AC component) is superimposed on the operating point voltage. To do. The operating point voltage of the output voltage Vout corresponding to the operating point voltage of the input voltage Vin is determined by the input / output characteristics as shown in FIG. 9, and the operating range of the output voltage Vout becomes maximum when Vin = Vout.
　本実施形態の場合、記憶フェーズにおいてスイッチＳ８がオンになっているため、インバータ回路Ｉｎｖ１０の入出力端子間が短絡し、Ｖｉｎ＝Ｖｏｕｔとなっている。このため、インバータ回路Ｉｎｖ１０の出力端子の動作点電圧がＶｉｎ＝Ｖｏｕｔの時の動作点電圧に設定される。以降の増幅フェーズでは、当該記憶フェーズで設定された動作点電圧を基準に増幅動作が行われるため、出力電圧Ｖｏｕｔの動作範囲を最大化することができる。 In the case of this embodiment, since the switch S8 is turned on in the storage phase, the input / output terminals of the inverter circuit Inv10 are short-circuited, and Vin = Vout. Therefore, the operating point voltage at the output terminal of the inverter circuit Inv10 is set to the operating point voltage when Vin = Vout. In the subsequent amplification phase, the amplification operation is performed based on the operating point voltage set in the storage phase, so that the operation range of the output voltage Vout can be maximized.
　制御信号φ１がＬｏｗになり、記憶フェーズが終了すると、増幅フェーズが開始される。増幅フェーズでは、制御信号φ１がＬｏｗかつ制御信号φ２がＬｏｗである。すなわち、スイッチＳ１～Ｓ４，Ｓ７，Ｓ８がオフになっている。増幅フェーズにおける増幅動作は、第１実施形態と同様である。 When the control signal φ1 becomes Low and the storage phase is completed, the amplification phase is started. In the amplification phase, the control signal φ1 is low and the control signal φ2 is low. That is, the switches S1 to S4, S7, and S8 are turned off. The amplification operation in the amplification phase is the same as in the first embodiment.
　制御信号φ２がＨｉｇｈになり、増幅フェーズが終了すると、遮断フェーズが開始される。遮断フェーズでは、制御信号φ１がＬｏｗかつ制御信号φ２がＨｉｇｈである。すなわち、スイッチＳ１～Ｓ４，Ｓ７がオフに、スイッチＳ８がオンになっている。 When the control signal φ2 becomes High and the amplification phase is completed, the blocking phase is started. In the cutoff phase, the control signal φ1 is low and the control signal φ2 is high. That is, the switches S1 to S4 and S7 are turned off and the switch S8 is turned on.
　スイッチＳ８がオンになることにより、インバータ回路Ｉｎｖ１の入力端子に電圧Ｖ３が印加され、トランジスタＭ１又はトランジスタＭ３がオフになる。これにより、インバータ回路Ｉｎｖ１の貫通電流が遮断される。このような増幅回路を用いて積分回路を構成することにより、低消費電力な積分回路を構成することができる。積分回路については後述する。 When the switch S8 is turned on, the voltage V3 is applied to the input terminal of the inverter circuit Inv1, and the transistor M1 or the transistor M3 is turned off. Thereby, the through current of the inverter circuit Inv1 is cut off. By configuring an integration circuit using such an amplifier circuit, an integration circuit with low power consumption can be configured. The integration circuit will be described later.
　制御信号φ２がＬｏｗになり、遮断フェーズが終了した後、所定時間遅れて制御信号φ１がＨｉｇｈになり、再び記憶フェーズが開始される。制御信号φ１がＨｉｇｈになるタイミングを、制御信号φ２がＬｏｗになるタイミングより遅らせることにより、インバータ回路Ｉｎｖ１０の入出力が電圧源Ｖ３と短絡するのを防ぐことができる。 After the control signal φ2 becomes Low and the shut-off phase ends, the control signal φ1 becomes High after a predetermined time delay, and the storage phase is started again. By delaying the timing when the control signal φ1 becomes High from the timing when the control signal φ2 becomes Low, it is possible to prevent the input / output of the inverter circuit Inv10 from being short-circuited with the voltage source V3.
（第４実施形態）
　次に、第４実施形態に係る積分回路について、図１０及び図１１を参照して説明する。本実施形態に係る積分回路は、上述の第３実施形態に係る増幅回路を備える。図１０は、本実施形態に係る積分回路を示す図である。図１０に示すように、本実施形態に係る積分回路は、増幅回路と、スイッチＳ９と、スイッチＳ１０と、容量素子Ｃ５と、スイッチＳ１１と、スイッチＳ１２と、容量素子Ｃ６と、を備える。図１０において、増幅回路の構成は、インバータ回路Ｉｎｖ１０とスイッチＳ８と、を除いて省略されている。 (Fourth embodiment)
Next, an integration circuit according to the fourth embodiment will be described with reference to FIGS. The integrating circuit according to the present embodiment includes the amplifier circuit according to the third embodiment described above. FIG. 10 is a diagram illustrating an integration circuit according to the present embodiment. As shown in FIG. 10, the integrating circuit according to the present embodiment includes an amplifier circuit, a switch S9, a switch S10, a capacitive element C5, a switch S11, a switch S12, and a capacitive element C6. In FIG. 10, the configuration of the amplifier circuit is omitted except for the inverter circuit Inv10 and the switch S8.
　スイッチＳ９は、この積分回路による積分対象となる入力電流Ｉｉｎの電流源（図示省略）と、容量素子Ｃ５の一方の端子との間に設けられ、これらの間を接続又は開放する。スイッチＳ９の開閉は制御信号φ３により制御される。スイッチＳ９は、制御信号φ３がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ９として、例えば、ＭＯＳトランジスタが用いられる。 The switch S9 is provided between a current source (not shown) of the input current Iin to be integrated by the integration circuit and one terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S9 is controlled by a control signal φ3. The switch S9 is turned on (closed state) when the control signal φ3 is High, and is turned off (open state) when the control signal φ3 is Low. For example, a MOS transistor is used as the switch S9.
　スイッチＳ１０は、グラウンドと容量素子Ｃ５の一方の端子との間に設けられ、これらの間を接続又は開放する。スイッチＳ１０の開閉は制御信号φ４により制御される。スイッチＳ１０は、制御信号φ４がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ１０として、例えば、ＭＯＳトランジスタが用いられる。 The switch S10 is provided between the ground and one terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S10 is controlled by a control signal φ4. The switch S10 is turned on (closed state) when the control signal φ4 is High, and is turned off (open state) when the control signal φ4 is Low. For example, a MOS transistor is used as the switch S10.
　容量素子Ｃ５は、一方の端子をスイッチＳ９，Ｓ１０と接続され、他方の端子をスイッチＳ１１，Ｓ１２と接続されている。スイッチＳ９とスイッチＳ１１とがオンになると、容量素子Ｃ５は、一方の端子を電流源と接続され、他方の端子を接地され、入力電流Ｉｉｎに応じた電荷を蓄積する。スイッチＳ１０とスイッチＳ１２とがオンになると、容量素子Ｃ５は、一方の端子を接地され、他方の端子を増幅回路の入力端子と接続され、蓄積した電荷を容量素子Ｃ６に転送する。容量素子Ｃ５は、この積分回路の事前積分容量として機能する。 The capacitor element C5 has one terminal connected to the switches S9 and S10 and the other terminal connected to the switches S11 and S12. When the switch S9 and the switch S11 are turned on, the capacitor C5 has one terminal connected to the current source and the other terminal grounded, and accumulates electric charge according to the input current Iin. When the switch S10 and the switch S12 are turned on, the capacitor C5 has one terminal grounded, the other terminal connected to the input terminal of the amplifier circuit, and transfers the accumulated charge to the capacitor C6. The capacitive element C5 functions as a pre-integration capacitor of this integration circuit.
　スイッチＳ１１は、グラウンドと容量素子Ｃ５の他方の端子との間に設けられ、これらの間を接続又は開放する。スイッチＳ１１の開閉は制御信号φ３により制御される。スイッチＳ１１は、制御信号φ３がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ１１として、例えば、ＭＯＳトランジスタが用いられる。 The switch S11 is provided between the ground and the other terminal of the capacitive element C5, and connects or opens between them. Opening and closing of the switch S11 is controlled by a control signal φ3. The switch S11 is turned on (closed state) when the control signal φ3 is High, and is turned off (open state) when the control signal φ3 is Low. For example, a MOS transistor is used as the switch S11.
　スイッチＳ１２は、容量素子Ｃ５の他方の端子とインバータ回路Ｉｎｖ１０の入力端子との間に設けられ、これらの間を接続又は開放する。スイッチＳ１２の開閉は制御信号φ４により制御される。スイッチＳ１２は、制御信号φ４がＨｉｇｈのときにオン（閉状態）になり、Ｌｏｗのときにオフ（開状態）となる。スイッチＳ１２として、例えば、ＭＯＳトランジスタが用いられる。 The switch S12 is provided between the other terminal of the capacitive element C5 and the input terminal of the inverter circuit Inv10, and connects or opens between them. Opening and closing of the switch S12 is controlled by a control signal φ4. The switch S12 is turned on (closed state) when the control signal φ4 is High, and is turned off (open state) when the control signal φ4 is Low. For example, a MOS transistor is used as the switch S12.
　容量素子Ｃ６は、一方の端子を増幅回路の入力端子に接続され、他方の端子を増幅回路の出力端子に接続されている。すなわち、容量素子Ｃ６は、増幅回路と並列に接続されている。スイッチＳ１０とスイッチＳ１２とがオンになると、増幅回路の負帰還により容量素子Ｃ５に蓄積された電荷が転送され、転送された電荷が容量素子Ｃ６に蓄積される。容量素子Ｃ６の他方の端子の電圧が、この積分回路の出力電圧Ｖｏｕｔとなる。 The capacitor element C6 has one terminal connected to the input terminal of the amplifier circuit and the other terminal connected to the output terminal of the amplifier circuit. That is, the capacitive element C6 is connected in parallel with the amplifier circuit. When the switch S10 and the switch S12 are turned on, the charge accumulated in the capacitive element C5 is transferred by the negative feedback of the amplifier circuit, and the transferred charge is accumulated in the capacitive element C6. The voltage at the other terminal of the capacitive element C6 becomes the output voltage Vout of this integrating circuit.
　次に、本実施形態に係る積分回路の動作について、図１１を参照して説明する。図１１は、本実施形態に係る積分回路の動作を示すタイミングチャートである。図１１に示すように、この積分回路は、スイッチＳ９～Ｓ１２の動作に注目した場合、サンプリングフェーズ及び転送フェーズという２つの動作状態を有する。 Next, the operation of the integration circuit according to this embodiment will be described with reference to FIG. FIG. 11 is a timing chart showing the operation of the integrating circuit according to this embodiment. As shown in FIG. 11, this integration circuit has two operation states of a sampling phase and a transfer phase when attention is paid to the operation of the switches S9 to S12.
　サンプリングフェーズでは、制御信号φ３がＨｉｇｈかつ制御信号φ４がＬｏｗである。すなわち、スイッチＳ９，Ｓ１１がオンになり、スイッチＳ１０，Ｓ１２がオフになっている。したがって、サンプリングフェーズでは、入力電流Ｉｉｎに応じた電荷が容量素子Ｃ５に蓄積される。 In the sampling phase, the control signal φ3 is High and the control signal φ4 is Low. That is, the switches S9 and S11 are turned on and the switches S10 and S12 are turned off. Therefore, in the sampling phase, charges corresponding to the input current Iin are accumulated in the capacitive element C5.
　サンプリングフェーズにおいて、増幅回路及び容量素子Ｃ６は、容量素子Ｃ５と電気的に分離されており、増幅回路は上述の遮断フェーズ及び記憶フェーズの動作を行う。記憶フェーズでは、スイッチＳ１～Ｓ４，Ｓ８がオンになり、Ｖｉｎ＝Ｖｏｕｔのときの動作点電圧が記憶されるとともに、容量素子Ｃ６が短絡し、蓄積された電荷が放電される。記憶フェーズは、サンプリングフェーズ中の任意の期間に行われ、残りの期間には、遮断フェーズが行われる。これにより、積分回路の消費電力を低減させることができる。 In the sampling phase, the amplifier circuit and the capacitive element C6 are electrically separated from the capacitive element C5, and the amplifier circuit performs the above-described shut-off phase and storage phase operation. In the storage phase, the switches S1 to S4, S8 are turned on, the operating point voltage when Vin = Vout is stored, the capacitive element C6 is short-circuited, and the accumulated charge is discharged. The storage phase is performed during an arbitrary period during the sampling phase, and the blocking phase is performed during the remaining period. Thereby, the power consumption of the integration circuit can be reduced.
　制御信号φ３がＬｏｗになり、サンプリングフェーズが終了すると、所定時間遅れて制御信号φ４がＨｉｇｈになり、転送フェーズが開始される。制御信号φ４がＨｉｇｈになるタイミングを、制御信号φ３がＬｏｗになるタイミングより遅らせることにより、積分回路の短絡を防ぐことができる。 When the control signal φ3 becomes Low and the sampling phase ends, the control signal φ4 becomes High with a predetermined time delay, and the transfer phase is started. By delaying the timing when the control signal φ4 becomes High from the timing when the control signal φ3 becomes Low, it is possible to prevent a short circuit of the integrating circuit.
　転送フェーズでは、制御信号φ３がＬｏｗかつ制御信号φ４がＨｉｇｈである。すなわち、スイッチＳ１０，Ｓ１２がオンになり、スイッチＳ９，Ｓ１１がオフになっている。 In the transfer phase, the control signal φ3 is Low and the control signal φ4 is High. That is, the switches S10 and S12 are turned on and the switches S9 and S11 are turned off.
　転送フェーズにおいて、増幅回路は上述の増幅フェーズの動作を行い、入力電圧Ｖｉｎを所定の利得で増幅する。この際、負帰還の原理により、容量素子Ｃ５に蓄積された電荷が、容量素子Ｃ６に転送され、容量素子Ｃ６の他方の端子の電圧が出力電圧Ｖｏｕｔとして出力される。 In the transfer phase, the amplifier circuit performs the operation of the above-described amplification phase, and amplifies the input voltage Vin with a predetermined gain. At this time, due to the principle of negative feedback, the charge accumulated in the capacitive element C5 is transferred to the capacitive element C6, and the voltage at the other terminal of the capacitive element C6 is output as the output voltage Vout.
　容量素子Ｃ５，Ｃ６の容量をＣ５，Ｃ６とすると、容量素子Ｃ５に蓄積された電荷が全て容量素子Ｃ６に転送された場合、Ｖｏｕｔ＝（Ｃ５／Ｃ６）×Ｖｉｎとなる。一般に、オペアンプの駆動能力や容量に応じて決まる時定数をτとすると、出力電圧Ｖｏｕｔは以下の式で表される。
Ｖｏｕｔ（ｔ）＝（Ｃ５／Ｃ６）（１－ｅｘｐ（－１／τ））×Ｖｉｎ Assuming that the capacities of the capacitive elements C5 and C6 are C5 and C6, when all the charges accumulated in the capacitive element C5 are transferred to the capacitive element C6, Vout = (C5 / C6) × Vin. In general, when a time constant determined according to the driving capability and capacity of an operational amplifier is τ, the output voltage Vout is expressed by the following equation.
Vout (t) = (C5 / C6) (1-exp (−1 / τ)) × Vin
　すなわち、出力電圧Ｖｏｕｔは、時間の経過とともに（Ｃ５／Ｃ６）×Ｖｉｎに近づいていく。転送フェーズの継続時間は、Ｃ５、Ｃ６、τ、及び要求される積分精度に応じて決定される。 That is, the output voltage Vout approaches (C5 / C6) × Vin over time. The duration of the transfer phase is determined according to C5, C6, τ and the required integration accuracy.
　転送フェーズが終了し、制御信号φ４がＬｏｗになると、所定時間遅れて制御信号φ３がＨｉｇｈになり、再びサンプリングフェーズが開始される。制御信号φ３がＨｉｇｈになるタイミングを、制御信号φ４がＬｏｗになるタイミングより遅らせることにより、積分回路の短絡を防ぐことができる。 When the transfer phase ends and the control signal φ4 becomes low, the control signal φ3 becomes high after a predetermined time delay, and the sampling phase is started again. By delaying the timing when the control signal φ3 becomes High from the timing when the control signal φ4 becomes Low, it is possible to prevent a short circuit of the integrating circuit.
　以上説明した通り、本実施形態に係る積分回路は、サンプリング期間中の増幅回路の消費電力を抑制することができる。また、増幅回路が高い利得を有することから、精度よく積分動作を行うことができる。さらに、転送フェーズ中に電流源と積分回路とが電気的に分離されるため、転送フェーズ中に入力電流Ｉｉｎが入力された場合に生じる積分誤差の発生を防止することができる。 As described above, the integration circuit according to the present embodiment can suppress the power consumption of the amplifier circuit during the sampling period. Further, since the amplifier circuit has a high gain, the integration operation can be performed with high accuracy. Furthermore, since the current source and the integration circuit are electrically separated during the transfer phase, it is possible to prevent the occurrence of an integration error that occurs when the input current Iin is input during the transfer phase.
　なお、積分回路が第１実施形態及び第２実施形態に係る増幅回路を備える構成も可能である。積分回路が第２実施形態に係る増幅回路を備える場合、増幅回路の電流駆動能力が向上するため、時定数τが小さくなる。したがって、転送フェーズを短縮し、積分動作を高速化することができる。 Note that a configuration in which the integrating circuit includes the amplifier circuit according to the first and second embodiments is also possible. When the integration circuit includes the amplifier circuit according to the second embodiment, the current driving capability of the amplifier circuit is improved, so that the time constant τ is reduced. Therefore, the transfer phase can be shortened and the integration operation can be speeded up.
（第５実施形態）
　次に、第５実施形態に係るＡＤ変換器について、図１２及び図１３を参照して説明する。図１２は、本実施形態に係るＡＤ変換器を示す図である。図１２に示すように、本実施形態に係るＡＤ変換器は、複数のパイプラインステージを備えるパイプラインＡＤ変換器である。 (Fifth embodiment)
Next, an AD converter according to a fifth embodiment will be described with reference to FIGS. FIG. 12 is a diagram illustrating the AD converter according to the present embodiment. As shown in FIG. 12, the AD converter according to the present embodiment is a pipeline AD converter including a plurality of pipeline stages.
　図１３は、ＡＤ変換器のパイプラインステージの一例を示す図である。このパイプラインステージでは、１ビットのＡＤ変換が行われる。図１３に示すように、パイプラインステージは、第４実施形態に係る積分回路と、ＡＤ変換回路ＡＤＣと、ＤＡ変換回路ＤＡＣとを備える。 FIG. 13 is a diagram showing an example of the pipeline stage of the AD converter. In this pipeline stage, 1-bit AD conversion is performed. As shown in FIG. 13, the pipeline stage includes an integration circuit according to the fourth embodiment, an AD conversion circuit ADC, and a DA conversion circuit DAC.
　ＡＤ変換回路ＡＤＣは、入力電流Ｉｉｎに応じた入力電圧が参照電圧Ｖｒｅｆ以上の場合に１を出力し、参照電圧Ｖｒｅｆより小さい場合に０を出力する。これにより、１ビットのＡＤ変換が行われる。 The AD converter circuit ADC outputs 1 when the input voltage corresponding to the input current Iin is equal to or higher than the reference voltage Vref, and outputs 0 when it is lower than the reference voltage Vref. Thereby, 1-bit AD conversion is performed.
　ＤＡ変換回路ＤＡＣは、ＡＤ変換回路ＡＤＣの出力信号をＤＡ変換する。ＤＡ変換回路ＤＡＣは、ＡＤ変換回路ＡＤＣの出力信号が１の場合に参照電圧Ｖｒｅｆに応じた電流を出力し、０の場合には電流を出力しない。 The DA conversion circuit DAC DA converts the output signal of the AD conversion circuit ADC. The DA conversion circuit DAC outputs a current corresponding to the reference voltage Vref when the output signal of the AD conversion circuit ADC is 1, and does not output a current when the output signal is 0.
　このような構成により、１ビットのＡＤ変換が行われ、出力電圧Ｖｏｕｔは後段のパイプラインステージに入力される。ＡＤ変換器は、第４実施形態に係る積分回路を備えるため、低消費電力であるとともに、精度よくＡＤ変換を行うことができる。 With this configuration, 1-bit AD conversion is performed, and the output voltage Vout is input to the subsequent pipeline stage. Since the AD converter includes the integration circuit according to the fourth embodiment, the AD converter has low power consumption and can perform AD conversion with high accuracy.
　なお、このＡＤ変換器は、全差動の構成にしてもよいし、各パイプラインステージで複数ビットのＡＤ変換、或いは、１．５ビットなどの冗長ビットを有するＡＤ変換を行うように構成することも可能である。また、上述の各実施形態に係る増幅回路及び積分回路は、パイプラインＡＤ変換器以外の任意のＡＤ変換器に適用することができる。 The AD converter may be configured to be fully differential, or configured to perform AD conversion of a plurality of bits or AD conversion having redundant bits such as 1.5 bits at each pipeline stage. It is also possible. In addition, the amplifier circuit and the integration circuit according to each of the embodiments described above can be applied to any AD converter other than the pipeline AD converter.
　なお、本発明は上記各実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記各実施形態に開示されている複数の構成要素を適宜組み合わせることによって種々の発明を形成できる。また例えば、各実施形態に示される全構成要素からいくつかの構成要素を削除した構成も考えられる。さらに、異なる実施形態に記載した構成要素を適宜組み合わせてもよい。 Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.
Ｃ１～Ｃ６：容量素子、Ｓ１～Ｓ１２：スイッチ、Ｉｎｖ１，Ｉｎｖ２，Ｉｎｖ１０，Ｉｎｖ２０：インバータ回路、Ｖ１～Ｖ３：電圧源、φ１～φ４：制御信号、ＡＤＣ：ＡＤ変換回路、ＤＡＣ：ＤＡ変換回路 C1 to C6: Capacitance elements, S1 to S12: Switches, Inv1, Inv2, Inv10, Inv20: Inverter circuits, V1 to V3: Voltage sources, φ1 to φ4: Control signals, ADC: AD conversion circuit, DAC: DA conversion circuit

Claims (6)

  1. 　第１導電型の第１トランジスタと、
    　第１端子を前記第１トランジスタの第１端子に接続された第１導電型の第２トランジスタと、
    　入力端子を前記第１トランジスタの第１端子に接続され、出力端子を前記第２トランジスタの制御端子に接続された第１インバータ回路と、
    　前記第１トランジスタの第１端子と前記第１インバータ回路の入力端子との間に接続された第１容量素子と、
    　前記第２トランジスタの制御端子と前記第１インバータ回路の出力端子との間に接続された第２容量素子と、
    　前記第１インバータ回路の入力端子と出力端子とを接続する第１スイッチと、
    　所定の第１電圧を供給する第１電圧源と、
    　前記第１電圧源と前記第２トランジスタの制御端子とを接続する第２スイッチと、
    　制御端子を前記第１トランジスタの制御端子に接続された第２導電型の第３トランジスタと、
    　第１端子を前記第３トランジスタの第１端子に接続され、第２端子を前記第２トランジスタの第２端子に接続された第２導電型の第４トランジスタと、
    　入力端子を前記第３トランジスタの第１端子に接続され、出力端子を前記第４トランジスタの制御端子に接続された第２インバータ回路と、
    　前記第３トランジスタの第１端子と前記第２インバータ回路の入力端子との間に接続された第３容量素子と、
    　前記第４トランジスタの制御端子と前記第２インバータ回路の出力端子との間に接続された第４容量素子と、
    　前記第２インバータ回路の入力端子と出力端子とを接続する第３スイッチと、
    　所定の第２電圧を供給する第２電圧源と、
    　前記第２電圧源と前記第４トランジスタの制御端子とを接続する第４スイッチと、
    を備える増幅回路。     A first transistor of a first conductivity type;
    A second transistor of the first conductivity type having a first terminal connected to the first terminal of the first transistor;
    A first inverter circuit having an input terminal connected to a first terminal of the first transistor and an output terminal connected to a control terminal of the second transistor;
    A first capacitor connected between a first terminal of the first transistor and an input terminal of the first inverter circuit;
    A second capacitive element connected between a control terminal of the second transistor and an output terminal of the first inverter circuit;
    A first switch connecting an input terminal and an output terminal of the first inverter circuit;
    A first voltage source for supplying a predetermined first voltage;
    A second switch connecting the first voltage source and a control terminal of the second transistor;
    A third transistor of second conductivity type having a control terminal connected to the control terminal of the first transistor;
    A fourth transistor of a second conductivity type having a first terminal connected to a first terminal of the third transistor and a second terminal connected to a second terminal of the second transistor;
    A second inverter circuit having an input terminal connected to the first terminal of the third transistor and an output terminal connected to the control terminal of the fourth transistor;
    A third capacitive element connected between a first terminal of the third transistor and an input terminal of the second inverter circuit;
    A fourth capacitor connected between a control terminal of the fourth transistor and an output terminal of the second inverter circuit;
    A third switch for connecting an input terminal and an output terminal of the second inverter circuit;
    A second voltage source for supplying a predetermined second voltage;
    A fourth switch connecting the second voltage source and a control terminal of the fourth transistor;
    An amplifier circuit comprising:
  2. 　制御端子を前記第１トランジスタの制御端子に接続された第１導電型の第５トランジスタと、
    　前記第１トランジスタの第１端子と前記第５トランジスタの第１端子とを接続する第５スイッチと、
    　制御端子を前記第３トランジスタの制御端子に接続された第２導電型の第６トランジスタと、
    　前記第３トランジスタの第１端子と前記第６トランジスタの第１端子とを接続する第６スイッチと、
    を備える請求項１に記載の増幅回路。     A fifth transistor of the first conductivity type having a control terminal connected to the control terminal of the first transistor;
    A fifth switch connecting the first terminal of the first transistor and the first terminal of the fifth transistor;
    A second transistor of the second conductivity type having a control terminal connected to the control terminal of the third transistor;
    A sixth switch connecting the first terminal of the third transistor and the first terminal of the sixth transistor;
    An amplifying circuit according to claim 1.
  3. 　前記第１トランジスタ又は前記第２トランジスタをオフにする所定の第３電圧を供給する第３電圧源と、
    　前記第３電圧源と前記第１及び第３トランジスタの制御端子とを接続する第７スイッチと、
    を備える請求項１又は請求項２に記載の増幅回路。     A third voltage source for supplying a predetermined third voltage for turning off the first transistor or the second transistor;
    A seventh switch connecting the third voltage source and the control terminals of the first and third transistors;
    An amplifying circuit according to claim 1, comprising:
  4. 　前記第１トランジスタの制御端子及び前記第２トランジスタの制御端子の接続点と、前記第３トランジスタの第２端子及び前記第４トランジスタの第２端子の接続点と、を接続する第８スイッチを備える
    請求項１～３のいずれか１項に記載の増幅回路。     An eighth switch that connects a connection point between the control terminal of the first transistor and the control terminal of the second transistor and a connection point of the second terminal of the third transistor and the second terminal of the fourth transistor; The amplifier circuit according to any one of claims 1 to 3.
  5. 　請求項１～請求項４のいずれか１項に記載の増幅回路を備えた積分回路。 An integrating circuit comprising the amplifier circuit according to any one of claims 1 to 4.
  6. 　請求項５に記載の積分回路を備えるＡＤ変換器。 An AD converter comprising the integration circuit according to claim 5.
PCT/JP2015/061096 2014-05-09 2015-04-09 Amplifier circuit, integration circuit, and a/d converter WO2015170547A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206800A (en) * 1991-11-22 1993-08-13 Kawasaki Steel Corp Output circuit
JP2007243837A (en) * 2006-03-10 2007-09-20 Toshiba Corp Differential amplifier circuit
WO2007116378A2 (en) * 2006-04-12 2007-10-18 Nxp B.V. Electronic circuit
JP2009044391A (en) * 2007-08-08 2009-02-26 Digian Technology Inc Ad converter
JP2013526745A (en) * 2010-05-14 2013-06-24 ジニティクス カンパニー リミテッド Integration circuit combining an inverting integrator and a non-inverting integrator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206800A (en) * 1991-11-22 1993-08-13 Kawasaki Steel Corp Output circuit
JP2007243837A (en) * 2006-03-10 2007-09-20 Toshiba Corp Differential amplifier circuit
WO2007116378A2 (en) * 2006-04-12 2007-10-18 Nxp B.V. Electronic circuit
JP2009044391A (en) * 2007-08-08 2009-02-26 Digian Technology Inc Ad converter
JP2013526745A (en) * 2010-05-14 2013-06-24 ジニティクス カンパニー リミテッド Integration circuit combining an inverting integrator and a non-inverting integrator

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