CN102324928A - A kind of frequency calibration circuit of active RC filter - Google Patents
A kind of frequency calibration circuit of active RC filter Download PDFInfo
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- CN102324928A CN102324928A CN201110133841A CN201110133841A CN102324928A CN 102324928 A CN102324928 A CN 102324928A CN 201110133841 A CN201110133841 A CN 201110133841A CN 201110133841 A CN201110133841 A CN 201110133841A CN 102324928 A CN102324928 A CN 102324928A
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Abstract
The invention discloses a kind of frequency calibration circuit of active RC filter, comprise the capacitor array control signal feedback circuit module of capacitor array charge-discharge circuit module, voltage window comparison circuit module and the numerical portion of analog part.Wherein the capacitor array in the capacitor array charge-discharge circuit module duplicates the capacitor array in the active RC filter fully; Through its voltage that obtains; Compare with the voltage in the voltage window comparison circuit module of expecting, the signal that again voltage ratio is obtained outputs to capacitor array control signal feedback circuit module, through its processing to voltage comparison signal; Form feedback with analog part; Obtain the control signal of capacitor array, and then remove to adjust the capacitance of the capacitor array in the active RC filter, realize adjustment the response of active RC filter main body channel frequency.Its advantage is: overcome the variation of the frequency response that the active RC filter circuit causes owing to the influence of technology, supply voltage and temperature etc.
Description
Technical field
The present invention relates to a kind of frequency calibration circuit, particularly a kind of frequency calibration circuit of active RC filter.
Background technology
In the existing active RC filter,, therefore be necessary the cut-off frequency of active RC filter is calibrated, to obtain needed cut-off frequency because electric capacity can cause the drift of the cut-off frequency of active RC filter along with the variation of technology, temperature etc. on the sheet.
Summary of the invention
The objective of the invention is to realize a kind of frequency automatic calibration circuit that can be applicable to active RC filter.
In order to realize goal of the invention of the present invention, realize through adopting following technical scheme:
A kind of frequency calibration circuit of active RC filter; The capacitor array control signal feedback circuit module that comprises capacitor array charge-discharge circuit module, voltage window comparison circuit module and the numerical portion of analog part; Wherein the capacitor array in the capacitor array charge-discharge circuit module duplicates the capacitor array in the active RC filter fully, and it holds the variation of capacitor array appearance value in the value trace active RC filter, and both have identical control signal; The voltage that obtains through capacitor array charge-discharge circuit module; Compare with the voltage in the voltage window comparison circuit module of expecting, the signal that again voltage ratio is obtained outputs to capacitor array control signal feedback circuit module, through the processing of numerical portion to voltage comparison signal; Form feedback with analog part; Obtain the control signal of capacitor array, and then remove to adjust the capacitance of the capacitor array in the active RC filter, realize adjustment the response of active RC filter main body channel frequency.
Said capacitor array charge-discharge circuit module comprises capacitor array, transmission gate, tail current source It, nmos switch pipe M1 and nmos switch pipe M2, and wherein the anode of capacitor array connects power line, and has appearance value control word S < 3 >, S < 2 >, S < 1 >, S < 0 >; Tail current source It negativing ending grounding; Nmos switch pipe M1 links to each other with the source electrode of nmos switch pipe M2; And link to each other with the anode of tail current source It; The grid of nmos switch pipe M1 connects the reverse clock SW2_B of clock signal SW2; Its drain electrode connects power line, and the grid of nmos switch pipe M2 connects clock signal SW2, and drain electrode connects the negative terminal Vcap of said capacitor array; The conducting of transmission gate or turn-off by clock signal SW1 with and reverse clock SW1_B decide, its anode connects power line, negative terminal connects the negative terminal Vcap of said capacitor array.
Said voltage window comparison circuit module comprises the first comparator C OMP1, the second comparator C OMP2, the first d type flip flop DFF1, the second d type flip flop DFF2; Wherein the first comparator C OMP1 has positive input terminal and negative input end; Positive input terminal links to each other with the negative terminal Vcap of said capacitor array, and said negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP2 has positive input terminal and negative input end, and positive input terminal links to each other with the negative terminal Vcap of said capacitor array, and said negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF1 has data input pin and input end of clock, and input end of clock links to each other with the output of the first comparator C OMP1, and input end of clock is the reverse clock SW3_B of clock signal SW3; The second d type flip flop DFF2 has data input pin and input end of clock, and input end of clock links to each other with the output of the second comparator C OMP2, and input end of clock is the reverse clock SW3_B of clock signal SW3.
Said capacitor array control signal feedback circuit module comprises together or door XNOR and digital coding; A wherein same or door XNOR has anode input and negative terminal input; The anode input receives the Q end output signal VH_OUT from the first d type flip flop DFF1, and the negative terminal input receives the Q end output signal VL_OUT from the second d type flip flop DFF2; Digital coding has three input ports; Wherein the VIN port receives the Q end output signal VH_OUT from the first d type flip flop DFF1; The LOCK port is connected to together or the output of an XNOR; SW4 is a clock end, and output S < 3 >, S < 2 >, S < 1 >, the S < 0>of digital coding part deliver to the corresponding control word end of capacitor array.
Beneficial effect of the present invention is: overcome the variation of the frequency response that the active RC filter circuit causes owing to the influence of technology, supply voltage and temperature etc., the drift of cut-off frequency that has prevented active RC filter is to the influence of circuit.
Description of drawings
Fig. 1 is the frequency calibration electrical block diagram of active RC filter of the present invention;
Fig. 2 is the frequency calibration circuit clock distribution map of active RC filter of the present invention;
Fig. 3 is the frequency calibration circuit working flow chart of active RC filter of the present invention.
Wherein, the symbol description of Fig. 1 to Fig. 3 is following:
1, capacitor array charge-discharge circuit module, 11, capacitor array, 12, transmission gate, 13, nmos switch pipe M1; 14, nmos switch pipe M2,15, tail current source It, 2, voltage window comparison circuit module, 21, the first comparator C OMP1; 22, the second comparator C OMP2,23, the first d type flip flop DFF1,24, the second d type flip flop DFF2; 3, capacitor array control signal feedback circuit module, 31, digital coding, 32, with or door XNOR.
Embodiment
As shown in Figure 1, be the frequency calibration electrical block diagram of active RC filter of the present invention.Its structure comprises the capacitor array control signal feedback circuit module 3 of capacitor array charge-discharge circuit module 1, voltage window comparison circuit module 2 and the numerical portion of analog part.
Said capacitor array charge-discharge circuit module 1 comprises capacitor array 11, transmission gate 12, nmos switch pipe M113, nmos switch pipe M214, tail current source It15; Wherein the anode of capacitor array 11 connects power line, and has appearance value control word S < 3 >, S < 2 >, S < 1 >, S < 0 >; Tail current source It15 negativing ending grounding; Nmos switch pipe M113 links to each other with the source electrode of nmos switch pipe M214; And link to each other with the anode of tail current source It15; The grid of nmos switch pipe M113 connects the reverse clock SW2_B of clock signal SW2; Its drain electrode connects power line, and the grid of nmos switch pipe M214 connects clock signal SW2, and drain electrode connects the negative terminal Vcap of said capacitor array 11; The conducting of transmission gate 12 or turn-off by clock signal SW1 with and reverse clock SW1_B decide, its anode connects power line, negative terminal connects the negative terminal Vcap of said capacitor array 11.
Said voltage window comparison circuit module comprises the first comparator C OMP121, the second comparator C OMP222, the first d type flip flop DFF123, the second d type flip flop DFF224; Wherein the first comparator C OMP121 has positive input terminal and negative input end; Positive input terminal links to each other with the negative terminal Vcap of said capacitor array 11, and said negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP222 has positive input terminal and negative input end, and positive input terminal links to each other with the negative terminal Vcap of said capacitor array 11, and said negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF123 has data input pin and input end of clock, and input end of clock links to each other with the output of the first comparator C OMP121, and input end of clock is the reverse clock SW3_B of clock signal SW3; The second d type flip flop DFF224 has data input pin and input end of clock, and input end of clock links to each other with the output of the second comparator C OMP222, and input end of clock is the reverse clock SW3_B of clock signal SW3.
Said capacitor array control signal feedback circuit module 3 comprises together or door XNOR32 and digital coding 31; A wherein same or door XNOR32 has anode input and negative terminal input; The anode input receives the Q end output signal VH_OUT from the first d type flip flop DFF123, and the negative terminal input receives the Q end output signal VL_OUT from the second d type flip flop DFF224; Digital coding 31 has three input ports; Wherein the VIN port receives the Q end output signal VH_OUT from the first d type flip flop DFF123; The LOCK port is connected to together or the output of an XNOR32; SW4 is a clock end, and the output S < 3>of digital coding 31 parts, S < 2 >, S < 1 >, S < 0>deliver to the corresponding control word end of capacitor array 11.
As shown in Figure 2, be the frequency calibration circuit clock distribution map of active RC filter of the present invention.SW1/SW1_B among Fig. 1, SW2/SW2_B, SW3/SW3_B, SW4/SW4_B are one group of clock signal, and its phase place situation is as shown in Figure 2, and their duty ratios separately are respectively: 1/5,2/5,2/5,1/5.Clock SW3 falls behind clock SW2, and delaying time is D1, and clock SW4 falls behind clock SW3, and delaying time is D2.Clock SW1/SW1_B is the replacement clock, and the control transmission door stored voltage value on is moved power supply potential on electric capacity at SW1=1 in the cycle.SW2=1 is the charging clock cycle, when SW2=1, and nmos switch pipe M2 conducting, the voltage Vcap of capacitor array lower end discharges through M2 and tail current source It; Until the SW3=1 clock cycle, at this moment, SW2_B=1; Nmos switch pipe M1 conducting, tail current It flows into power line VDDA through M1, and capacitor array lower end Vcap is no longer discharge then; And this moment SW1=0, SW1_B=1, transmission gate ends; Capacitor array lower end Vcap voltage no longer includes discharge path, therefore remains unchanged by capacitor array lower end, back Vcap voltage in the SW2=1 cycle, is used for comparing with reference voltage window.The setting of reference voltage window is corresponding with needed capacitor array value, promptly in this reference voltage window, and the cut-off frequency value that expression capacitor array integral capacitor value can corresponding active-RC filter.At the SW3 rising edge, d type flip flop is gathered the output information of prime comparator, and the output of d type flip flop will be delivered to digital circuit and partly carry out judgment processing, finally provide corresponding action.
As shown in Figure 3, be the frequency calibration circuit working flow chart of active RC filter of the present invention.Concrete working condition is following; After the SW2=1 cycle ends; When if capacitor array lower end Vcap magnitude of voltage is between reference voltage window VREF_L and the VREF_H; Capacitor array can remain unchanged, and expression capacitor array appearance value at this moment can access the active-RC filter cutoff frequency that needs, and the automatic frequency calibration can be accomplished.And if capacitor array lower end Vcap magnitude of voltage is not between reference voltage window VREF_L and VREF_H the time; Numerical portion then need be according to the output signal of analog part; Judge to do which kind of adjustment to capacitor array, so that the Vcap magnitude of voltage can remain in the reference voltage window under current flow-route and temperature.
The output VH_OUT of analog part and VL_OUT warp are same or obtain the LOCK signal behind the door, deliver in the digital module with the VH_OUT signal.Three kinds of situation of the relatively existence of aforementioned Vcap magnitude of voltage and reference voltage window VREF_L and VREF_H; Be Vcap < VREF_L < VREF_H; VREF_L Vcap VREF_H, < < Vcap makes the combination of value of VH_OUT and LOCK three kinds of situation also can occur to VREF_H to VREF_L; Be VH_OUT=L, LOCK=H; VH_OUT=L, LOCK=L and VH_OUT=H, LOCK=H.Digital module is analyzed the value of VH_OUT and LOCK at the rising edge of clock signal SW4; When LOCK=L, can think that the appearance value of capacitor array this moment can access the suitable filters cut-off frequency, i.e. the control word S of capacitor array < 3 >; S < 2 >; S < 1 >, S < 0>can keep current state, and the automatic frequency calibration of filter is accomplished.And when LOCK=H, have two kinds of situation, and need be to the control word S < 3>of capacitor array, S < 2 >, S < 1 >, S < 0>adjusts.VH_OUT=L means capacitor array owing to the influence that receives flow-route and temperature drift etc. shows less appearance value, when clock signal SW4 rising edge, increases the control word S < 3>of a capacitor array; S < 2 >, S < 1 >, S < 0>improves its appearance value, through cycle criterion; Final Vcap magnitude of voltage gets in the reference voltage window, and LOCK=L can stop to increase S < 3 >, S < 2>this moment; S < 1 >, S < 0 >, the automatic frequency calibration of expression filter this moment is accomplished.And during another kind of situation VH_OUT=H, mean that capacitor array owing to the influence that receives flow-route and temperature drift etc. shows bigger appearance value, when rising edge appears in clock signal SW4, reduces the control word S < 3>of a capacitor array; S < 2 >, S < 1 >, S < 0>reduces its appearance value, through cycle criterion; Final Vcap magnitude of voltage gets in the reference voltage window, and LOCK=L can stop to reduce S < 3 >, S < 2>this moment; S < 1 >, S < 0 >, the automatic frequency calibration of expression filter this moment is accomplished.
Claims (4)
1. the frequency calibration circuit of an active RC filter; It is characterized in that: the capacitor array control signal feedback circuit module (3) that comprises capacitor array charge-discharge circuit module (1), voltage window comparison circuit module (2) and the numerical portion of analog part; Wherein the capacitor array (11) in the capacitor array charge-discharge circuit module (1) duplicates the capacitor array in the active RC filter fully; It holds the variation of capacitor array appearance value in the value trace active RC filter; And both have identical control signal, and the voltage that obtains through capacitor array charge-discharge circuit module (1) compares with voltage in the voltage window comparison circuit module (2) of expectation; The signal that again voltage ratio is obtained outputs to capacitor array control signal feedback circuit module (3); Capacitor array control signal feedback circuit module (3) through numerical portion is to the processing of voltage comparison signal, forms feedback with the capacitor array charge-discharge circuit module (1) of analog part, obtains the control signal of capacitor array (11); And then remove to adjust the capacitance of the capacitor array in the active RC filter, realize adjustment to the response of active RC filter main body channel frequency.
2. the frequency calibration circuit of active RC filter as claimed in claim 1; It is characterized in that: said capacitor array charge-discharge circuit module (1) comprises capacitor array (11), transmission gate (12), nmos switch pipe M1 (13), nmos switch pipe M2 (14), tail current source It (15); Wherein the anode of capacitor array (11) connects power line, and has appearance value control word S < 3 >, S < 2 >, S < 1 >, S < 0 >; Tail current source It (15) negativing ending grounding; Nmos switch pipe M1 (13) links to each other with the source electrode of nmos switch pipe M2 (14); And link to each other with the anode of tail current source It (15); The grid of nmos switch pipe M1 (13) connects the reverse clock SW2_B of clock signal SW2; Its drain electrode connects power line, and the grid of nmos switch pipe M2 (14) connects clock signal SW2, and drain electrode connects the negative terminal Vcap of said capacitor array (11); The conducting of transmission gate (12) or turn-off by clock signal SW1 with and reverse clock SW1_B decide, its anode connects power line, negative terminal connects the negative terminal Vcap of said capacitor array (11).
3. the frequency calibration circuit of active RC filter as claimed in claim 1; It is characterized in that: said voltage window comparison circuit module (2) comprises the first comparator C OMP1 (21), the second comparator C OMP2 (22), the first d type flip flop DFF1 (23), the second d type flip flop DFF2 (24); Wherein the first comparator C OMP1 (21) has positive input terminal and negative input end; Positive input terminal links to each other with the negative terminal Vcap of said capacitor array (11), and said negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP2 (22) has positive input terminal and negative input end, and positive input terminal links to each other with the negative terminal Vcap of said capacitor array (11), and said negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF1 (23) has data input pin and input end of clock, and input end of clock links to each other with the output of the first comparator C OMP1 (21), and input end of clock is the reverse clock SW3_B of clock signal SW3; The second d type flip flop DFF2 (24) has data input pin and input end of clock, and input end of clock links to each other with the output of the second comparator C OMP2 (22), and input end of clock is the reverse clock SW3_B of clock signal SW3.
4. the frequency calibration circuit of active RC filter as claimed in claim 1; It is characterized in that: said capacitor array control signal feedback circuit module (3) comprises together or door XNOR (32) and digital coding (31); A wherein same or door XNOR (32) has anode input and negative terminal input; The anode input receives the Q end output signal VH_OUT from the first d type flip flop DFF1 (23), and the negative terminal input receives the Q end output signal VL_OUT from the second d type flip flop DFF2 (24); Digital coding (31) has three input ports; Wherein the VIN port receives the Q end output signal VH_OUT from the first d type flip flop DFF1 (23); The LOCK port is connected to together or the output of door XNOR (32); SW4 is a clock end, and output S < 3 >, S < 2 >, S < 1 >, the S < 0>of digital coding (31) part deliver to the corresponding control word end of capacitor array (11).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110133841 CN102324928B (en) | 2011-05-23 | 2011-05-23 | Frequency calibration circuit of active RC (Resistor-Capacitor) filter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110133841 CN102324928B (en) | 2011-05-23 | 2011-05-23 | Frequency calibration circuit of active RC (Resistor-Capacitor) filter |
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| CN102324928A true CN102324928A (en) | 2012-01-18 |
| CN102324928B CN102324928B (en) | 2013-04-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201110133841 Active CN102324928B (en) | 2011-05-23 | 2011-05-23 | Frequency calibration circuit of active RC (Resistor-Capacitor) filter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916679A (en) * | 2012-10-19 | 2013-02-06 | 钜泉光电科技(上海)股份有限公司 | Circuit for supplying precise low-frequency clock signal, and control method for circuit |
| CN102983836A (en) * | 2012-11-27 | 2013-03-20 | 重庆西南集成电路设计有限责任公司 | Automatic frequency tuning circuit of active resistance-capacitance (RC) filter |
| CN103078630A (en) * | 2012-12-20 | 2013-05-01 | 香港应用科技研究院有限公司 | Bandwidth calibration method for filter |
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| US6239654B1 (en) * | 1999-05-28 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | Filter circuit |
| US20030216129A1 (en) * | 2002-05-16 | 2003-11-20 | Waleed Khalil | Self-calibrating circuit for wireless transmitter or the like |
| CN1551501A (en) * | 2003-05-12 | 2004-12-01 | 因芬尼昂技术股份公司 | Apparatus and method for calibrating resistance/ capacitor filter circuit |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN202068398U (en) * | 2011-05-23 | 2011-12-07 | 中科芯集成电路股份有限公司 | Frequency calibration circuit of active RC filter |
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2011
- 2011-05-23 CN CN 201110133841 patent/CN102324928B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239654B1 (en) * | 1999-05-28 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | Filter circuit |
| US20030216129A1 (en) * | 2002-05-16 | 2003-11-20 | Waleed Khalil | Self-calibrating circuit for wireless transmitter or the like |
| CN1551501A (en) * | 2003-05-12 | 2004-12-01 | 因芬尼昂技术股份公司 | Apparatus and method for calibrating resistance/ capacitor filter circuit |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN202068398U (en) * | 2011-05-23 | 2011-12-07 | 中科芯集成电路股份有限公司 | Frequency calibration circuit of active RC filter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916679A (en) * | 2012-10-19 | 2013-02-06 | 钜泉光电科技(上海)股份有限公司 | Circuit for supplying precise low-frequency clock signal, and control method for circuit |
| CN102916679B (en) * | 2012-10-19 | 2016-03-16 | 钜泉光电科技(上海)股份有限公司 | Circuit and the control method thereof of accurate low-frequency clock signal are provided |
| CN102983836A (en) * | 2012-11-27 | 2013-03-20 | 重庆西南集成电路设计有限责任公司 | Automatic frequency tuning circuit of active resistance-capacitance (RC) filter |
| CN102983836B (en) * | 2012-11-27 | 2015-11-18 | 重庆西南集成电路设计有限责任公司 | Active RC filter automatic frequency tuning circuit |
| CN103078630A (en) * | 2012-12-20 | 2013-05-01 | 香港应用科技研究院有限公司 | Bandwidth calibration method for filter |
| CN103078630B (en) * | 2012-12-20 | 2015-09-30 | 香港应用科技研究院有限公司 | For the bandwidth calibration of filter |
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Address after: 2 / F, building 9, plot 04-6 (100 didui Road), Liyuan Development Zone, Binhu District, Wuxi City, Jiangsu Province Patentee after: ZHONGKEXIN INTEGRATED CIRCUIT Co.,Ltd. Address before: 214072 Jiangsu province Wuxi City Liyuan Development Zone, Road No. 100 building 9 layer 2 Patentee before: CHINA KEY SYSTEM & INTEGRATED CIRCUIT Co.,Ltd. |