CN203798886U - Current sampling circuit - Google Patents

Abstract

The utility model provides a current sampling circuit which comprises a pin Ps, a shunt power NMOS tube, a sampling power NMOS tube M2, a sampling power NMOS tube M3, a sampling power NMOS tube M4, and a sampling resistor R2. The shunt power NMOS tube and the drain electrodes of the sampling power NMOS tube M2, M3 and M4 are all connected with the pin Ps. The shunt power NMOS tube and the grid electrodes of the sampling power NMOS tube M2 are connected with a power supply Vin. One end of the sampling resistor Rs is connected with the source electrodes of the sampling power NMOS tube M2, M3 and M4, and the other end of the sampling resistor Rs is grounded. The current sampling circuit is characterized in that the conduction states of the sampling power NMOS tube M3 and M4 are respectively controlled by a signal; the signals for controlling the conduction states of the sampling power NMOS tube M3 are provided by external input pins A and B; and the current sampling circuit can achieve a plurality of current limiting values and is simple in mode.

Description

A kind of current sampling circuit

Technical field

The utility model relates to integrated circuit fields, particularly for the current sampling circuit of Analogous Integrated Electronic Circuits.

Background technology

In integrated circuit, especially in Analogous Integrated Electronic Circuits, in order to detect large electric current, because the requirement of power consumption etc. is detecting after need to sampling to electric current.And the sampling of electric current can only have a kind of sampled value conventionally.

Mainly there is following defect in such scheme:

Because can only sample a kind of electric current, so the current value that it can detect only has one, be not easy to realize multiple current value and obtain sample detecting.

Summary of the invention

In order to solve current detection circuit a kind of current value of can only sampling, be not easy to realize multiple current value the shortcoming that obtains sample detecting.

Solution of the present utility model is as follows:

A kind of current sampling circuit, comprise that pin Ps, shunting power NMOS pipe (3), sampled power NMOS manage M2(4), M3(5), M4(6), sampling resistor Rs(8), shunting power NMOS pipe (3) and sampled power NMOS pipe M2(4), M3(5) and drain electrode adapter pin Ps M4(6), shunting power NMOS pipe (3) and sampled power NMOS manage M2(4) grid meet power supply Vin, sampling resistor Rs(8) a termination sampling pipe NMOS pipe M2(4), M3(5), M4(6) source electrode, other end ground connection.Sampled power NMOS manages M3(5) and conducting state M4(6) controlled respectively by signal, described control sampled power NMOS pipe M3(5) and M4(6) signal of conducting state by outside input pin A(7) and pin B(8) provide.

The present invention has the following advantages:

Current sampling circuit signal A and B input the first pin (7) by outside and the second pin (8) provides.Realize multiple cut-off current, mode is simple.

Brief description of the drawings

Fig. 1 is schematic diagram of the present invention.

Embodiment

As shown in Figure 1, M1, M2, M3, M4 are power NMOS pipe.M1 is isocon, and M2, M3, M4 are sampling pipe.Wherein M1, M2 grid meet power supply Vin, and therefore M1, M2 are in normally on, are fixing access state.Signal A, the B that the conducting state of M3, M4 provides by outside input pin 7 and 8 connects respectively the grid of M3, M4 and controls.M3, M4 conducting in the time that the signal of M3, M4 is high level, M3, M4 cut-off during for low level.Control according to actual needs the conducting state of M3, M4.Pin Ps connects the drain electrode of power MOS pipe M1, M2, M3, M4.The source electrode of sampling resistor Rs mono-termination sampling pipe M2, M3, M4, other end ground connection.

In Ps, there is electric current input.Because M1, M2 are in normally on, electric current in Ps flows through M1, M2, the electric current that flows through M1 directly arrives ground, and the electric current that flows through M2 flows into sampling resistor Rs, when the M3 controlling when outside input pin 7 and 8 and/or M4 conducting, electric current in Ps flows through after them, flows into sampling resistor Rs.The electric current flowing into is exported to subsequent conditioning circuit after sampling resistor Rs produces voltage Vs.

Wherein M1, M2, M3, M4 are with certain size setting.Set ratio value is determined according to the concrete condition of circuit.By the control of 7 and 8 couples of M3 of outside input pin and/or M4 conducting state, can obtain different sample rate currents by M2, M3, M4, therefore also just can produce different voltage Vs by sampling resistor Rs.M2, M3, M4 conducting more, the electric current of sampling is larger, and the sampled voltage Vs of generation is also just larger.When maximum, be M2, M3, the whole conductings of M4.The sample rate current corresponding sampled value of 1(signal A, B different conditions that specifically sees the following form).

Claims (1)

1. a current sampling circuit, comprise pin Ps, shunting power NMOS manages (3), sampled power NMOS manages M2(4), M3(5), M4(6), sampling resistor Rs(8), shunting power NMOS pipe (3) and sampled power NMOS pipe M2(4), M3(5) pin Ps is taken in drain electrode and M4(6), shunting power NMOS pipe (3) and sampled power NMOS manage M2(4) grid meet power supply Vin, sampling resistor Rs(8) a termination sampled power NMOS pipe M2(4), M3(5), M4(6) source electrode, other end ground connection, it is characterized in that: sampled power NMOS manages M3(5) and conducting state M4(6) controlled respectively by signal, described control sampled power NMOS pipe M3(5) and M4(6) signal of conducting state by outside input pin A(7) and pin B(8) provide.