CN104422867A - Chip device and testing method thereof - Google Patents
Chip device and testing method thereof Download PDFInfo
- Publication number
- CN104422867A CN104422867A CN201310395193.0A CN201310395193A CN104422867A CN 104422867 A CN104422867 A CN 104422867A CN 201310395193 A CN201310395193 A CN 201310395193A CN 104422867 A CN104422867 A CN 104422867A
- Authority
- CN
- China
- Prior art keywords
- pmos
- circuit
- ended
- nmos tube
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a chip device and a testing method thereof. N modules and n single-ended to differential conversion circuits are built in the chip device, each module corresponds to one single-ended to differential conversion circuit, each module is connected with a differential port of the single-ended to differential conversion circuit corresponding to the module, and single-ended ports of each single-ended to differential conversion circuit are respectively connected with pins of the chip device. Since the n modules and the n single-ended to differential conversion circuits are built in the chip device and each module is connected with the differential port of one corresponding single-ended to differential conversion circuit, differential signals output by the modules are converted into single-ended signals or the single-ended signals are converted into differential signals and then are output to the modules; since the single-ended ports of the single-ended to differential conversion circuits are connected with the pins of the chip device, each module only needs to occupy one pin, n modules only need to occupy n pins and precious pin resources are saved.
Description
Technical field
The present invention relates to field tests, especially relate to a kind of chip device and method of testing thereof.
Background technology
In the prior art, generally include multiple module in chip device, each module, when input or outputting analog signal, uses differential signal.Therefore, each module needs two pins taking chip device, for inputing or outputing differential signal.Obviously, if a chip device has n module, then n module will take at least 2n pin.Visible, the pin number that the modules of prior art chips device takies is more, thus causes the waste of valuable pin resource.
Summary of the invention
The technical matters that the present invention solves is to provide a kind of chip device and method of testing thereof, realizes reducing the pin number that module takies chip device, thus saves valuable pin resource.
For this reason, the technical scheme of technical solution problem of the present invention is:
The invention provides a kind of chip device, described chip device is built-in with n module and n single-ended and differential conversion circuit, each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively; Wherein, described n be more than or equal to 1 natural number.
Preferably, described chip device is also built-in with m on-off circuit, and the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit; In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits; Wherein, described m is the natural number being less than or equal to n.
Preferably, described m equals n, and the single-ended single-end port with differential conversion circuit of described n is connected to the same pin of described chip device respectively by n described on-off circuit.
Preferably, described chip device is also provided with control pin, and the control signal that described control pin receives is for controlling the conducting of described on-off circuit with closed.
Preferably, on-off circuit described in any one comprises the first NMOS tube and the first PMOS;
The drain electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, as the input port of this on-off circuit; The source electrode of described first NMOS tube is connected, as the output port of this on-off circuit with the source electrode of a described PMOS;
If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects output port that to be this single-ended with differential conversion circuit, the input port of this on-off circuit connects this single-end port; If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects input port that to be this single-ended with differential conversion circuit, the output port of this on-off circuit connects this single-end port.
Preferably, described single-ended be that single-ended transfer difference circuit or difference turn single-end circuit with differential conversion circuit.
Preferably, difference described in any one turns single-end circuit and comprises: the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS, the 7th PMOS, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the first resistance;
The source electrode of the second PMOS, the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and the source electrode of the 5th PMOS are connected to supply voltage, the grid of the second PMOS and the grid of the second NMOS tube are connected to the cut-in voltage that this difference turns single-end circuit, the drain electrode of the second PMOS, the drain and gate of the 3rd PMOS, the grid of the 4th PMOS, the grid of the 5th PMOS and the drain electrode of the second NMOS tube are connected to bias voltage, the drain electrode of the 4th PMOS connects the source electrode of the 6th PMOS and the source electrode of the 7th PMOS, the drain electrode of the 6th PMOS connects the drain and gate of the 3rd NMOS tube, and the 4th grid of NMOS tube, the drain electrode of the 7th PMOS connects the drain electrode of the 4th NMOS tube and the grid of the 5th NMOS tube, the grid of the 5th NMOS tube connects the drain electrode of the 5th NMOS tube and the drain electrode of the 5th PMOS by the first resistance, the source electrode of the 5th NMOS tube, the source electrode of the 4th NMOS tube, the source electrode of the 3rd NMOS tube, the source electrode of the second NMOS tube is connected to ground voltage, the drain electrode of described 5th PMOS turns the output port of single-end circuit as this difference, the grid of the 6th PMOS and the grid of the 7th PMOS turn the input port of single-end circuit as this difference.
Preferably, described in any one, single-ended transfer difference circuit comprises: the 8th PMOS, the 9th PMOS, the tenth PMOS, the 11 PMOS, the 12 PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance and electric capacity;
The source electrode of the 8th PMOS, the source electrode of the 9th PMOS and the source electrode of the tenth PMOS are connected to supply voltage, the drain electrode of the 8th PMOS, the grid of the 9th PMOS and drain electrode, the first end of the 3rd resistance and the grid of the tenth PMOS are connected to bias voltage, second end of the 3rd resistance connects the first end of the 5th resistance and the source electrode of the 6th NMOS tube, the drain electrode of the 6th NMOS tube connects the first end of the 4th resistance and the first end of the second resistance, second end of the second resistance is connected to the first end of described electric capacity and the grid of the 12 PMOS, second end of the 4th resistance connects the first end of the 6th resistance and the grid of the 11 PMOS, the grid of the 6th NMOS tube, the grid of the 8th PMOS, the grid of the 7th NMOS tube, the grid of the 8th NMOS tube and the grid of the 9th NMOS tube are connected to the cut-in voltage of this single-ended transfer difference circuit, second end of the 5th resistance connects the drain electrode of the 7th NMOS tube, the source electrode of the 7th NMOS tube, the source electrode of the 8th NMOS tube, the source electrode of the 9th NMOS tube and the second end of described electric capacity are connected to ground voltage, the drain electrode of the tenth PMOS is connected to the source electrode of the 11 PMOS and the source electrode of the 12 PMOS, the drain electrode of the 11 PMOS connects the drain electrode of the 8th NMOS tube, the drain electrode of the 12 PMOS connects the drain electrode of the 9th NMOS tube, second end of described 6th resistance is the input port of this single-ended transfer difference circuit, and the drain electrode of described 11 PMOS and the drain electrode of described 12 PMOS are the output port of this single-ended transfer difference circuit.
Present invention also offers a kind of chip device method of testing, described chip device is built-in with n module and n single-ended and differential conversion circuit, each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively; Wherein, described n be more than or equal to 1 natural number;
There is in a described n module at least one module to be tested; Described method comprises: the output signal of testing the pin of module to be tested corresponding to the module of output module, and to the pin input test signal of module to be tested corresponding to the module of load module;
Pin corresponding to module is for this module is by the single-ended pin be connected with differential conversion circuit.
Preferably, described chip device is also built-in with m on-off circuit, and the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit; In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits; Wherein, described m is the natural number being less than or equal to n;
Also comprise before described method:
Each on-off circuit corresponding to module to be tested is set to conducting state, and each on-off circuit corresponding to other modules except module to be tested is set to off-state;
On-off circuit corresponding to module is for this module is by the single-ended on-off circuit be connected with differential conversion circuit.
Known by technique scheme, n module and n single-ended and differential conversion circuit is built-in with at chip device in the present invention, the difference port of the single-ended and differential conversion circuit that each model calling one is corresponding, therefore the differential signal that described module exports converted to single-ended signal or export described module to after converting single-ended signal to differential signal, the single-ended pin being connected chip device with the single-end port of differential conversion circuit, visible, each module only need take a pin, therefore n module only need take n pin, need to take 2n pin compared to the module of n in prior art, decrease the pin number taking chip device, thus save valuable pin resource.
Accompanying drawing explanation
Circuit when Fig. 1 is test chip device of the prior art connects;
Fig. 2 is the concrete structure figure of the first embodiment of chip device provided by the invention;
Fig. 3 is the concrete structure figure of the second embodiment of chip device provided by the invention;
Fig. 4 is the preferred concrete structure figure of one of the second embodiment of chip device provided by the invention;
Fig. 5 is the concrete structure figure of a kind of on-off circuit provided by the invention;
Fig. 6 is the concrete structure figure that a kind of difference provided by the invention turns single-end circuit;
Fig. 7 is the concrete structure figure that another kind of difference provided by the invention turns single-end circuit;
Fig. 8 is the concrete structure figure of a kind of single-ended transfer difference circuit provided by the invention;
Fig. 9 is the concrete structure figure of another kind of single-ended transfer difference circuit provided by the invention;
Figure 10 is the schematic flow sheet of the specific embodiment of chip device method of testing provided by the invention.
Embodiment
In the prior art, generally include multiple module in chip device, each module, when input or outputting analog signal, uses differential signal.Therefore, each module needs two pins taking chip device, for inputing or outputing differential signal.Obviously, if a chip device has n module, then n module will take at least 2n pin.In fact, in some cases, need differential signal to be converted to single-ended signal and use.Such as, when test chip device, a lot of testing apparatus is single-ended test port, such as signal generator and oscillograph, after now just needing that single-ended chip or single-ended transfer difference chip are turned to the external difference of chip device, then connecting test equipment.As shown in Figure 1, when module (such as module 2) is for load module, the single-ended signal of output is changed into differential signal through single-ended transfer difference chip by signal generator, and this differential signal exports load module to by the pin of two on chip device (such as pin 3 and pin 4).When module (such as module 1) is for output module, the differential signal that module exports exports difference to by the pin of two on chip device (such as pin 1 and pin 2) and turns single-ended chip, this differential signal turns single-ended chip through difference and changes into single-ended signal, tests this single-ended signal by oscillograph.Visible, the number of pins that the modules of prior art chips device takies is more, and pin resource is normally more valuable; And due to the external difference of chip device and single-ended conversion chip, therefore more complicated will be operated.
And in embodiments of the present invention, provide a kind of chip device and method of testing thereof, realize reducing the pin number that module takies chip device, thus save valuable pin resource, simultaneously when testing this chip without the need to external difference and single-ended conversion chip, thus minimizing Operating Complexity.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the embodiment of the present invention below in conjunction with accompanying drawing.
Refer to Fig. 2, the invention provides the first embodiment of chip device, in the present embodiment, described chip device is built-in with n module and n single-ended and differential conversion circuit.As shown in Figure 2, n module be respectively module 1, module 2, module 3, module 4 ..., module n, n single-ended be respectively with differential conversion circuit single-ended with differential conversion circuit 1, single-ended with differential conversion circuit 2, single-ended with differential conversion circuit 3, single-ended with differential conversion circuit 4 ..., single-ended with differential conversion circuit n.Wherein, described n be more than or equal to 1 natural number.That is, chip device is at least built-in with 1 module.
Each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively.
Described single-ended and differential conversion circuit is used for the conversion between single-ended signal and differential signal, is specially single-ended transfer difference circuit or difference turns single-end circuit.When module is load module, when namely needing to this module input signal, the corresponding single-ended transfer difference circuit of this module, when module is output module, namely during this module output signal, the corresponding difference of this module turns single-end circuit.In fig. 2, module 1 is corresponding single-ended with differential conversion circuit 1, and module 2 is corresponding single-ended with differential conversion circuit 2, the like, module n is corresponding single-ended with differential conversion circuit n.
The difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module.Therefore, module 1 connects difference port that is single-ended and differential conversion circuit 1, and module 2 connects difference port that is single-ended and differential conversion circuit 2, the like, module n connects difference port that is single-ended and differential conversion circuit n.
Each single-ended pin being connected described chip device with the single-end port of difference channel respectively.As shown in Figure 2, be single-endedly connected pin 1 with the single-end port of differential conversion circuit 1, be single-endedly connected pin 2 with the single-end port of differential conversion circuit 2, the like, be single-endedly connected pin n with the single-end port of differential conversion circuit n.
It should be noted that, each pin in pin 1 to pin n may be input pin, also may be output pin, determined by the single-ended module be connected with differential conversion circuit by pin, if this module is load module, the pin that then load module correspondence connects is input pin, if this module is output module, then the pin that output module correspondence connects is output pin.
Known by technique scheme, n module and n single-ended and differential conversion circuit is built-in with at chip device in the present embodiment, the difference port of the single-ended and differential conversion circuit that each model calling one is corresponding, therefore the differential signal that described module exports converted to single-ended signal or export described module to after converting single-ended signal to differential signal, the single-ended pin being connected chip device with the single-end port of differential conversion circuit, visible, each module only need take a pin, therefore n module only need take n pin, need to take 2n pin compared to the module of n in prior art, decrease the pin number taking chip device, thus save valuable pin resource.
Meanwhile, also without the need to the external difference of chip device and single-ended conversion chip, thus reduce Operating Complexity.
Refer to Fig. 3, the invention provides the second embodiment of chip device, in the present embodiment, described chip device is built-in with n module and n single-ended and differential conversion circuit.As shown in Figure 3, n module be respectively module 1, module 2, module 3, module 4 ..., module n, n single-ended be respectively with differential conversion circuit single-ended with differential conversion circuit 1, single-ended with differential conversion circuit 2, single-ended with differential conversion circuit 3, single-ended with differential conversion circuit 4 ..., single-ended with differential conversion circuit n.Wherein, described n be more than or equal to 1 natural number.That is, chip device is at least built-in with 1 module.
Each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module.Each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively.
Described chip device is also built-in with m on-off circuit, therefore, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively described, specifically comprise two kinds of situations, a kind of situation is, the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit, another kind of situation is, except the m be connected with m on-off circuit is individual single-ended with other each the single-ended pin being connected described chip device with difference rotation circuit respectively except differential conversion circuit.As shown in Figure 3, module 1 connects difference port that is single-ended and differential conversion circuit 1, single-endedly be connected to pin 1 with the single-end port of differential conversion circuit 1 by on-off circuit 1, module 2 connects difference port that is single-ended and differential conversion circuit 2, is single-endedly also connected to pin 1 with the single-end port of differential conversion circuit 2 by on-off circuit 2.Module n connects the difference port of single-ended and differential conversion circuit n, is single-endedly connected pin j with the single-end port of differential conversion circuit n.Wherein, described m is the natural number being less than or equal to n.
In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits.Single-endedly same pin can be connected to respectively by an on-off circuit with differential conversion circuit because at built-in n the on-off circuit of chip device in the present embodiment, therefore, two or more.So in the present embodiment, the pin of each connecting valve circuit, is at least connected with two described on-off circuits.As shown in Figure 3, pin 1 is connected with on-off circuit 1 and on-off circuit 2, and pin 2 is connected with on-off circuit 3 and on-off circuit 4.
In the present embodiment, because each pin of connecting valve circuit is at least connected to two modules by two on-off circuits, therefore, at least two modules only need take a pin, and the pin number j that n module takies is less than n.Therefore, compared to the embodiment in Fig. 2, in the present embodiment, further reduce pin number, save valuable pin resource.
It should be noted that, in the present embodiment, an on-off circuit can connect multiple pin, then the module that this on-off circuit correspondence connects can use multiple pin.
In the present embodiment, in order to make the quantity of pin minimum, can in chip device a built-in n on-off circuit, namely described m equals n, then as shown in Figure 4, the single-ended single-end port with differential conversion circuit of described n is connected to the same pin of described chip device respectively by n described on-off circuit.Now, n module only need take a pin.Maximizedly reduce pin resource.
In the present embodiment, when wanting to use a certain module, only need control should the on-off circuit conducting of module, all the other all on-off circuits disconnect.Therefore, described chip device is also provided with control pin, and the control signal that described control pin receives is for controlling conducting and the disconnection of described on-off circuit.Described control signal is specially and controls on-off circuit conducting corresponding to test module, and controls the control signal that on-off circuit corresponding to other modules except described test module disconnect.
The invention provides a kind of concrete structure of on-off circuit below.In the present embodiment, any one on-off circuit can adopt this structure.As shown in Figure 5, on-off circuit described in any one comprises the first NMOS tube N1 and the first PMOS P1.
The drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS P1, as the input port of this on-off circuit, the source electrode of described first NMOS tube N1 is connected, as the output port of this on-off circuit with the source electrode of a described PMOS P1.The grid of the first NMOS tube N1 and the grid of a PMOS P1 are the control end of this on-off circuit, are in conducting state or off-state for control N1 and P1 simultaneously, thus realize the state that is turned on or off controlling this on-off circuit.
Because NMOS tube can only output low level, PMOS can only export high level, and therefore, the form of this NMOS tube in parallel and PMOS ensure that on-off circuit can export high level, also can output low level.
If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects output port that to be this single-ended with differential conversion circuit, the input port of this on-off circuit connects this single-end port, and the output port of this on-off circuit connects the pin of described chip device; If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects input port that to be this single-ended with differential conversion circuit, the output port of this on-off circuit connects this single-end port, and the input port of this on-off circuit connects the pin of described chip device.Illustrate, if when the on-off circuit in Fig. 31 adopts the structure shown in Fig. 5, if it is single-ended when being output port with the single ended interfaces of differential conversion circuit 1 that on-off circuit 1 connects, that is now module 1 is output module, single-ended with differential conversion module 1 for difference turns single-ended block, now the first NMOS tube N1 is connected single-ended with differential conversion circuit 1 with the drain electrode of the first PMOS P1, and the first NMOS tube N1 is connected pin 1 with the source electrode of the first PMOS P1.If when the on-off circuit in Fig. 32 adopts the structure shown in Fig. 5, if it is single-ended when being input port with the single ended interfaces of differential conversion circuit 2 that on-off circuit 2 connects, that is now module 2 is load module, single-ended is single-ended transfer difference module with differential conversion module 2, now the first NMOS tube N1 is connected single-ended with differential conversion circuit 2 with the source electrode of the first PMOS P1, and the first NMOS tube N1 is connected pin 1 with the drain electrode of the first PMOS P1.
It should be noted that, except the structure shown in Fig. 5, on-off circuit can also take other structures, as long as can realize on-off action, the present invention does not limit this.
In the present invention, single-ended is that single-ended transfer difference circuit or difference turn single-end circuit with differential conversion circuit.The present invention below provides a kind of single-ended transfer difference circuit and difference to turn the concrete structure of single-end circuit respectively, the single-ended structure that all can adopt with differential conversion circuit below of any one in any embodiment in the present invention.
As shown in Figure 6, any one difference turns single-end circuit and can comprise: the second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P7, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and the first resistance R1.
The source electrode of the second PMOS P2, the source electrode of the 3rd PMOS P3, the source electrode of the 4th PMOS P4 and the source electrode of the 5th PMOS P5 are connected to supply voltage VDD, and the grid of the second PMOS P2 and the grid of the second NMOS tube N2 are connected to the cut-in voltage that this difference turns single-end circuit.Whether in running order for controlling whole difference if turning the state of single-end circuit for this cut-in voltage.Particularly, when this cut-in voltage is high level, it is in running order that whole difference turns single-end circuit.
The grid of the drain electrode of the second PMOS P2, the drain and gate of the 3rd PMOS P3, the 4th PMOS P4, the grid of the 5th PMOS P5 and the drain electrode of the second NMOS tube N2 are connected to bias voltage VBP.This bias voltage VBP makes the 3rd PMOS P3, the 4th PMOS P4 and the 5th PMOS P5 work in saturation region.
The drain electrode of the 4th PMOS P4 connects the source electrode of the 6th PMOS P6 and the source electrode of the 7th PMOS P7, the drain electrode of the 6th PMOS P6 connects the drain and gate of the 3rd NMOS tube N3, and the 4th grid of NMOS tube N4, the drain electrode of the 7th PMOS P7 connects the drain electrode of the 4th NMOS tube N4 and the grid of the 5th NMOS tube N5, the grid of the 5th NMOS tube N5 also connects the drain electrode of the 5th NMOS tube N5 and the drain electrode of the 5th PMOS P5 by the first resistance R1, the source electrode of the 5th NMOS tube N5, the source electrode of the 4th NMOS tube N4, the source electrode of the 3rd NMOS tube N3, the source electrode of the second NMOS tube N2 is connected to ground voltage VSS.
Turn in single-end circuit in this difference, the drain electrode of the 5th PMOS P5 turns the output port of single-end circuit, i.e. Single-end output as this difference.The grid of the 6th PMOS P6 and the grid of the 7th PMOS P7 turn the input port of single-end circuit as this difference, namely Differential Input 1 and Differential Input 2.
As shown in Figure 7, this difference turns single-end circuit and can also comprise the 7th resistance R7, the 8th resistance R8 and the 9th resistance R9.9th resistance R9 is positioned at the common node of the drain electrode of the second PMOS P2 and the drain electrode of the 3rd PMOS P3, and between the drain electrode of the second NMOS tube N2.The first end of the 7th resistance R7 connects the source electrode of the 6th PMOS P6, the first end of the 8th resistance R8 connects the drain-source pole of the 7th PMOS P7, after second end of the 7th resistance R7 is connected with second end of the 8th resistance R8, be connected with the drain electrode of the 4th PMOS P4.
As shown in Figure 8, described in any one, single-ended transfer difference circuit can comprise: the 8th PMOS P8, the 9th PMOS P9, the tenth PMOS P10, the 11 PMOS P11, the 12 PMOS P12, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and electric capacity C.
The source electrode of the source electrode of the 8th PMOS P8, the source electrode of the 9th PMOS P9 and the tenth PMOS P10 is connected to supply voltage VDD, and the drain electrode of the 8th PMOS P8, the grid of the 9th PMOS P9 and drain electrode, the first end of the 3rd resistance R3 and the grid of the tenth PMOS P10 are connected to bias voltage VBP.This bias voltage VBP makes the 9th PMOS P9 and the tenth PMOS P10 work in saturation region.
Second end of the 3rd resistance R3 connects the first end of the 5th resistance R5 and the source electrode of the 6th NMOS, the drain electrode of the 6th NMOS tube N6 connects the first end of the 4th resistance R4 and the first end of the second resistance R2, second end of the second resistance R2 is connected to the first end of described electric capacity C and the grid of the 12 PMOS P12, second end of the 4th resistance R4 connects the first end of the 6th resistance R6 and the grid of the 11 PMOS P11, the grid of the 6th NMOS tube N6, the grid of the 8th PMOS P8, the grid of the 7th NMOS tube N7, the grid of the 8th NMOS tube N8 and the grid of the 9th NMOS tube N9 are connected to the cut-in voltage of this single-ended transfer difference circuit.Whether this cut-in voltage is in running order for the state controlling whole single-ended transfer difference circuit.Particularly, when this cut-in voltage is high level, whole single-ended transfer difference circuit is in running order.
Second end of the 5th resistance R5 connects the drain electrode of the 7th NMOS tube N7, the source electrode of the 7th NMOS tube N7, the source electrode of the 8th NMOS tube N8, the source electrode of the 9th NMOS tube N9 and second end of described electric capacity C are connected to ground voltage VSS, the drain electrode of the tenth PMOS P10 is connected to the source electrode of the 11 PMOS P11 and the source electrode of the 12 PMOS P12, the drain electrode of the 11 PMOS P11 connects the drain electrode of the 8th NMOS tube N8, the drain electrode of the 12 PMOS P12 connects the drain electrode of the 9th NMOS tube N9.
In this single-ended transfer difference circuit, second end of the 6th resistance R6 is the input port of this single-ended transfer difference circuit, i.e. single ended input, the drain electrode of described 11 PMOS P11 and the drain electrode of described 12 PMOS P12 are the output port of this single-ended transfer difference circuit, namely Differential Input 1 and Differential Input 2.
As shown in Figure 9, this difference turns single-end circuit and can also comprise the tenth resistance R10, the 11 resistance R11, the 12 resistance R12 and the 13 resistance R13.
The first end of the tenth resistance R10 is connected with the source electrode of the 11 PMOS P11, the first end of the 11 resistance R11 is connected with the source electrode of the 12 PMOS P12, after second end of the tenth resistance R10 is connected with second end of the 11 resistance R11, be connected with the drain electrode of the tenth PMOS P10.12 resistance R12 is connected between the 11 PMOS P11 and the 8th NMOS tube N8, and the 13 resistance R13 is connected between the 12 PMOS P12 and the 9th NMOS tube N9.Node between 11 PMOS P11 and the 12 resistance R12, and the node between the 12 PMOS P12 and the 13 resistance R13 is output port.
Present invention also offers chip device method of testing, for testing chip device provided by the invention.The equipment that the testing apparatus used when testing is single port, such as oscillograph, signal generator etc.Elaborate below.
Present invention also offers the specific embodiment of chip device method of testing, described method is used for the chip device in the embodiment shown in test pattern 2.Particularly, described chip device is built-in with n module and n single-ended and differential conversion circuit, each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively; Wherein, described n be more than or equal to 1 natural number.
There is in a described n module at least one module to be tested.That is, the one or more modules in n module are tested.These modules to be tested can be load modules, also can be output modules.
In the present embodiment, described method comprises:
S101: the output signal of testing the pin of module to be tested corresponding to the module of output module.
S102: to the pin input test signal of module to be tested corresponding to the module of load module.
Pin corresponding to module is for this module is by the single-ended pin be connected with differential conversion circuit.
Wherein, the execution sequence of step S101 and step S102 not circumscribed.Can perform simultaneously, also can perform sequentially.If module to be tested is output module, then perform S101, if module to be tested is load module, then perform S102.
Step S101 can be tested by oscillograph when testing, and in step S102, test signal can be exported by signal generator.
Preferably, can also test the chip device of the embodiment shown in Fig. 3 further.Now, described chip device is also built-in with m on-off circuit, and the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit; In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits; Wherein, described m is the natural number being less than or equal to n.
Then also comprise before step S101:
Each on-off circuit corresponding to module to be tested is set to conducting state, and each on-off circuit corresponding to other modules except module to be tested is set to off-state.
On-off circuit corresponding to module is for this module is by the single-ended on-off circuit be connected with differential conversion circuit.
Chip device method of testing provided by the invention may be used for the embodiment to arbitrary chip device provided by the invention.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a chip device, it is characterized in that, described chip device is built-in with n module and n single-ended and differential conversion circuit, each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively; Wherein, described n be more than or equal to 1 natural number.
2. device according to claim 1, is characterized in that, described chip device is also built-in with m on-off circuit, and the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit; In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits; Wherein, described m is the natural number being less than or equal to n.
3. device according to claim 2, is characterized in that, described m equals n, and the single-ended single-end port with differential conversion circuit of described n is connected to the same pin of described chip device respectively by n described on-off circuit.
4. the device according to Claims 2 or 3, described chip device is also provided with control pin, and the control signal that described control pin receives is for controlling the conducting of described on-off circuit with closed.
5. the device according to Claims 2 or 3, is characterized in that, on-off circuit described in any one comprises the first NMOS tube and the first PMOS;
The drain electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, as the input port of this on-off circuit; The source electrode of described first NMOS tube is connected, as the output port of this on-off circuit with the source electrode of a described PMOS;
If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects output port that to be this single-ended with differential conversion circuit, the input port of this on-off circuit connects this single-end port; If during the single-ended and single-end port of differential conversion circuit that this on-off circuit the connects input port that to be this single-ended with differential conversion circuit, the output port of this on-off circuit connects this single-end port.
6. device according to claim 1, is characterized in that, described single-ended be that single-ended transfer difference circuit or difference turn single-end circuit with differential conversion circuit.
7. circuit according to claim 6, it is characterized in that, difference described in any one turns single-end circuit and comprises: the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS, the 7th PMOS, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the first resistance;
The source electrode of the second PMOS, the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and the source electrode of the 5th PMOS are connected to supply voltage, the grid of the second PMOS and the grid of the second NMOS tube are connected to the cut-in voltage that this difference turns single-end circuit, the drain electrode of the second PMOS, the drain and gate of the 3rd PMOS, the grid of the 4th PMOS, the grid of the 5th PMOS and the drain electrode of the second NMOS tube are connected to bias voltage, the drain electrode of the 4th PMOS connects the source electrode of the 6th PMOS and the source electrode of the 7th PMOS, the drain electrode of the 6th PMOS connects the drain and gate of the 3rd NMOS tube, and the 4th grid of NMOS tube, the drain electrode of the 7th PMOS connects the drain electrode of the 4th NMOS tube and the grid of the 5th NMOS tube, the grid of the 5th NMOS tube connects the drain electrode of the 5th NMOS tube and the drain electrode of the 5th PMOS by the first resistance, the source electrode of the 5th NMOS tube, the source electrode of the 4th NMOS tube, the source electrode of the 3rd NMOS tube, the source electrode of the second NMOS tube is connected to ground voltage, the drain electrode of described 5th PMOS turns the output port of single-end circuit as this difference, the grid of the 6th PMOS and the grid of the 7th PMOS turn the input port of single-end circuit as this difference.
8. circuit according to claim 6, it is characterized in that, described in any one, single-ended transfer difference circuit comprises: the 8th PMOS, the 9th PMOS, the tenth PMOS, the 11 PMOS, the 12 PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance and electric capacity;
The source electrode of the 8th PMOS, the source electrode of the 9th PMOS and the source electrode of the tenth PMOS are connected to supply voltage, the drain electrode of the 8th PMOS, the grid of the 9th PMOS and drain electrode, the first end of the 3rd resistance and the grid of the tenth PMOS are connected to bias voltage, second end of the 3rd resistance connects the first end of the 5th resistance and the source electrode of the 6th NMOS tube, the drain electrode of the 6th NMOS tube connects the first end of the 4th resistance and the first end of the second resistance, second end of the second resistance is connected to the first end of described electric capacity and the grid of the 12 PMOS, second end of the 4th resistance connects the first end of the 6th resistance and the grid of the 11 PMOS, the grid of the 6th NMOS tube, the grid of the 8th PMOS, the grid of the 7th NMOS tube, the grid of the 8th NMOS tube and the grid of the 9th NMOS tube are connected to the cut-in voltage of this single-ended transfer difference circuit, second end of the 5th resistance connects the drain electrode of the 7th NMOS tube, the source electrode of the 7th NMOS tube, the source electrode of the 8th NMOS tube, the source electrode of the 9th NMOS tube and the second end of described electric capacity are connected to ground voltage, the drain electrode of the tenth PMOS is connected to the source electrode of the 11 PMOS and the source electrode of the 12 PMOS, the drain electrode of the 11 PMOS connects the drain electrode of the 8th NMOS tube, the drain electrode of the 12 PMOS connects the drain electrode of the 9th NMOS tube, second end of described 6th resistance is the input port of this single-ended transfer difference circuit, and the drain electrode of described 11 PMOS and the drain electrode of described 12 PMOS are the output port of this single-ended transfer difference circuit.
9. a chip device method of testing, it is characterized in that, described chip device is built-in with n module and n single-ended and differential conversion circuit, each described module is a corresponding described single-ended and differential conversion circuit respectively, the difference port of the single-ended and differential conversion circuit that each described model calling is corresponding with this module, each single-ended pin being connected described chip device with the single-end port of differential conversion circuit respectively; Wherein, described n be more than or equal to 1 natural number;
There is in a described n module at least one module to be tested; Described method comprises: the output signal of testing the pin of module to be tested corresponding to the module of output module, and to the pin input test signal of module to be tested corresponding to the module of load module;
Pin corresponding to module is for this module is by the single-ended pin be connected with differential conversion circuit.
10. method according to claim 9, is characterized in that, described chip device is also built-in with m on-off circuit, and the described single-ended single-end port with differential conversion circuit of m is connected to the pin of described chip device respectively by a described m on-off circuit; In each pin of this connecting valve circuit, each pin is at least connected with two described on-off circuits; Wherein, described m is the natural number being less than or equal to n;
Also comprise before described method:
Each on-off circuit corresponding to module to be tested is set to conducting state, and each on-off circuit corresponding to other modules except module to be tested is set to off-state;
On-off circuit corresponding to module is for this module is by the single-ended on-off circuit be connected with differential conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395193.0A CN104422867B (en) | 2013-09-03 | 2013-09-03 | A kind of chip device and its method of testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395193.0A CN104422867B (en) | 2013-09-03 | 2013-09-03 | A kind of chip device and its method of testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104422867A true CN104422867A (en) | 2015-03-18 |
| CN104422867B CN104422867B (en) | 2017-06-06 |
Family
ID=52972443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310395193.0A Active CN104422867B (en) | 2013-09-03 | 2013-09-03 | A kind of chip device and its method of testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104422867B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330132A (en) * | 2016-08-17 | 2017-01-11 | 北京无线电测量研究所 | Middle-frequency two-way active balun |
| CN107765576A (en) * | 2016-08-19 | 2018-03-06 | 智瑞佳（苏州）半导体科技有限公司 | A kind of power conversion chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020163387A1 (en) * | 1999-04-21 | 2002-11-07 | Infineon Technologies North America Corp., A Delaware Corporation | System and method for converting from single-ended to differential signals |
| CN1531201A (en) * | 2003-03-13 | 2004-09-22 | 因芬尼昂技术股份公司 | Low current lost waiting state circuit for converting differential signal into monoterminal signal |
| CN101005282A (en) * | 2006-01-20 | 2007-07-25 | 三星电子株式会社 | Differential-to-single-ended converter and phase-locked loop circuit having the same |
| CN102723944A (en) * | 2012-07-03 | 2012-10-10 | 佛山敏石芯片有限公司 | Method and circuit for converting single-ended signal to differential signal |
| CN102904552A (en) * | 2012-10-18 | 2013-01-30 | 上海宏力半导体制造有限公司 | Differential to single-ended convertor |
| CN202713264U (en) * | 2012-07-03 | 2013-01-30 | 佛山敏石芯片有限公司 | Circuit converting single-terminal signal into difference signal |
| US8384438B1 (en) * | 2011-08-11 | 2013-02-26 | Initio Corporation | Single-to-differential conversion circuit and method |
| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
-
2013
- 2013-09-03 CN CN201310395193.0A patent/CN104422867B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020163387A1 (en) * | 1999-04-21 | 2002-11-07 | Infineon Technologies North America Corp., A Delaware Corporation | System and method for converting from single-ended to differential signals |
| CN1531201A (en) * | 2003-03-13 | 2004-09-22 | 因芬尼昂技术股份公司 | Low current lost waiting state circuit for converting differential signal into monoterminal signal |
| CN101005282A (en) * | 2006-01-20 | 2007-07-25 | 三星电子株式会社 | Differential-to-single-ended converter and phase-locked loop circuit having the same |
| US8384438B1 (en) * | 2011-08-11 | 2013-02-26 | Initio Corporation | Single-to-differential conversion circuit and method |
| CN102723944A (en) * | 2012-07-03 | 2012-10-10 | 佛山敏石芯片有限公司 | Method and circuit for converting single-ended signal to differential signal |
| CN202713264U (en) * | 2012-07-03 | 2013-01-30 | 佛山敏石芯片有限公司 | Circuit converting single-terminal signal into difference signal |
| CN102904552A (en) * | 2012-10-18 | 2013-01-30 | 上海宏力半导体制造有限公司 | Differential to single-ended convertor |
| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330132A (en) * | 2016-08-17 | 2017-01-11 | 北京无线电测量研究所 | Middle-frequency two-way active balun |
| CN106330132B (en) * | 2016-08-17 | 2019-02-26 | 北京无线电测量研究所 | A kind of intermediate frequency bidirectional active balun |
| CN107765576A (en) * | 2016-08-19 | 2018-03-06 | 智瑞佳（苏州）半导体科技有限公司 | A kind of power conversion chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104422867B (en) | 2017-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203798886U (en) | Current sampling circuit | |
| CN103559128A (en) | Power-on and power-off test circuit and power-on and power-off test device | |
| CN103246631A (en) | Pin multiplexing method and circuit for improving pin use rate | |
| CN102931971B (en) | Three-state control signal input/output (IO) circuit | |
| CN103336240A (en) | A test circuit applied to chip tests of integrated circuits | |
| CN103684407A (en) | Otg device | |
| CN203673803U (en) | Signal source switching circuit for liquid crystal module testing, and liquid crystal module test tool | |
| CN103746681B (en) | A kind of upper and lower electricity output tri-state control circuit of cmos device power supply | |
| CN104422867A (en) | Chip device and testing method thereof | |
| CN202102275U (en) | IO port expansion circuit | |
| CN103187870B (en) | Buck conversion circuit | |
| CN207571730U (en) | A kind of debugging switching circuit and debugging circuit board | |
| CN110659037A (en) | JTAG-based burning device | |
| CN206224465U (en) | The circuit of the variable bus address of IIC devices | |
| CN106598900B (en) | LVDS driver circuit | |
| CN102832790A (en) | Power generating circuit and switching circuit | |
| CN204287861U (en) | A kind of audio-frequency signal switching device | |
| CN103901289A (en) | Test apparatus and test voltage generation method thereof | |
| CN109753394B (en) | Circuit and method for debugging firmware configuration information in real time | |
| CN206658151U (en) | A kind of power control circuit | |
| CN207782386U (en) | One kind preventing leakage circuit after chip power-down | |
| CN110166040A (en) | A kind of I O multiplexing circuit, integrated circuit and control method | |
| CN205210256U (en) | A device for expanding chroma 3380p test platform's function | |
| CN204291011U (en) | A kind of gigabit Ethernet switching device shifter | |
| CN203480508U (en) | Single-serial-port communication circuit for communicating different signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 510663 3rd floor, area C1, innovation building, 182 science Avenue, Guangzhou Science City, Luogang District, Guangzhou City, Guangdong Province Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 510663 3rd floor, area C1, innovation building, 182 science Avenue, Guangzhou Science City, Luogang District, Guangzhou City, Guangdong Province Patentee before: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 510555 No. 107 Bowen Road, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Ankai Microelectronics Co., Ltd Address before: 510663 floor 3, zone C1, innovation building, No. 182, science Avenue, Guangzhou Science City, Luogang District, Guangzhou City, Guangdong Province Patentee before: Guangzhou Ankai Microelectronics Co., Ltd |