CN104422867B - A kind of chip device and its method of testing - Google Patents
A kind of chip device and its method of testing Download PDFInfo
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- CN104422867B CN104422867B CN201310395193.0A CN201310395193A CN104422867B CN 104422867 B CN104422867 B CN 104422867B CN 201310395193 A CN201310395193 A CN 201310395193A CN 104422867 B CN104422867 B CN 104422867B
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Abstract
The invention provides a kind of chip device and its method of testing, the chip device is built-in with n module and n single-ended and differential conversion circuit, each described module corresponds to a described single-ended and differential conversion circuit respectively, each described module connects the single-ended difference port with differential conversion circuit corresponding with the module, each single-ended pin for being connected the chip device respectively with the single-end port of differential conversion circuit；Wherein.In the present invention n module and n single-ended and differential conversion circuit are built-in with chip device, each module connects a corresponding single-ended difference port with differential conversion circuit, therefore the differential signal that the module is exported is converted into single-ended signal or is converted into being exported after differential signal to the module by single-ended signal, the single-ended pin that chip device is connected with the single-end port of differential conversion circuit, it can be seen that, each module need to only take a pin, therefore n module need to only take n pin, so as to save the pin resource of preciousness.
Description
Technical field
The present invention relates to testing field, more particularly, to a kind of chip device and its method of testing.
Background technology
In the prior art, multiple modules are generally included in chip device, each module is input into or exports simulation letter
Number when, use differential signal.Therefore, each module needs to take two pins of chip device, for input or defeated
Go out differential signal.Obviously, if a chip device has n module, n module will take at least 2n pin.Can
See, the pin number that the modules of chip device take in the prior art is more, so as to cause valuable pin resource
Waste.
The content of the invention
Present invention solves the technical problem that being to provide a kind of chip device and its method of testing, realize that reducing module takes
The pin number of chip device, so as to save the pin resource of preciousness.
Therefore, the technical scheme that the present invention solves technical problem is：
The invention provides a kind of chip device, the chip device is built-in with n module and n single-ended and difference turn
Circuit is changed, each described module corresponds to a described single-ended and differential conversion circuit respectively, each described module is connected and the mould
The corresponding single-ended difference port with differential conversion circuit of block, each is single-ended to be connected respectively with the single-end port of differential conversion circuit
The pin of the chip device；Wherein, the n is the natural number more than or equal to 1.
Preferably, the chip device is also built-in with m on-off circuit, and m described single-ended and differential conversion circuit
Single-end port is connected to the pin of the chip device by the m on-off circuit respectively；The connecting valve circuit each
In pin, each pin has been at least connected with two on-off circuits；Wherein, the m is the natural number less than or equal to n.
Preferably, the m is equal to n, and the n single-ended individual by n respectively with the single-end port of differential conversion circuit
The on-off circuit is connected to the same pin of the chip device.
Preferably, the chip device is additionally provided with controlling switch, and the control signal that the controlling switch is received is used for
Control conducting and the closure of the on-off circuit.
Preferably, any one described on-off circuit includes the first NMOS tube and the first PMOS；
The drain electrode of first NMOS tube is connected with the drain electrode of first PMOS, used as the on-off circuit
Input port；The source electrode of first NMOS tube is connected with the source electrode of a PMOS, used as switch electricity
The output port on road；
If the single-end port of the single-ended and differential conversion circuit of on-off circuit connection is the single-ended and differential conversion circuit
Output port when, the input port of the on-off circuit connects the single-end port；If the single-ended and difference of on-off circuit connection
When the single-end port of change-over circuit is the input port of the single-ended and differential conversion circuit, the output port connection of the on-off circuit
The single-end port.
Preferably, described single-ended and differential conversion circuit is single-ended transfer difference circuit or differential-to-single-ended circuit.
Preferably, any one described differential-to-single-ended circuit includes：Second PMOS, the 3rd PMOS,
Four PMOSs, the 5th PMOS, the 6th PMOS, the 7th PMOS, the second NMOS tube, the 3rd
NMOS tube, the 4th NMOS tube, the 5th NMOS tube and first resistor；
The source electrode of the second PMOS, the source electrode of the 3rd PMOS, the source electrode of the 4th PMOS and
The source electrode of five PMOSs is connected to the grid company of supply voltage, the grid of the second PMOS and the second NMOS tube
It is connected to the cut-in voltage of the differential-to-single-ended circuit, the drain electrode of the second PMOS, the drain electrode of the 3rd PMOS and grid
Pole, the grid of the 4th PMOS, the drain electrode of the grid and the second NMOS tube of the 5th PMOS are connected to biasing
Voltage, the source electrode and the source electrode of the 7th PMOS of drain electrode the 6th PMOS of connection of the 4th PMOS, the 6th
The drain and gate and the grid of the 4th NMOS tube of drain electrode the 3rd NMOS tube of connection of PMOS, the 7th
The drain electrode of drain electrode the 4th NMOS tube of connection of PMOS and the grid of the 5th NMOS tube, the 5th NMOS tube
Grid pass through first resistor connect the 5th NMOS tube drain electrode and the 5th PMOS drain electrode, the 5th NMOS
The source electrode of pipe, the source electrode of the 4th NMOS tube, the source electrode of the 3rd NMOS tube, the source electrode of the second NMOS tube are connected to
Ground voltage, the drain electrode of the 5th PMOS as the differential-to-single-ended circuit output port, the 6th PMOS
Grid and the 7th PMOS grid as the differential-to-single-ended circuit input port.
Preferably, any one described single-ended transfer difference circuit includes：8th PMOS, the 9th PMOS,
Ten PMOSs, the 11st PMOS, the 12nd PMOS, the 6th NMOS tube, the 7th NMOS tube,
8th NMOS tube, the 9th NMOS tube, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance and
Electric capacity；
The source electrode of the 8th PMOS, the source electrode of the 9th PMOS and the source electrode of the tenth PMOS are connected to
Supply voltage, the drain electrode of the 8th PMOS, the grid of the 9th PMOS and drain electrode, the first end of 3rd resistor and
The grid of the tenth PMOS is connected to bias voltage, and the second end of 3rd resistor connects the first end and the 6th of the 5th resistance
The source electrode of NMOS tube, the first end and the first end of second resistance of drain electrode the 4th resistance of connection of the 6th NMOS tube,
Second end of second resistance is connected to the first end of the electric capacity and the grid of the 12nd PMOS, the second of the 4th resistance
The first end of the 6th resistance of end connection and the grid of the 11st PMOS, the grid of the 6th NMOS tube, the 8th PM
The grid of the grid of OS pipes, the grid, the grid of the 8th NMOS tube and the 9th NMOS tube of the 7th NMOS tube
The cut-in voltage of the single-ended transfer difference circuit is connected to, the second end of the 5th resistance connects the drain electrode of the 7th NMOS tube, the
The second of the source electrode of seven NMOS tubes, the source electrode of the 8th NMOS tube, the source electrode of the 9th NMOS tube and the electric capacity
End is connected to ground voltage, and the drain electrode of the tenth PMOS is connected to the source electrode and the 12nd PMO of the 11st PMOS
The source electrode of S pipes, the drain electrode of drain electrode the 8th NMOS tube of connection of the 11st PMOS, the 12nd PMOS
The drain electrode of drain electrode the 9th NMOS tube of connection；Second end of the 6th resistance is the input of the single-ended transfer difference circuit
Mouthful, the drain electrode of the 11st PMOS and the drain electrode of the 12nd PMOS are the single-ended transfer difference circuit
Output port.
Present invention also offers a kind of chip device method of testing, the chip device is built-in with n module and n single
End and differential conversion circuit, each described module correspond to a described single-ended and differential conversion circuit, each described module respectively
The connection single-ended difference port with differential conversion circuit corresponding with the module, each single-ended and differential conversion circuit single-ended end
Mouth connects the pin of the chip device respectively；Wherein, the n is the natural number more than or equal to 1；
There is at least one module to be tested in the n module；Methods described includes：It is defeated to test module to be tested
Go out the output signal of the pin corresponding to the module of module, and the drawing corresponding to the module of input module to module to be tested
Pin input test signal；
Pin corresponding to module is that the module passes through the single-ended pin being connected with differential conversion circuit.
Preferably, the chip device is also built-in with m on-off circuit, and m described single-ended and differential conversion circuit
Single-end port is connected to the pin of the chip device by the m on-off circuit respectively；The connecting valve circuit each
In pin, each pin has been at least connected with two on-off circuits；Wherein, the m is the natural number less than or equal to n；
Also include before methods described：
Each on-off circuit corresponding to module to be tested is set to conducting state, and by addition to module to be tested
Each on-off circuit corresponding to other modules is set to off-state；
On-off circuit corresponding to module is that the module passes through the single-ended on-off circuit being connected with differential conversion circuit.
According to the above-mentioned technical solution, n module and n single-ended and difference are built-in with chip device in the present invention
Change-over circuit, each module connects a corresponding single-ended difference port with differential conversion circuit, therefore by the module
The differential signal of output is converted into single-ended signal or is converted into single-ended signal to be exported after differential signal to the module, single-ended
With the pin that the single-end port of differential conversion circuit is connected chip device, it is seen then that each module need to only take a pin, therefore
N module need to only take n pin, need to take 2n pin compared to n module in the prior art, reduce occupancy
The pin number of chip device, so as to save the pin resource of preciousness.
Brief description of the drawings
Circuit connection when Fig. 1 is test chip device of the prior art；
The concrete structure diagram of the first embodiment of the chip device that Fig. 2 is provided for the present invention；
The concrete structure diagram of the second embodiment of the chip device that Fig. 3 is provided for the present invention；
A kind of preferred concrete structure diagram of the second embodiment of the chip device that Fig. 4 is provided for the present invention；
A kind of concrete structure diagram of on-off circuit that Fig. 5 is provided for the present invention；
A kind of concrete structure diagram of differential-to-single-ended circuit that Fig. 6 is provided for the present invention；
The concrete structure diagram of another differential-to-single-ended circuit that Fig. 7 is provided for the present invention；
A kind of concrete structure diagram of single-ended transfer difference circuit that Fig. 8 is provided for the present invention；
The concrete structure diagram of another single-ended transfer difference circuit that Fig. 9 is provided for the present invention；
The schematic flow sheet of the specific embodiment of the chip device method of testing that Figure 10 is provided for the present invention.
Specific embodiment
In the prior art, multiple modules are generally included in chip device, each module is input into or exports simulation letter
Number when, use differential signal.Therefore, each module needs to take two pins of chip device, for input or defeated
Go out differential signal.Obviously, if a chip device has n module, n module will take at least 2n pin.It is real
On border, used, it is necessary to differential signal is converted into single-ended signal in some cases.For example, when test chip device, a lot
Test equipment is single-ended test mouthful, such as signal generator and oscillograph are now accomplished by the external difference of chip device
After turning single-ended chip or single-ended transfer difference chip, test equipment is reconnected.As shown in figure 1, working as module（Such as module 2）For defeated
When entering module, the single-ended signal of output is changed into differential signal by signal generator by single-ended transfer difference chip, the differential signal
By two pins on chip device（Such as pin 3 and pin 4）Export to input module.Work as module（Such as module 1）For
During output module, the differential signal of module output is by two pins on chip device（Such as pin 1 and pin 2）Output is extremely
Difference turns single-ended chip, and the differential signal turns single-ended chip and changes into single-ended signal by difference, and it is single-ended to test this by oscillograph
Signal.It can be seen that, the number of pins that the modules of chip device take in the prior art is more, and pin resource to be typically comparing precious
Expensive；And due to the external difference of chip device and single-ended conversion chip, therefore to operate more complicated.
And in embodiments of the present invention, there is provided a kind of chip device and its method of testing, realize that reducing module takes core
The pin number of piece device, thus save preciousness pin resource, while test the chip when without external difference with it is single-ended
Conversion chip, so as to reduce Operating Complexity.
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Embodiment is described in detail.
Fig. 2 is referred to, the invention provides the first embodiment of chip device, in the present embodiment, the chip device
It is built-in with n module and n single-ended and differential conversion circuit.As shown in Fig. 2 n module is respectively module 1, module 2, mould
Block 3, module 4 ..., module n, n it is single-ended be respectively with a differential conversion circuit it is single-ended with differential conversion circuit 1, it is single-ended with it is poor
Point change-over circuit 2, it is single-ended with differential conversion circuit 3, it is single-ended with differential conversion circuit 4 ..., it is single-ended with differential conversion circuit n.
Wherein, the n is the natural number more than or equal to 1.That is, chip device is at least built-in with 1 module.
Each described module corresponds to a described single-ended and differential conversion circuit respectively, and each described module is connected and the mould
The corresponding single-ended difference port with differential conversion circuit of block, each is single-ended to be connected respectively with the single-end port of differential conversion circuit
The pin of the chip device.
The conversion that described single-ended and differential conversion circuit is used between single-ended signal and differential signal, specially single-ended slip
Parallel circuit or differential-to-single-ended circuit.When module is input module, that is, need during to the module input signal, the mould
Block one single-ended transfer difference circuit of correspondence, when module is output module, that is, during the module output signal, module correspondence
One differential-to-single-ended circuit.In fig. 2, the corresponding single-ended and differential conversion circuit 1 of module 1, the correspondence of module 2 is single-ended to be turned with difference
Circuit 2 is changed, the like, the corresponding single-ended and differential conversion circuit n of module n.
Each described module connects the single-ended difference port with differential conversion circuit corresponding with the module.Therefore, module 1
The single-ended difference port with differential conversion circuit 1 of connection, module 2 connects single-ended and differential conversion circuit 2 difference port, successively
Analogize, the single-ended difference port with differential conversion circuit n of module n connections.
Each single-ended pin for being connected the chip device respectively with the single-end port of difference channel.As shown in Fig. 2 single-ended
Pin 1 is connected with the single-end port of differential conversion circuit 1, the single-ended single-end port with differential conversion circuit 2 is connected pin 2, according to
Secondary to analogize, the single-ended single-end port with differential conversion circuit n is connected pin n.
It should be noted that each pin in pin 1 to pin n is probably input pin, it is also possible to which output is drawn
Pin, is determined by pin by the single-ended module being connected with differential conversion circuit, if the module is input module, input module
The pin of correspondence connection is input pin, if the module is output module, the pin of output module correspondence connection is output
Pin.
According to the above-mentioned technical solution, in the present embodiment chip device be built-in with n module and n it is single-ended with it is poor
Point change-over circuit, each module connects a corresponding single-ended difference port with differential conversion circuit, therefore by the mould
The differential signal of block output is converted into single-ended signal or is converted into being exported after differential signal to the module by single-ended signal, single
End is connected the pin of chip device with the single-end port of differential conversion circuit, it is seen then that each module need to only take a pin, because
This n module need to only take n pin, need to take 2n pin compared to n module in the prior art, reduce and account for
With the pin number of chip device, so as to save the pin resource of preciousness.
Meanwhile, without to the external difference of chip device and single-ended conversion chip, so as to reduce Operating Complexity.
Fig. 3 is referred to, the invention provides the second embodiment of chip device, in the present embodiment, the chip device
It is built-in with n module and n single-ended and differential conversion circuit.As shown in figure 3, n module is respectively module 1, module 2, mould
Block 3, module 4 ..., module n, n it is single-ended be respectively with a differential conversion circuit it is single-ended with differential conversion circuit 1, it is single-ended with it is poor
Point change-over circuit 2, it is single-ended with differential conversion circuit 3, it is single-ended with differential conversion circuit 4 ..., it is single-ended with differential conversion circuit n.
Wherein, the n is the natural number more than or equal to 1.That is, chip device is at least built-in with 1 module.
Each described module corresponds to a described single-ended and differential conversion circuit respectively, and each described module is connected and is somebody's turn to do
The corresponding single-ended difference port with differential conversion circuit of module.Each single-ended single-end port with differential conversion circuit connects respectively
Connect the pin of the chip device.
The chip device is also built-in with m on-off circuit, therefore, described each single-ended and differential conversion circuit list
End port connects the pin of the chip device respectively, specifically includes two kinds of situations, and a kind of situation is that m described single-ended and poor
The single-end port of point change-over circuit is connected to the pin of the chip device, another feelings by the m on-off circuit respectively
Condition is that other each the single-ended and difference in addition to the individual single-ended and differential conversion circuits of the m being connected with m on-off circuit rotate electricity
Road connects the pin of the chip device respectively.As shown in figure 3, module 1 connects single-ended and differential conversion circuit 1 differential ends
Mouthful, single-ended to be connected to pin 1 by on-off circuit 1 with differential conversion circuit 1 single-end port, module 2 connects single-ended and difference
The difference port of change-over circuit 2, it is single-ended that pin 1 is also connected to by on-off circuit 2 with differential conversion circuit 2 single-end port.
The single-ended difference port with differential conversion circuit n of module n connections, the single-ended single-end port with differential conversion circuit n is connected and draws
Pin j.Wherein, the m is the natural number less than or equal to n.
In each pin of the connecting valve circuit, each pin has been at least connected with two on-off circuits.Because
In the built-in n on-off circuit of chip device in the present embodiment, therefore, it is two or more single-ended with differential conversion electricity
Road can be connected to same pin by an on-off circuit respectively.So in the present embodiment, each connecting valve circuit
Pin, has been at least connected with two on-off circuits.As shown in figure 3, pin 1 is connected with on-off circuit 1 and on-off circuit 2, draw
Pin 2 is connected with on-off circuit 3 and on-off circuit 4.
In the present embodiment, because each pin of connecting valve circuit is connected to two at least through two on-off circuits
Module, therefore, at least two modules need to only take a pin, and the pin number j of n module occupancy is less than n.Therefore, phase
Than the embodiment in Fig. 2, pin number is further reduced in the present embodiment, save the pin resource of preciousness.
It should be noted that in the present embodiment, an on-off circuit can connect multiple pins, then the on-off circuit is corresponding
The module of connection can use multiple pins.
In the present embodiment, in order that pin quantity it is minimum, can in chip device built-in n on-off circuit,
I.e. described m is equal to n, then as shown in figure 4, the n single-ended single-end port with differential conversion circuit passes through n institute respectively
State the same pin that on-off circuit is connected to the chip device.Now, n module need to only take a pin.It is maximized
Reduce pin resource.
In the present embodiment, when want using a certain module when, only need to control to should module on-off circuit turn on, its
Remaining all of on-off circuit disconnects.Therefore, the chip device is additionally provided with controlling switch, and the controlling switch is received
Control signal be used to control the conducting of the on-off circuit and disconnect.The control signal is specially control test module correspondence
On-off circuit conducting, and the control letter that the corresponding on-off circuit of other modules in addition to the test module of control disconnects
Number.
The present invention provides a kind of concrete structure of on-off circuit below.In the present embodiment, any one on-off circuit all may be used
To use this structure.As shown in figure 5, any one described on-off circuit includes a first NMOS tube N1 and PMO
S pipes P1.
The drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS P1, used as the on-off circuit
Input port, the source electrode of the first NMOS tube N1 is connected with the source electrode of a PMOS P1, is opened as this
The output port on powered-down road.The grid of the first NMOS tube N1 and the grid of a PMOS P1 are the on-off circuit
Control end, for controlling simultaneously, N1 and P1 is in the conduction state or off-state, so as to realize controlling the on-off circuit
The state that is turned on or off.
Because NMOS tube can only export low level, PMOS can only export high level, therefore, this N in parallel
The form of metal-oxide-semiconductor and PMOS ensure that on-off circuit can export high level, can also export low level.
If the single-end port of the single-ended and differential conversion circuit of on-off circuit connection is the single-ended and differential conversion circuit
Output port when, the input port of the on-off circuit connects the single-end port, and the output port connection of the on-off circuit is described
The pin of chip device；If the single-end port of the single-ended and differential conversion circuit of on-off circuit connection turns for this is single-ended with difference
When changing the input port of circuit, the output port of the on-off circuit connects the single-end port, and the input port of the on-off circuit connects
Connect the pin of the chip device.If for example, when on-off circuit 1 in Fig. 3 is using structure shown in Fig. 5, if switch electricity
When the single ended interfaces of the single-ended and differential conversion circuit 1 of the connection of road 1 are output port, that is to say, that now module 1 is output mould
Block, single-ended and differential conversion module 1 turns single-ended block for difference, now the first NMOS tube N1 and the first PMOS
The drain electrode of P1 connects single-ended and differential conversion circuit 1, and the source electrode of the first NMOS tube N1 and the first PMOS P1 connects
Connect pin 1.If the on-off circuit 2 in Fig. 3 uses the structure shown in Fig. 5, if the single-ended and differential conversion of the connection of on-off circuit 2
When the single ended interfaces of circuit 2 are input port, that is to say, that now module 2 is input module, single-ended to be with differential conversion module 2
Single-ended transfer difference module, now the source electrode connection of the first NMOS tube N1 and the first PMOS P1 is single-ended turns with difference
Change circuit 2, the drain electrode connection pin 1 of the first NMOS tube N1 and the first PMOS P1.
It should be noted that in addition to the structure shown in Fig. 5, on-off circuit may also take on other structures, as long as can be real
Existing on-off action, the present invention is not limited this.
In the present invention, single-ended is single-ended transfer difference circuit or differential-to-single-ended circuit with differential conversion circuit.Below
The present invention provides the concrete structure of a kind of single-ended transfer difference circuit and differential-to-single-ended circuit, any implementation in the present invention respectively
Any one single-ended and differential conversion circuit in example can use following structure.
As shown in fig. 6, any one differential-to-single-ended circuit can include：Second PMOS P2, the 3rd PMOS
Pipe P3, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P
7th, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and
One resistance R1.
The source electrode of the second PMOS P2, the source electrode of the 3rd PMOS P3, the source of the 4th PMOS P4
The source electrode of pole and the 5th PMOS P5 is connected to supply voltage VDD, the grid of the second PMOS P2 and
The grid of two NMOS tube N2 is connected to the cut-in voltage of the differential-to-single-ended circuit.The cut-in voltage is used to control entirely
Whether the state of differential-to-single-ended circuit is in running order.Specifically, when the cut-in voltage is high level, whole difference turns
Single-end circuit is in running order.
The drain electrode of the second PMOS P2, the drain and gate of the 3rd PMOS P3, the 4th PMOS
The grid of P4, the drain electrode of the grid of the 5th PMOS P5 and the second NMOS tube N2 are connected to bias voltage VB
P.Bias voltage VBP causes the 3rd PMOS P3, the 4th PMOS P4 and the 5th PMOS P5
Work in saturation region.
The source electrode and the 7th PMOS P7 of the 6th PMOS P6 of drain electrode connection of the 4th PMOS P4
Source electrode, the 6th PMOS P6 drain electrode connection the 3rd NMOS tube N3 drain and gate and the 4th NM
The grid of OS pipes N4, the drain electrode of the 4th NMOS tube N4 of drain electrode connection of the 7th PMOS P7 and the 5th NM
The grid of OS pipes N5, the grid of the 5th NMOS tube N5 also connects the 5th NMOS tube N5 by first resistor R1
Drain electrode and the 5th PMOS P5 drain electrode, the source electrode of the 5th NMOS tube N5, the source of the 4th NMOS tube N4
Pole, the source electrode of the 3rd NMOS tube N3, the source electrode of the second NMOS tube N2 are connected to ground voltage VSS.
In the differential-to-single-ended circuit, the drain electrode of the 5th PMOS P5 is used as the defeated of the differential-to-single-ended circuit
Exit port, i.e. Single-end output.The grid of the 6th PMOS P6 and the grid of the 7th PMOS P7 are used as the difference
Turn the input port of single-end circuit, that is, Differential Input 1 and Differential Input 2.
As shown in fig. 7, the differential-to-single-ended circuit can also include the 7th resistance R7, the 8th resistance R8 and the 9th resistance
R9.9th resistance R9 is located at the public section of drain electrode with the drain electrode of the 3rd PMOS P3 of the second PMOS P2
Point, between the drain electrode with the second NMOS tube N2.The first end of the 7th resistance R7 connects the source of the 6th PMOS P6
Pole, the first end of the 8th resistance R8 connects the hourglass source electrode of the 7th PMOS P7, second end and the 8th of the 7th resistance R7
After the second end connection of resistance R8, the drain electrode with the 4th PMOS P4 is connected.
As shown in figure 8, any one described single-ended transfer difference circuit can include：8th PMOS P8, the 9th PM
OS pipes P9, the tenth PMOS P10, the 11st PMOS P11, the 12nd PMOS P12, the 6th N
Metal-oxide-semiconductor N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, second resistance R
2nd, 3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and electric capacity C.
The source electrode of the 8th PMOS P8, the source electrode of the 9th PMOS P9 and the tenth PMOS P10's
Source electrode is connected to drain electrode, the grid of the 9th PMOS P9 and the leakage of supply voltage VDD, the 8th PMOS P8
The grid of pole, the first end of 3rd resistor R3 and the tenth PMOS P10 is connected to bias voltage VBP.The biasing
Voltage VBP causes that the 9th PMOS P9 and the tenth PMOS P10 work in saturation region.
Second end of 3rd resistor R3 connects the first end of the 5th resistance R5 and the source electrode of the 6th NMOS, the 6th N
The first end and the first end of second resistance R2 of the 4th resistance R4 of drain electrode connection of metal-oxide-semiconductor N6, the of second resistance R2
Two ends are connected to the first end of the electric capacity C and the grid of the 12nd PMOS P12, second end of the 4th resistance R4
Connect the first end of the 6th resistance R6 and the grid of the 11st PMOS P11, the grid of the 6th NMOS tube N6,
The grid of the 8th PMOS P8, the grid of the 7th NMOS tube N7, the grid and the 9th of the 8th NMOS tube N8
The grid of NMOS tube N9 is connected to the cut-in voltage of the single-ended transfer difference circuit.The cut-in voltage is used to control whole list
Hold the state of slip parallel circuit whether in running order.Specifically, when the cut-in voltage is high level, whole single-ended slip
Parallel circuit is in running order.
Second end of the 5th resistance R5 connects the drain electrode of the 7th NMOS tube N7, the source of the 7th NMOS tube N7
Pole, the second end of the source electrode, the source electrode of the 9th NMOS tube N9 and the electric capacity C of the 8th NMOS tube N8 are connected to
Ground voltage VSS, the drain electrode of the tenth PMOS P10 is connected to the source electrode and the 12nd of the 11st PMOS P11
The source electrode of PMOS P12, the drain electrode of the 8th NMOS tube N8 of drain electrode connection of the 11st PMOS P11, the
The drain electrode of the 9th NMOS tube N9 of drain electrode connection of 12 PMOS P12.
In the single-ended transfer difference circuit, second end of the 6th resistance R6 is the input port of the single-ended transfer difference circuit, i.e.,
Single ended input, the drain electrode of the 11st PMOS P11 and the drain electrode of the 12nd PMOS P12 are the list
Hold the output port of slip parallel circuit, that is, Differential Input 1 and Differential Input 2.
As shown in figure 9, the differential-to-single-ended circuit can also include the tenth resistance R10, the 11st resistance R11, the tenth
Two resistance R12 and the 13rd resistance R13.
The first end of the tenth resistance R10 is connected with the source electrode of the 11st PMOS P11, the 11st resistance R11's
First end is connected with the source electrode of the 12nd PMOS P12, second end of the tenth resistance R10 and the 11st resistance R11's
After the connection of second end, the drain electrode with the tenth PMOS P10 is connected.12nd resistance R12 is connected to the 11st PMO
Between S pipes P11 and the 8th NMOS tube N8, the 13rd resistance R13 is connected to the 12nd PMOS P12 and
Between nine NMOS tube N9.Node between 11st PMOS P11 and the 12nd resistance R12, and the 12nd
Node between PMOS P12 and the 13rd resistance R13 is output port.
Present invention also offers chip device method of testing, for testing the chip device that the present invention is provided.
The test equipment used during test is the equipment of single port, such as oscillograph, signal generator etc..Elaborate below.
Present invention also offers the specific embodiment of chip device method of testing, methods described is used for shown in test chart 2
Chip device in embodiment.Specifically, the chip device is built-in with n module and n single-ended and differential conversion circuit,
Each described module corresponds to a described single-ended and differential conversion circuit respectively, and each described module connection is corresponding with the module
The single-ended difference port with differential conversion circuit, each is single-ended to be connected the chip respectively with the single-end port of differential conversion circuit
The pin of device；Wherein, the n is the natural number more than or equal to 1.
There is at least one module to be tested in the n module.That is, will in n module or
Multiple modules are tested.These modules to be tested can be input module, or output module.
In the present embodiment, methods described includes：
S101：Test the output signal of the pin corresponding to the module that module to be tested is output module.
S102：To pin input test signal of the module to be tested corresponding to the module of input module.
Pin corresponding to module is that the module passes through the single-ended pin being connected with differential conversion circuit.
Wherein, the execution sequence of step S101 and step S102 is not limited.Can perform simultaneously, it is also possible to successively
Order is performed.If module to be tested is output module, S101 is performed, if module to be tested is input module,
Perform S102.
Step S101 test when can be tested by oscillograph, in step S102 test signal can be by
Signal generator is exported.
Preferably, chip device that can also be further to the embodiment shown in Fig. 3 is tested.Now, the chip
Device is also built-in with m on-off circuit, and m described single-ended individual by the m respectively with the single-end port of differential conversion circuit
On-off circuit is connected to the pin of the chip device；In each pin of the connecting valve circuit, each pin is at least connected with
There are two on-off circuits；Wherein, the m is the natural number less than or equal to n.
Then also include before step S101：
Each on-off circuit corresponding to module to be tested is set to conducting state, and by addition to module to be tested
Each on-off circuit corresponding to other modules is set to off-state.
On-off circuit corresponding to module is that the module passes through the single-ended on-off circuit being connected with differential conversion circuit.
The chip device method of testing that the present invention is provided can be used for the implementation of any chip device provided the present invention
Example.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (9)
1. a kind of chip device, it is characterised in that the chip device is built-in with n module and n single-ended with differential conversion electricity
Road, each described module corresponds to a described single-ended and differential conversion circuit respectively, and each described module is connected and the module pair
The difference port of the single-ended and differential conversion circuit answered, each is single-ended to be connected described with the single-end port of differential conversion circuit respectively
The pin of chip device；Wherein, the n is the natural number more than or equal to 1；
The chip device is also built-in with m on-off circuit, and the m single-ended single-end port with differential conversion circuit leads to respectively
Cross the pin that the m on-off circuit is connected to the chip device；In each pin of the connecting valve circuit, each pin
It has been at least connected with two on-off circuits；Wherein, the m is the natural number less than or equal to n.
2. device according to claim 1, it is characterised in that the m is equal to n, the n single-ended and differential conversion circuit
Single-end port the same pin of the chip device is connected to by n on-off circuits respectively.
3. device according to claim 1 and 2, the chip device is additionally provided with controlling switch, and the controlling switch connects
The control signal for receiving is used to control conducting and the closure of the on-off circuit.
4. device according to claim 1 and 2, it is characterised in that any one described on-off circuit includes the first NMOS tube
With the first PMOS；
The drain electrode of first NMOS tube is connected with the drain electrode of first PMOS, used as the input port of the on-off circuit；
The source electrode of first NMOS tube is connected with the source electrode of a PMOS, used as the output port of the on-off circuit；
If the single-ended single-end port with differential conversion circuit of on-off circuit connection is that this is single-ended defeated with differential conversion circuit
During exit port, the input port of the on-off circuit connects the single-end port；If the single-ended and differential conversion of on-off circuit connection
When the single-end port of circuit is the input port of the single-ended and differential conversion circuit, the output port of the on-off circuit connects the list
End port.
5. device according to claim 1, it is characterised in that it is described it is single-ended be single-ended transfer difference electricity with differential conversion circuit
Road or differential-to-single-ended circuit.
6. device according to claim 5, it is characterised in that any one described differential-to-single-ended circuit includes：Second
PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS pipes, the 7th PMOS, the second NMOS tube,
Three NMOS tubes, the 4th NMOS tube, the 5th NMOS tube and first resistor；
The source electrode of the second PMOS, the source electrode of the source electrode, the source electrode of the 4th PMOS and the 5th PMOS of the 3rd PMOS connect
It is connected to supply voltage, the grid of the grid of the second PMOS and the second NMOS tube is connected to the unlatching electricity of the differential-to-single-ended circuit
Pressure, the drain electrode of the second PMOS, the drain and gate of the 3rd PMOS, the grid of the 4th PMOS, the grid of the 5th PMOS
Bias voltage, the source electrode and the 7th of drain electrode the 6th PMOS of connection of the 4th PMOS are connected to the drain electrode of the second NMOS tube
The source electrode of PMOS, the drain and gate and the grid of the 4th NMOS tube of drain electrode the 3rd NMOS tube of connection of the 6th PMOS,
The drain electrode of drain electrode the 4th NMOS tube of connection of the 7th PMOS and the grid of the 5th NMOS tube, the grid of the 5th NMOS tube is by the
One resistance connects the drain electrode of the 5th NMOS tube and the drain electrode of the 5th PMOS, the source electrode of the 5th NMOS tube, the source of the 4th NMOS tube
Pole, the source electrode of the 3rd NMOS tube, the source electrode of the second NMOS tube are connected to ground voltage, and the drain electrode of the 5th PMOS is used as the difference
Divide the output port for turning single-end circuit, the grid of the 6th PMOS and the grid of the 7th PMOS are used as the differential-to-single-ended circuit
Input port.
7. device according to claim 5, it is characterised in that any one described single-ended transfer difference circuit includes：8th
PMOS, the 9th PMOS, the tenth PMOS, the 11st PMOS, the 12nd PMOS, the 6th NMOS tube, the 7th NMOS tube,
8th NMOS tube, the 9th NMOS tube, second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance and electric capacity；
The source electrode of the 8th PMOS, the source electrode of the 9th PMOS and the source electrode of the tenth PMOS are connected to supply voltage, the 8th
The grid connection of the drain electrode of PMOS, the grid of the 9th PMOS and drain electrode, the first end of 3rd resistor and the tenth PMOS
To bias voltage, the second end of 3rd resistor connects the first end of the 5th resistance and the source electrode of the 6th NMOS tube, the 6th NMOS tube
Drain electrode connection the 4th resistance first end and second resistance first end, the second end of second resistance is connected to the electric capacity
The grid of first end and the 12nd PMOS, the second end of the 4th resistance connects the first end and the 11st PMOS of the 6th resistance
Grid, the grid of the 6th NMOS tube, the grid of the 8th PMOS, the grid of the 7th NMOS tube, the grid of the 8th NMOS tube and
The grid of the 9th NMOS tube is connected to the cut-in voltage of the single-ended transfer difference circuit, and the second end of the 5th resistance connects the 7th NMOS
The drain electrode of pipe, the source electrode of the 7th NMOS tube, the second end of the source electrode, the source electrode of the 9th NMOS tube and the electric capacity of the 8th NMOS tube
Ground voltage is connected to, the drain electrode of the tenth PMOS is connected to the source electrode of the 11st PMOS and the source electrode of the 12nd PMOS, the
The drain electrode of drain electrode the 8th NMOS tube of connection of 11 PMOS pipes, the drain electrode of drain electrode the 9th NMOS tube of connection of the 12nd PMOS；
Second end of the 6th resistance is the input port of the single-ended transfer difference circuit, the drain electrode of the 11st PMOS and described
The drain electrode of the 12nd PMOS is the output port of the single-ended transfer difference circuit.
8. a kind of chip device method of testing, it is characterised in that the chip device be built-in with n module and n it is single-ended with it is poor
Point change-over circuit, each described module corresponds to a described single-ended and differential conversion circuit respectively, each described module connection with
The corresponding single-ended difference port with differential conversion circuit of the module, each single-ended single-end port with differential conversion circuit is distinguished
Connect the pin of the chip device；Wherein, the n is the natural number more than or equal to 1；
There is at least one module to be tested in the n module；Methods described includes：Module to be tested is tested for output module
Module corresponding to pin output signal, and to module to be tested for input module module corresponding to pin be input into
Test signal；
Pin corresponding to module is that the module passes through the single-ended pin being connected with differential conversion circuit.
9. method according to claim 8, it is characterised in that the chip device is also built-in with m on-off circuit, m
The single-ended single-end port with differential conversion circuit is connected to drawing for the chip device by the m on-off circuit respectively
Pin；In each pin of the connecting valve circuit, each pin has been at least connected with two on-off circuits；Wherein, the m is
Natural number less than or equal to n；
Also include before methods described：
Each on-off circuit corresponding to module to be tested is set to conducting state, and by other in addition to module to be tested
Each on-off circuit corresponding to module is set to off-state；
On-off circuit corresponding to module is that the module passes through the single-ended on-off circuit being connected with differential conversion circuit.
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| CN201310395193.0A CN104422867B (en) | 2013-09-03 | 2013-09-03 | A kind of chip device and its method of testing |
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| CN106330132B (en) * | 2016-08-17 | 2019-02-26 | 北京无线电测量研究所 | A kind of intermediate frequency bidirectional active balun |
| CN107765576A (en) * | 2016-08-19 | 2018-03-06 | 智瑞佳（苏州）半导体科技有限公司 | A kind of power conversion chip |
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| CN102723944A (en) * | 2012-07-03 | 2012-10-10 | 佛山敏石芯片有限公司 | Method and circuit for converting single-ended signal to differential signal |
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| CN102904552A (en) * | 2012-10-18 | 2013-01-30 | 上海宏力半导体制造有限公司 | Differential to single-ended convertor |
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| CN103066985A (en) * | 2012-12-06 | 2013-04-24 | 无锡中星微电子有限公司 | Chip provided with multiplex pin |
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| US6285259B1 (en) * | 1999-04-21 | 2001-09-04 | Infineon Technologies North America Corp. | System and method for converting from single-ended to differential signals |
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|---|---|---|---|---|
| CN1531201A (en) * | 2003-03-13 | 2004-09-22 | 因芬尼昂技术股份公司 | Low current lost waiting state circuit for converting differential signal into monoterminal signal |
| CN101005282A (en) * | 2006-01-20 | 2007-07-25 | 三星电子株式会社 | Differential-to-single-ended converter and phase-locked loop circuit having the same |
| US8384438B1 (en) * | 2011-08-11 | 2013-02-26 | Initio Corporation | Single-to-differential conversion circuit and method |
| CN102723944A (en) * | 2012-07-03 | 2012-10-10 | 佛山敏石芯片有限公司 | Method and circuit for converting single-ended signal to differential signal |
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| CN104422867A (en) | 2015-03-18 |
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