CN104836548B - The input circuit that the Duty Cycle Distortion of input signal can be compensated - Google Patents
The input circuit that the Duty Cycle Distortion of input signal can be compensated Download PDFInfo
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Abstract
The present invention provides a kind of input circuit that can be compensated to the Duty Cycle Distortion of input signal, and it includes：Dutycycle calibration module, its reference signal based on predetermined duty cycle produce output signal；Duty detection circuit, its input connects the output end of dutycycle calibration module, it detects the dutycycle of the output signal of dutycycle calibration module output, and output duty cycle calibrates control signal when the dutycycle of output signal is not equal to predetermined duty cycle, wherein dutycycle calibration module is calibrated based on the dutycycle calibration control signal that duty detection circuit exports to dutycycle calibration module, until the dutycycle of obtained output signal is equal to predetermined duty cycle；The input module for replicating the structure of dutycycle calibration module and being formed, it is calibrated also based on the dutycycle calibration control signal of duty detection circuit output to input module.Compared with prior art, input circuit provided by the invention can compensate to the Duty Cycle Distortion of input signal.
Description
【Technical field】
It is more particularly to a kind of the Duty Cycle Distortion of input signal to be compensated the present invention relates to circuit design field
Input circuit.
【Background technology】
For input circuit, due to non-ideal factors such as the mismatches of device, the dutycycle of input signal can be caused
Distortion.For example the dutycycle of input signal is 50%, after input circuit, due to the device in the input circuit
The non-ideal factors such as mismatch, may cause the dutycycle of output signal there was only 49%, 51%, or other values.Dutycycle
Distortion can consume many time margins, especially seem important under the conditions of high-speed applications.For at present, due to the mismatch of device
Duty Cycle Distortion Deng input signal caused by non-ideal factor can not eliminate, and only subtract by increasing the size of device
It is small.However, this can bring the increase of chip area and power consumption.
Therefore, it is necessary to propose a kind of input circuit that can be compensated to the Duty Cycle Distortion of input signal.
【The content of the invention】
It is an object of the invention to provide input circuit, and it can be compensated to the Duty Cycle Distortion of input signal.
In order to solve the above problems, the present invention provide it is a kind of the Duty Cycle Distortion of input signal can be compensated it is defeated
Enter circuit, it includes：Dutycycle calibration module, its reference signal based on predetermined duty cycle produce output signal；Dutycycle is examined
Slowdown monitoring circuit, its input connect the output end of the dutycycle calibration module, and it detects the dutycycle calibration module output
The dutycycle of output signal, and the output duty cycle calibration control when the dutycycle of the output signal is not equal to predetermined duty cycle
Signal, wherein dutycycle calibration module are calibrated based on the dutycycle calibration control signal that duty detection circuit exports to dutycycle
Module is calibrated, until the dutycycle of obtained output signal is equal to predetermined duty cycle；Replicate the knot of dutycycle calibration module
Structure and the input module formed, it enters also based on the dutycycle calibration control signal of duty detection circuit output to input module
Row calibration.
Further, the predetermined duty cycle is 50 percent, and the input circuit also includes：Reference voltage produces
Circuit, it produces reference voltage signal；Reference signal generation circuit, it produces the reference signal of predetermined duty cycle, wherein, duty
First input end than calibration module is connected with the reference signal of the predetermined duty cycle, and the second input receives the benchmark electricity
Press signal, its more described reference signal and the reference voltage signal and export the output signal for representing comparative result, it is described
The first input end of input module is connected with the desired input signals, and the second input receives the reference voltage signal, its
Compare the desired input signals and the reference voltage signal and export the target output signal for representing comparative result；Dutycycle
Calibration module is adjusted based on the dutycycle calibration control signal that duty detection circuit exports and obtains one group of dutycycle calibration ginseng
Number, the dutycycle calibration parameter obtained based on adjustment are calibrated to dutycycle calibration module, are controlled being calibrated based on dutycycle
One group of final dutycycle calibration parameter is obtained under the continuous adjustment of signal, based on the final dutycycle calibration parameter of the group to dutycycle
Calibration module is calibrated to cause the dutycycle of its output signal exported to be equal to predetermined duty cycle.
Further, duty detection circuit include buffer, phase inverter, first resistor, second resistance, the first electric capacity,
Second electric capacity, comparator and control unit.The input of the buffer is connected with the input of phase inverter, the buffer and
The input of the phase inverter receives the output signal from the output of dutycycle calibration module；The output end of buffer successively via
First resistor and the first electric capacity are connected with earth terminal, and the output end of phase inverter is successively via second resistance and the second electric capacity and ground connection
End is connected, and the connection end of first resistor and the first electric capacity is connected with the first input end of comparator, second resistance and the second electric capacity
Connection end be connected with the second input of comparator, the output end of comparator is connected with the input of control unit, the control
Unit processed calibrates control signal based on the comparative result output duty cycle that comparator exports.
Further, dutycycle calibration module and input module include output driving circuit, the output driving circuit
Including input, the multiple first output driving units being connected between power end and its output end and be connected to its output end and
Multiple second output driving units between earth terminal, include in each first output driving unit being connected to power end and institute
The first controlling switch and PMOS transistor between the output end of output driving circuit are stated, is wrapped in each second output driving unit
Include and be connected to nmos pass transistor and the second controlling switch between output and ground, in each first output driving unit
PMOS transistor is connected jointly with the grid of the nmos pass transistor of each second output driving unit, forms the output driving circuit
Input, the nmos pass transistor of PMOS transistor and each second output driving unit in each first output driving unit
Drain electrode be connected jointly after, the output end of the output driving circuit is formed, by controlling the first controlling switch and the second control to open
The introducing of the first output driving unit and the second output driving unit effectively where it can be somebody's turn to do by the on or off of pass
Output driving circuit removes from the output driving circuit, based on dutycycle calibration control signal control dutycycle calibration module
With the first controlling switch and the number of the second controlling switch turned in input module, to realize to dutycycle calibration module and defeated
Enter the calibration of module.
Further, the dutycycle calibration module and input module also include output buffer cell, and the output is delayed
The input for rushing unit is connected with the output end of the output driving circuit, and its output end is as dutycycle calibration module and input
The equal output end of module.
Further, the duty of the output signal of the dutycycle calibration module output is detected in duty detection circuit
During than less than predetermined duty cycle, output duty cycle calibrate control signal with increase the number of the first controlling switch of conducting and/or
Reduce the number of the second controlling switch of conducting；The defeated of the dutycycle calibration module output is detected in duty detection circuit
When going out the dutycycle of signal and being higher than predetermined duty cycle, output duty cycle calibrates control signal to reduce the first controlling switch of conducting
Number and/or increase conducting the second controlling switch number.
Further, the dutycycle calibration module and input module also include input comparing unit, the input
The reference signal or desired input signals of the first input end connection predetermined duty cycle of comparing unit, the input comparing unit
Second input connects a reference voltage signal, the output end of the input comparing unit and the input of the output driving circuit
It is connected.
Further, it is described input comparing unit include PMOS transistor MP0 and MP1, nmos pass transistor MN0, MN1,
MN0B and MN1B.PMOS transistor MP0 and MP1 source electrode is connected with power end, PMOS transistor MP0 drain electrode and nmos pass transistor
MN0 drain electrode is connected, and PMOS transistor MP1 drain electrode is connected with nmos pass transistor MN1 drain electrode, nmos pass transistor MN0, MN1,
MN0B and MN1B source electrode is connected with earth terminal, nmos pass transistor MN0B drain electrode and nmos pass transistor MN0 drain electrode and
Nmos pass transistor MN1B grid is connected, and nmos pass transistor MN1B drain electrode and nmos pass transistor MN1 drain electrode and NMOS are brilliant
Body pipe MN0B grid is connected, and PMOS transistor MP0 grid is used as the input after being connected with nmos pass transistor MN0 grid
The first input end of comparing unit, PMOS transistor MP1 grid be connected with nmos pass transistor MN1 grid after as described defeated
Enter the second input of comparing unit, the node that PMOS transistor MP1 drain electrode is connected with nmos pass transistor MN1 drain electrode is defeated
Enter the output end of comparing unit.
Compared with prior art, the dutycycle of dutycycle calibration module is calibrated using reference signal in the present invention,
It is achieved thereby that the synchronous calibration of the dutycycle to input module, non-ideal so as to eliminate or reduce the mismatch of device etc.
Factor influences to caused by the Duty Cycle Distortion of input signal.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these accompanying drawings other
Accompanying drawing.Wherein：
Fig. 1 is that the input circuit that the Duty Cycle Distortion of input signal compensates can be implemented at one in the present invention
Structured flowchart in example；
Fig. 2 is the structured flowchart of duty detection circuit in one embodiment in the present invention；
Fig. 3 is the structured flowchart of duty-ratio calibrating circuit or input module in one embodiment in the present invention；With
Fig. 4 is the circuit diagram of output driving circuit in one embodiment in Fig. 3.
【Embodiment】
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected with word represent directly or indirectly to be electrical connected.
Fig. 1 is the input circuit 100 that can be compensated to the Duty Cycle Distortion of input signal in the present invention at one
Structured flowchart in embodiment.As shown in Figure 1, the input circuit 100 includes reference signal generation circuit 110, benchmark electricity
Press generation circuit 120, dutycycle calibration module RX_0, duty detection circuit 130 and replicate dutycycle calibration module RX_0's
Structure and the input module RX_1 formed.
The reference voltage generating circuit 120 produces reference voltage signal VR.The reference signal generation circuit 110 produces
The reference signal RS of predetermined duty cycle.Dutycycle calibration module RX_0 first input end is believed with the benchmark of the predetermined duty cycle
Number RS is connected, and the second input receives the reference voltage signal VR.The first input end and target of the input module RX_1
Input signal IN is connected, and the second input receives the reference voltage signal VR.
The dutycycle calibration module RX_0 carries out dutycycle calibration to the reference signal RS of predetermined duty cycle and obtained defeated
Go out signal.In one embodiment, the predetermined duty cycle is 50 percent, is hereinafter situated between exemplified by 50 percent
Continue, but the technical staff in general field is it is appreciated that the predetermined duty cycle can also be changed to other values.It is described to account for
Sky exports the output signal for representing comparative result than calibration module RX_0 benchmark voltage signal VR and reference signal RS.
The input of the duty detection circuit 130 connects the output end of the dutycycle calibration module RX_0, and it is examined
The dutycycle of the output signal of the dutycycle calibration module RX_0 outputs is surveyed, and is not equal to percentage in the dutycycle of output signal
Output duty cycle calibration control signal DC when 50, it is defeated that the dutycycle calibration module RX_0 is based on duty detection circuit 130
The dutycycle calibration control signal DC gone out calibrates to the dutycycle calibration module RX_0, until obtaining accounting for for output signal
Empty ratio is equal to percentage 50.Specifically, when the dutycycle of output signal is not equal to percentage 50, the duty detection circuit
130 output duty cycles calibrate control signal DC, the dutycycle school that dutycycle calibration module 130 is exported based on duty detection circuit
Quasi- control signal adjusts to obtain one group of dutycycle calibration parameter, based on the obtained dutycycle calibration parameter of adjustment to the dutycycle
Calibration module RX_0 is calibrated, and when the dutycycle of output signal is equal to percentage 50, control signal is calibrated based on dutycycle
DC obtains one group of final dutycycle calibration parameter, based on the final dutycycle calibration parameter of the group to the dutycycle calibration module
RX_0 carries out calibration and enables to the dutycycle of output signal to be equal to 50 percent.
The structure of the input module RX_1 is to replicate dutycycle calibration module RX_0 structure, in the present invention, synchronous
, the input module RX_1 calibrates control signal to the input module also based on the dutycycle that duty detection circuit exports
RX_1 is calibrated.Finally accounted for specifically, the input module RX_1 also can obtain one group according to dutycycle calibration control signal
Sky is calibrated than calibration parameter based on the final dutycycle calibration parameter of the group to the input module RX_1.Input module RX_
1 comparison object input signal IN and reference voltage signal VR produces the target output signal for representing comparative result, target output
The dutycycle of signal distortion very little, target output signal compared with desired input signals IN dutycycle are supplied to application circuit
200 use.
As can be seen that because the structure of the input module RX_1 is to replicate dutycycle calibration module RX_0 structure, profit
Dutycycle calibration module RX_0 is calibrated with the reference signal RS of predetermined known dutycycle, synchronous is achieved that to input
Module RX_1 calibration, so as to eliminate or reduce the non-ideal factors such as the mismatch of the device in input module RX_1 to mesh
Influence caused by marking input signal IN Duty Cycle Distortion.
Fig. 2 is the structured flowchart of duty detection circuit 130 in one embodiment in the present invention.As shown in Figure 2,
The duty detection circuit 130 includes buffer BUF, phase inverter INV, first resistor R1, second resistance R2, the first electric capacity
C1, the second electric capacity C2, comparator 131 and control unit 132.
The input of the buffer BUF is connected with phase inverter INV input, the buffer BUF and described anti-phase
Device INV input receives the output signal from dutycycle calibration module RX_0 outputs.Buffer BUF output end passes through successively
It is connected by first resistor R1 and the first electric capacity C1 with earth terminal.Phase inverter INV output end is successively via second resistance R2 and
Two electric capacity C2 are connected with earth terminal.First resistor R1 and the first electric capacity C1 connection end and the first input end phase of comparator 131
Even.Second resistance R2 and the second electric capacity C2 connection end are connected with the second input of comparator 131, the output of comparator 131
End is connected with the input of control unit 132.Described control unit 132 is accounted for based on the comparative result output that comparator 131 exports
Sky is than calibration control signal.
When the dutycycle of the output signal of calibration is more than 50 percent, comparator 131 can export high level signal, this
When feel the need to adjust dutycycle calibration module RX_0 dutycycle to small direction, therefore described control unit 132
According to the corresponding dutycycle calibration control signal DC of the high level output, accordingly, the dutycycle calibration module RX_0 is according to this
Dutycycle calibration control signal DC adjusts its dutycycle calibration parameter, and then reduces its dutycycle calibration module RX_0 duty
Than；When the dutycycle of the output signal of calibration is less than 50 percent, comparator 131 can export low level signal, now recognize
To be necessary to adjust dutycycle calibration module RX_0 dutycycle to big direction, therefore described control unit 132 is according to this
The corresponding dutycycle calibration control signal DC of high level output, accordingly, the dutycycle calibration module RX_0 is according to the duty
Its dutycycle calibration parameter is adjusted than calibration control signal DC, and then increases its dutycycle calibration module RX_0 dutycycle.
In the present invention, locking discipline is set in described control unit 132, in lock-out state, described control unit 132
The dutycycle calibration control signal DC of output causes the dutycycle calibration module RX_0 no longer to adjust dutycycle calibration parameter.Than
Such as, lock-out state is entered when the output of comparator 131 is changed into low level from high level, for another example, in the output of comparator 131
Enter lock-out state when being changed into low level from high level.
Fig. 3 is the structure of duty-ratio calibrating circuit RX_0 or input module RX_1 in another embodiment in the present invention
Block diagram.In the present invention, duty-ratio calibrating circuit RX_0 structure can be with identical, simply with input module RX_1 structure
The size of device can be directly proportional.
The duty-ratio calibrating circuit RX_0 and input module RX_1 include input comparing unit 310, output driving electricity
Road 320 and output buffer cell 330.
It is described input comparing unit 310 include PMOS transistor MP0 and MP1, nmos pass transistor MN0, MN1, MN0B and
MN1B.PMOS transistor MP0 and MP1 source electrode is connected with power end, and PMOS transistor MP0 drain electrode is with nmos pass transistor MN0's
Drain electrode is connected, and PMOS transistor MP1 drain electrode is connected with nmos pass transistor MN1 drain electrode.Nmos pass transistor MN0, MN1, MN0B
It is connected with MN1B source electrode with earth terminal, nmos pass transistor MN0B drain electrode and nmos pass transistor MN0 drain electrode and NMOS are brilliant
Body pipe MN1B grid is connected, nmos pass transistor MN1B drain electrode and nmos pass transistor MN1 drain electrode and nmos pass transistor
MN0B grid is connected.PMOS transistor MP0 grid compares after being connected with nmos pass transistor MN0 grid as the input
The first input end of unit, the first input end receive reference signal RS or desired input signals IN, PMOS transistor MP1 grid
Pole terminates after being connected with nmos pass transistor MN1 grid as second input for inputting comparing unit, second input
Receive reference voltage signal VR.The node that transistor MP1 drain electrode is connected with transistor MN1 drain electrode is input comparing unit 310
Output end.The input comparing unit 310 is used for the signal for comparing the signal and the second input of its first input end, and leads to
Cross its output end output comparative result.
As shown in Figure 4, the output driving circuit 320 includes input I, is connected to power end V/I_SUPPLY and its
N number of first output driving unit 321 between output end O and be connected between its output end O and earth terminal VSS N number of second
Output driving unit 322, wherein N are more than or equal to 1.The input I is connected with inputting the output end of comparing unit 310, described
Output end O is connected with exporting the input of buffer cell 330, exports the output end of buffer cell 330 as dutycycle calibrating die
Block and the equal output end of input module.
Include being connected to power end V/I_SUPPLY and the output driving circuit in each first output driving unit
Output end O between the first controlling switch and PMOS transistor.Specifically, first the first output driving unit includes the first control
System switch SW1_0 and PMOS transistor PM1_0, second the first output driving unit include the first controlling switch SW1_1 and
PMOS transistor PM1_1, the 3rd the first output driving unit include the first controlling switch SW1_2 and PMOS transistor PM1_
2 ... ..., the first output driving of n-th unit includes the first controlling switch SW1_N-1 and PMOS transistor PM1_N-1.
Include being connected between output and ground nmos pass transistor and the in each second output driving unit 322
Two controlling switches.Specifically, first the second output driving unit includes the second controlling switch SW0_0 and nmos pass transistor NM0_
0, second the second output driving unit includes the second controlling switch SW0_1 and nmos pass transistor NM0_1, the 3rd second output
Driver element includes the second controlling switch SW0_2 and nmos pass transistor NM0_2 ... ..., and n-th the second output driving unit includes
Second controlling switch SW1_N-1 and nmos pass transistor NM1_N-1.
The NMOS of PMOS transistor and each second output driving unit 322 in each first output driving unit 321
The grid of transistor is connected jointly, forms the input I of the output driving circuit 320, in each first output driving unit 321
PMOS transistor and the nmos pass transistor of each second output driving unit 322 drain electrode it is common be connected after, form the output
The output end O of drive circuit 320.
The dutycycle calibration module RX_0 and the input module RX_1 are accounted for based on what duty detection circuit 130 exported
It is empty to control the on or off of the first controlling switch and the second controlling switch than calibration control signal, so as to by corresponding first
The output driving unit 322 of output driving unit 321 and second introducing output driving circuit 320 effectively drives from the output
Removed in dynamic circuit 320.The number of first controlling switch of conducting is bigger, and the driving force that it is pulled up is also bigger, can cause
The dutycycle of input signal is to directional distortion bigger than normal, and the number of the second controlling switch of conducting is bigger, its driving force pulled down
Also it is bigger, the dutycycle of input signal can be caused to directional distortion less than normal.
Based on such mode, the dutycycle that can be exported according to duty detection circuit calibrates control signal DC to adjust
First controlling switch and the number of the second controlling switch conducting, to realize to the dutycycle calibration module RX_0 and the input
Module RX_1 calibration, most it is adjusted to percent according to the accounting sky of the dutycycle calibration module RX_0 output signals exported at last
50.Now, the dutycycle of the reference signal of dutycycle calibration module RX_0 input is 50 percent, and its output signal
Dutycycle also be 50 percent, that is to say, that dutycycle calibration module RX_0 does not cause the dutycycle of input signal
Distortion.After calibration, input module RX_1 have with dutycycle calibration module RX_0 identical structures, input module RX_1 is not yet
The distortion of the dutycycle of input signal is caused, so as to eliminate or reduce the non-ideal factors such as the mismatch of device to input signal
Influence caused by Duty Cycle Distortion.
In one embodiment, the dutycycle calibration module RX_0 outputs are detected in duty detection circuit 130
When the dutycycle of output signal is less than 50 percent, output duty cycle is calibrated control signal and opened with increasing by the first of conducting the control
The number of pass and/or the number for reducing the second controlling switch turned on；The dutycycle is detected in duty detection circuit 130
When the dutycycle of the output signal of calibration module RX_0 outputs is higher than 50 percent, output duty cycle calibrates control signal to subtract
The number of the number of the first controlling switch turned on less and/or the second controlling switch of increase conducting.After locking, the duty
Than first controlling switch conductings of the calibration module RX_0 based on dutycycle calibration control signal control predetermined number and predetermined number
The conducting of the second controlling switch, the dutycycle of the output signal of now dutycycle calibration module RX_0 output is approximately equal to hundred
/ five ten.Synchronous, the input module RX_1 can also calibrate the first of control signal control predetermined number based on dutycycle
Controlling switch turn on and predetermined number the second controlling switch turn on, so as to eliminate or reduce the mismatch of device etc. it is non-ideal because
Element influence to caused by the Duty Cycle Distortion of input signal.
In the present invention, the dutycycle of input signal caused by reducing input circuit using system self-calibration method is lost
Very, time margin is optimized, so as to support higher input circuit working frequency.The present invention requires to reduce to the matching degree of device,
The input capacitance of input circuit is reduced, so as to improve incoming frequency, reduces chip area.
In the present invention, the word that the expression such as " connection ", " connected ", " company ", " connecing " is electrically connected with, unless otherwise instructed,
Then represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art is done to the embodiment of the present invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (8)
1. a kind of input circuit that the Duty Cycle Distortion of desired input signals can be compensated, it is characterised in that it includes：
Dutycycle calibration module, its reference signal based on predetermined duty cycle produce output signal；
Duty detection circuit, its input connect the output end of the dutycycle calibration module, and it detects the dutycycle school
The dutycycle of the output signal of quasi-mode block output, and export and account for when the dutycycle of the output signal is not equal to predetermined duty cycle
Sky calibrates control signal than calibration control signal, wherein dutycycle calibration module based on the dutycycle that duty detection circuit exports
Dutycycle calibration module is calibrated, until the dutycycle of obtained output signal is equal to predetermined duty cycle；
The input module for replicating the structure of dutycycle calibration module and being formed, its duty also based on duty detection circuit output
Input module is calibrated than calibration control signal.
2. the input circuit according to claim 1 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by, the predetermined duty cycle is 50 percent,
The input circuit also includes：
Reference voltage generating circuit, it produces reference voltage signal；
Reference signal generation circuit, it produces the reference signal of predetermined duty cycle,
Wherein, the first input end of dutycycle calibration module is connected with the reference signal of the predetermined duty cycle, the second input
The reference voltage signal is received, its more described reference signal and the reference voltage signal simultaneously export and represent comparative result
Output signal, the first input end of the input module are connected with the desired input signals, and the second input receives the base
Quasi- voltage signal, its more described desired input signals and the reference voltage signal and export represent comparative result target it is defeated
Go out signal；
Dutycycle calibration module is adjusted based on the dutycycle calibration control signal that duty detection circuit exports and is obtained one group and accounted for
Sky is than calibration parameter, and the dutycycle calibration parameter obtained based on adjustment is calibrated to dutycycle calibration module, based on duty
Than obtaining one group of final dutycycle calibration parameter under calibrating the continuous adjustment of control signal, based on the final dutycycle calibration ginseng of the group
It is several dutycycle calibration module to be calibrated to cause the dutycycle of its output signal exported to be equal to predetermined duty cycle.
3. the input circuit according to claim 1 that the Duty Cycle Distortion of desired input signals can be compensated, its
Be characterised by, duty detection circuit include buffer, phase inverter, first resistor, second resistance, the first electric capacity, the second electric capacity,
Comparator and control unit,
The input of the buffer is connected with the input of phase inverter, and the input of the buffer and the phase inverter receives
Output signal from the output of dutycycle calibration module；
The output end of buffer is connected via first resistor and the first electric capacity with earth terminal successively,
The output end of phase inverter is connected via second resistance and the second electric capacity with earth terminal successively,
The connection end of first resistor and the first electric capacity is connected with the first input end of comparator,
The connection end of second resistance and the second electric capacity is connected with the second input of comparator, and the output end of comparator and control are single
The input of member is connected,
Described control unit calibrates control signal based on the comparative result output duty cycle that comparator exports.
4. the input circuit according to claim 1 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by,
Dutycycle calibration module and input module include output driving circuit, and the output driving circuit includes input, connected
Multiple first output driving units for being connected between power end and its output end and it is connected between its output and ground
Multiple second output driving units,
Include being connected between the output end of power end and the output driving circuit the in each first output driving unit
One controlling switch and PMOS transistor, include in each second output driving unit being connected between output and ground
Nmos pass transistor and the second controlling switch, PMOS transistor and each second output driving in each first output driving unit
The grid of the nmos pass transistor of unit is connected jointly, forms the input of the output driving circuit, each first output driving list
After PMOS transistor in member is connected jointly with the drain electrode of the nmos pass transistor of each second output driving unit, the output is formed
The output end of drive circuit, by controlling the on or off of the first controlling switch and the second controlling switch can be by where it
The introducing output driving circuit or electric from the output driving of first output driving unit and the second output driving unit effectively
Removed in road,
Based on the first controlling switch for turning in dutycycle calibration control signal control dutycycle calibration module and input module and
The number of second controlling switch, to realize the calibration to dutycycle calibration module and input module.
5. the input circuit according to claim 4 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by,
The dutycycle calibration module and input module also include output buffer cell, the input of the output buffer cell
It is connected with the output end of the output driving circuit, the output equal as dutycycle calibration module and input module of its output end
End.
6. the input circuit according to claim 4 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by,
Detect that the dutycycle of the output signal of the dutycycle calibration module output accounts for less than predetermined in duty detection circuit
It is empty than when, output duty cycle calibrates control signal to increase the number of the first controlling switch of conducting and/or reduce the of conducting
The number of two controlling switches；
Detect that the dutycycle of the output signal of the dutycycle calibration module output accounts for higher than predetermined in duty detection circuit
It is empty than when, output duty cycle calibrates control signal to reduce the of the number of the first controlling switch of conducting and/or increase conducting
The number of two controlling switches.
7. the input circuit according to claim 4 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by,
The dutycycle calibration module and input module also include input comparing unit, described to input the first of comparing unit
Input connects the reference signal or desired input signals of predetermined duty cycle, the second input connection of the input comparing unit
One reference voltage signal, the output end of the input comparing unit are connected with the input of the output driving circuit.
8. the input circuit according to claim 7 that the Duty Cycle Distortion of desired input signals can be compensated, its
It is characterised by,
The input comparing unit includes PMOS transistor MP0 and MP1, nmos pass transistor MN0, MN1, MN0B and MN1B,
PMOS transistor MP0 and MP1 source electrode is connected with power end, PMOS transistor MP0 drain electrode and nmos pass transistor MN0 leakage
Extremely it is connected, PMOS transistor MP1 drain electrode is connected with nmos pass transistor MN1 drain electrode,
Nmos pass transistor MN0, MN1, MN0B and MN1B source electrode are connected with earth terminal, nmos pass transistor MN0B drain electrode and NMOS
Transistor MN0 drain electrode and nmos pass transistor MN1B grid are connected, nmos pass transistor MN1B drain electrode and nmos pass transistor
MN1 drain electrode and nmos pass transistor MN0B grid are connected,
PMOS transistor MP0 grid be connected with nmos pass transistor MN0 grid after as it is described input comparing unit first
Input,
PMOS transistor MP1 grid be connected with nmos pass transistor MN1 grid after as it is described input comparing unit second
Input,
The node that PMOS transistor MP1 drain electrode is connected with nmos pass transistor MN1 drain electrode is the output end of input comparing unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510270232.3A CN104836548B (en) | 2015-05-25 | 2015-05-25 | The input circuit that the Duty Cycle Distortion of input signal can be compensated |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510270232.3A CN104836548B (en) | 2015-05-25 | 2015-05-25 | The input circuit that the Duty Cycle Distortion of input signal can be compensated |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105958971A (en) * | 2016-06-02 | 2016-09-21 | 泰凌微电子（上海）有限公司 | Clock duty ratio calibration circuit |
| CN111273726B (en) * | 2018-12-05 | 2021-06-29 | 锐迪科（重庆）微电子科技有限公司 | Duty ratio deviation compensation circuit, method and chip |
| CN112669890A (en) * | 2019-10-16 | 2021-04-16 | 长鑫存储技术有限公司 | Output driving circuit and memory |
| CN113452978B (en) * | 2021-06-28 | 2023-01-17 | 深圳银星智能集团股份有限公司 | Obstacle detection method and electronic equipment |
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| US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
| CN1815887A (en) * | 2005-02-03 | 2006-08-09 | 尔必达存储器株式会社 | Duty detection circuit |
| CN101068109A (en) * | 2006-05-01 | 2007-11-07 | 国际商业机器公司 | Method and apparatus for correcting the duty cycle of a digital signal |
| CN103312299A (en) * | 2012-03-05 | 2013-09-18 | 联发科技（新加坡）私人有限公司 | Signal duty cycle detector and calibration system |
| CN204578496U (en) * | 2015-05-25 | 2015-08-19 | 灿芯半导体(上海)有限公司 | The input circuit that can compensate the Duty Cycle Distortion of input signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8644085B2 (en) * | 2011-04-05 | 2014-02-04 | International Business Machines Corporation | Duty cycle distortion correction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
| CN1815887A (en) * | 2005-02-03 | 2006-08-09 | 尔必达存储器株式会社 | Duty detection circuit |
| CN101068109A (en) * | 2006-05-01 | 2007-11-07 | 国际商业机器公司 | Method and apparatus for correcting the duty cycle of a digital signal |
| CN103312299A (en) * | 2012-03-05 | 2013-09-18 | 联发科技（新加坡）私人有限公司 | Signal duty cycle detector and calibration system |
| CN204578496U (en) * | 2015-05-25 | 2015-08-19 | 灿芯半导体(上海)有限公司 | The input circuit that can compensate the Duty Cycle Distortion of input signal |
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Denomination of invention: Input circuit compensating duty ratio distortion of input signal Effective date of registration: 20180420 Granted publication date: 20171110 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
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