TWI749979B - Control circuit and operation system - Google Patents

Abstract

A control circuit including a timer circuit and a voltage monitor module is provided. When a wakeup event occurs, the timer circuit asserts a trigger signal at regular time intervals. The voltage monitor module is configured to monitor whether an operation voltage reaches a predetermined value. The voltage monitor module includes a signal generator circuit, a first delay circuit, a second delay circuit and a decision circuit. The signal generator circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operation voltage and delays the reference signal to generate a first delayed signal. The second delay circuit delays the trigger signal to generate a second delayed signal. When the wakeup event occurs. The decision circuit enables a wakeup signal according to the reference signal, the first delayed signal, and the second delayed signal.

Description

Control circuit and operating system

The present invention relates to a control circuit, in particular to a control circuit that monitors whether an operating voltage reaches an expected voltage.

With the advancement of technology, there are more and more types and functions of electronic products. There are many electronic components inside the electronic product. In order to reduce the power consumption caused by the electronic components, when the electronic components have not been used for a long time, the electronic components enter a power saving mode. In the power saving mode, the operating voltage of the electronic component may be a standby voltage, such as 0V. When a wake-up event occurs, the operating voltage gradually rises from the standby voltage. Before the operating voltage reaches a stable voltage, if the electronic component operates according to the operating voltage, it may cause the electronic component to malfunction. In addition, when multiple operating voltages are increased at the same time, inrush current may be caused, which may damage electronic components.

An embodiment of the present invention provides a control circuit including a timing circuit and a voltage monitoring module. When a wake-up event occurs, the timing circuit enables a trigger signal at regular intervals. The voltage monitoring module is used to monitor whether an operating voltage reaches an expected voltage, and includes a signal generating circuit, a first delay circuit, a second delay circuit, and a judgment circuit. The signal generating circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operating voltage and delays the reference signal to generate a first delay signal. The second delay circuit delays the trigger signal to generate a second delay signal. When a wake-up event occurs, the judgment circuit enables a wake-up signal according to the reference signal, the first delay signal and the second delay signal.

Another embodiment of the present invention provides an operating system including a micro-control circuit and a control circuit. The micro-control circuit receives an operating voltage. When the operating voltage is less than an expected voltage, the micro-control circuit enters a sleep mode. When a wake-up signal is enabled, the micro-control circuit leaves the sleep mode and enters a normal mode. In the normal mode, the micro-control circuit operates according to the operating voltage. When a wake-up event occurs, the control circuit determines whether the operating voltage reaches the expected voltage. When the operating voltage reaches the expected voltage, the control circuit enables the wake-up signal. The control circuit includes a timing circuit and a voltage monitoring module. When a wake-up event occurs, the timing circuit enables a trigger signal at regular intervals. The voltage monitoring module monitors whether the operating voltage reaches the expected voltage according to the trigger signal. When the operating voltage reaches the expected voltage, the voltage monitoring module enables a wake-up signal.

In order to make the purpose, features and advantages of the present invention more comprehensible, the following specific examples are given in conjunction with the accompanying drawings for detailed descriptions. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, part of the repetition of the symbols of the drawings in the embodiments is for simplifying the description, and does not imply the relevance between different embodiments.

Figure 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes a control circuit 110 and a micro-control circuit 120. The control circuit 110 determines whether a wake-up event has occurred. In this embodiment, the control circuit 110 determines whether a wake-up event occurs according to the level of an external signal SLEEP. For example, when the level of the external signal SLEEP is not equal to a specific level (such as a low level), it means that no wake-up event has occurred. Therefore, the control circuit 110 cannot enable the wake-up signal WKU. At this time, the wake-up signal WKU may be equal to a first level, such as a high level. When the external signal SLEEP is equal to a specific level, it indicates that a wake-up event has occurred. Therefore, the control circuit 110 determines whether an operating voltage VDDR reaches a first expected voltage. When the operating voltage VDDR reaches the first expected voltage, the control circuit 110 enables the wake-up signal WKU. At this time, the wake-up signal WKU may be equal to a second level, such as a low level.

In this embodiment, the control circuit 110 includes a timing circuit 111 and a voltage monitoring module 112. The timing circuit 111 is used to determine whether a wake-up event has occurred. When a wake-up event occurs, the timing circuit 111 enables a trigger signal TMO every fixed time (for example, 1 second). When the wake-up event does not occur, the timing circuit 111 does not enable the trigger signal TMO. The voltage monitoring module 112 is used to monitor whether the operating voltage VDDR reaches a first expected voltage. When the trigger signal TMO is enabled, the voltage monitoring module 112 detects whether the operating voltage VDDR reaches a first expected voltage. When the operating voltage VDDR reaches the first expected voltage, the voltage monitoring module 112 enables the wake-up signal WKU. When the operating voltage VDDR does not reach the first expected voltage, the voltage monitoring module 112 does not enable the wake-up signal WKU.

In another embodiment, the timing circuit 111 further delays the external signal SLEEP to generate a delay signal SL_latch. In this example, the voltage monitoring module 112 determines whether to enable the wake-up signal WKU according to the operating voltage VDDR and the delay signal SL_latch. For example, when the operating voltage VDDR reaches the first expected voltage, if the delay signal SL_latch is not equal to a specific level (such as a low level), the voltage monitoring module 112 does not enable the wake-up signal WKU. In addition, when the delay signal SL_latch is equal to a specific level, if the operating voltage VDDR does not reach the first expected voltage, the voltage monitoring module 112 will not be able to wake up the signal WKU. In this example, when the delay signal SL_latch is equal to a certain level and the operating voltage VDDR reaches the first expected voltage, the voltage monitoring module 112 enables the wake-up signal WKU.

In other embodiments, regardless of whether the wake-up event occurs, the timing circuit 111 enables a trigger signal TMO every fixed time (eg, 1 second). In this example, the voltage monitoring module 112 detects whether a wake-up event occurs and monitors whether the operating voltage VDDR reaches a first expected voltage. In a possible embodiment, the voltage monitoring module 112 determines whether the wake-up event occurs according to the level of the external signal SLEEP. In addition, the voltage monitoring module 112 compares the monitored operating voltage VDDR with the first expected voltage to determine whether the operating voltage VDDR reaches the first expected voltage. For example, when the trigger signal TMO is enabled, the voltage monitoring module 112 determines whether the operating voltage VDDR reaches the first expected voltage. When the operating voltage VDDR reaches the first expected voltage, the voltage monitoring module 112 determines whether the level of the external signal SLEEP is equal to a specific level. When the level of the external signal SLEEP is equal to the specific level, the voltage monitoring module 112 enables the wake-up signal WKU. However, when the operating voltage VDDR does not reach the first expected voltage or the level of the external signal SLEEP is not equal to the specific level, the voltage monitoring module 112 does not enable the wake-up signal WKU.

The present invention does not limit the sequence in which the voltage monitoring module 112 monitors the external signal SLEEP and the operating voltage VDDR. In a possible embodiment, the voltage monitoring module 112 first determines whether the operating voltage VDDR has reached the first expected voltage, and only after the operating voltage VDDR reaches the first expected voltage, does it determine whether the level of the external signal SLEEP is equal to a specific level . In another possible embodiment, the voltage monitoring module 112 first determines whether the level of the external signal SLEEP is equal to a specific level. In this example, when the level of the external signal SLEEP is equal to the specific level, the voltage monitoring module 112 determines whether the operating voltage VDDR has reached the first expected voltage. In other embodiments, the voltage monitoring module 112 may directly receive the external signal SLEEP to determine whether the level of the external signal SLEEP is equal to a specific level. In another possible embodiment, the voltage monitoring module 112 delays the external signal SLEEP, and then determines whether the delay signal is equal to a specific level.

The micro-control circuit 120 receives the operating voltage VDDR and the wake-up signal WKU. When the operating voltage VDDR is less than the first expected voltage, the micro-control circuit 120 enters a sleep mode. In the sleep mode, since the operating voltage VDDR is insufficient to drive the micro-control circuit 120, the micro-control circuit 120 stops operating. When the wake-up signal WKU is enabled, the micro-control circuit 120 leaves the sleep mode and enters a normal mode. In the normal mode, the operating voltage VDDR has recovered to the first expected voltage (or even greater than the first expected voltage), so the micro-control circuit 120 can be driven. Therefore, the micro-control circuit 120 performs corresponding actions.

The invention does not limit the type of the micro-control circuit 120. In a possible embodiment, the micro-control circuit 120 may be a microprocessor. In another possible embodiment, the micro-control circuit 120 is another control circuit (similar to the control circuit 110). In this example, when the wake-up signal WKU is enabled, the micro-control circuit 120 determines whether the other operating voltage VDDQ reaches a second expected voltage. When the operating voltage VDDQ reaches the second expected voltage, the micro-control circuit 120 enables another wake-up signal (not shown). In this example, the wake-up signal enabled by the micro-control circuit 120 may be used to wake up another control circuit to determine whether another operating voltage (different from VDDR and VDDQ) has reached a corresponding expected voltage. In other embodiments, the wake-up signal enabled by the micro-control circuit 120 may be used to wake-up a load circuit, such as a microcontroller (Microcontroller Unit; MCU).

Figure 2 is a possible schematic diagram of the voltage monitoring module of the present invention. As shown in the figure, the voltage monitoring module 200 includes a signal generating circuit 210, delay circuits 220 and 240, and a judgment circuit 230. The signal generating circuit 210 generates a reference signal Q1 according to the trigger signal TMO. In this embodiment, the signal generating circuit 210 includes an inverter 211 and a D-type flip-flop 212. The inverter 211 is coupled between the input terminal D and the output terminal Q of the D-type flip-flop 212. In this example, the inverter 211 inverts the reference signal Q1 and provides the inverted result to the input terminal D of the D-type flip-flop 212. The clock terminal CK of the D-type flip-flop 212 receives the trigger signal TMO. When the trigger signal TMO is enabled, the D-type flip-flop 212 transmits the signal from the input terminal D to the output terminal Q. In a possible embodiment, when the trigger signal TMO is enabled, the trigger signal TMO changes from a low level to a high level. In another possible embodiment, when the trigger signal TMO is enabled, the trigger signal TMO changes from a high level to a low level. In other embodiments, the initial level of the reference signal Q1 is a low level.

The delay circuit 220 receives the operating voltage VDDR and delays the reference signal Q1 to generate a delay signal Q1_delay. In this embodiment, when the operating voltage VDDR is smaller, the response time of the delay circuit 220 is longer. Therefore, the delay circuit 220 needs more time to generate the delay signal Q1_delay. However, when the operating voltage VDDR gradually rises, the response time of the delay circuit 220 gradually becomes shorter. When the operating voltage VDDR reaches an expected voltage or is higher than the expected voltage, the delay time between the reference signal Q1 and the delay signal Q1_delay is maintained at a fixed value, where the delay time between the reference signal Q1 and the delay signal Q1_delay is called a The first delay time.

In other embodiments, the delay circuit 220 adjusts the first delay time according to an adjustment signal Tune_2. In this example, the delay circuit 220 may have ten stages of delay elements. The designer of the voltage monitoring module 200 uses the adjustment signal Tune_2 to trigger the first to fourth stage delay elements of the delay circuit 220. At this time, the total delay time of the first to fourth stage delay elements is the first delay time.

The delay circuit 240 delays the trigger signal TMO to generate a delay signal TMO_delay. In this embodiment, the delay circuit 240 receives an operating voltage VDD. In this example, even if the operating voltage VDDR drops to a standby voltage, the operating voltage VDD is maintained at a fixed value. For example, when the micro-control circuit 120 in FIG. 1 enters a sleep mode, the operating voltage VDDR drops to a standby voltage (such as 0V). At this time, the operating voltage VDD is maintained at a fixed value (for example, 1.8V). When the micro control circuit 120 leaves the sleep mode and enters the normal mode, the operating voltage VDDR gradually rises. At this time, the operating voltage VDD is still maintained at a fixed value. In other words, regardless of whether the micro-control circuit 120 is operating in the sleep mode or the normal mode, the operating voltage VDD remains unchanged (for example, maintained at 1.8V).

In other embodiments, the delay circuit 240 adjusts the delay time between the trigger signal TMO and the delay signal TMO_delay according to an adjustment signal Tune_1, or is referred to as a second delay time. In this example, the delay circuit 240 may have ten stages of delay elements, and the designer of the voltage monitoring module uses the adjustment signal Tune_1 to trigger the first to fifth stages of delay elements of the delay circuit 240. At this time, the total delay time of the first to fifth stage delay elements is used as the second delay time. The second delay time may be the same or different from the first delay time.

The judgment circuit 230 judges whether the level of the reference signal Q1 is equal to the level of the delay signal Q1_delay according to the delay signal TMO_delay. For example, when the level of the delay signal TMO_delay changes from a first level to a second level, the determining circuit 230 determines whether the reference signal Q1 is equal to the delay signal Q1_delay. When the level of the reference signal Q1 is equal to the level of the delay signal Q1_delay, it indicates that the operating voltage VDDR has risen from a standby voltage (such as 0V) to an expected voltage. Therefore, the judgment circuit 230 enables the wake-up signal WKU according to the level of the external signal SLEEP (or the delay signal SL_latch). In this embodiment, the judgment circuit 230 includes logic circuits 231 and 232 and a D-type flip-flop 233.

The logic circuit 231 receives the reference signal Q1 and the delay signal Q1_delay to generate an output signal CKO. In this embodiment, when the reference signal Q1 is equal to the delay signal Q1_delay, the output signal CKO is equal to a first level, and when the reference signal Q1 is not equal to the delay signal Q1_delay, the output signal CKO is equal to a second level. The second level is relative to the first level. For example, when the first level is a low level, the second level is a high level. When the first level is a high level, the second level is a low level. The present invention does not limit the structure of the logic circuit 231. In this embodiment, the logic circuit 231 is an XOR gate.

The input terminal D of the D-type flip-flop 233 receives the output signal CKO, the clock terminal CK receives the delay signal TMO_delay, and the output terminal Q of the D-type flip-flop 233 is used to provide a judgment signal Q2. In this embodiment, when the level of the delay signal TMO_delay changes from the first level to the second level, the D-type flip-flop 233 uses the output signal CKO as a judgment signal Q2. In a possible embodiment, when the judgment signal Q2 is equal to the first level (such as the low level), it means that the level of the reference signal Q1 is equal to the level of the delay signal Q1_delay. When the judgment signal Q2 is equal to the second level (for example, the high level), it means that the level of the reference signal Q1 is not equal to the level of the delay signal Q1_delay.

The logic circuit 232 is coupled to the output terminal Q of the D-type flip-flop 233 for receiving the judgment signal Q2. In this embodiment, the logic circuit 232 determines whether to enable the wake-up signal WKU according to the level of the judgment signal Q2 and the external signal SLEEP. For example, when the external signal SLEEP is equal to a specific level (such as a low level), it indicates that a wake-up event has occurred. At this time, if the judgment signal Q2 is equal to the first level (such as the low level), the logic circuit 232 enables the wake-up signal WKU. However, when the judgment signal Q2 is equal to the second level (such as the high level), even if a wake-up event occurs, the logic circuit 232 cannot enable the wake-up signal WKU.

In another embodiment, when the external signal SLEEP is not equal to a specific level, it means that a wake-up event has not occurred. Therefore, the logic circuit 232 cannot enable the wake-up signal WKU. At this time, even if the judgment signal Q2 is equal to the first level, the logic circuit 232 cannot enable the wake-up signal WKU. The present invention does not limit the structure of the logic circuit 232. In a possible embodiment, the logic circuit 232 is an OR gate.

In other embodiments, the logic circuit 232 determines whether to enable the wake-up signal WKU according to the levels of the determination signal Q2 and the delay signal SL_latch. In this example, the delay signal SL_latch is the delay signal of the external signal SLEEP. The delay signal SL_latch may be generated by an external device (such as the timing circuit 111). In some embodiments, the voltage monitoring module 200 further includes a delay circuit (not shown). The delay circuit receives and delays the external signal SLEEP to generate the delay signal SL_latch.

When the delay signal SL_latch is equal to a specific level, it indicates that a wake-up event has occurred. At this time, if the judgment signal Q2 is equal to the first level (such as the low level), the logic circuit 232 enables the wake-up signal WKU. However, when the judgment signal Q2 is equal to the second level (such as the high level), even if a wake-up event occurs, the logic circuit 232 cannot enable the wake-up signal WKU. In another embodiment, when the delay signal SL_latch is not equal to a specific level, it means that a wake-up event has not occurred. Therefore, the logic circuit 232 cannot enable the wake-up signal WKU. At this time, even if the judgment signal Q2 is equal to the first level, the logic circuit 232 cannot enable the wake-up signal WKU.

Figure 3 is a schematic diagram of the signals of the voltage monitoring module shown in Figure 2. When a wake-up event occurs, the level of the external signal SLEEP changes. In a possible embodiment, the external signal SLEEP changes from a high level to a low level, but it is not intended to limit the present invention. In other embodiments, when a wake-up event occurs, the external signal SLEEP changes from a low level to a high level.

Since the external signal SLEEP is equal to a specific level (such as a low level), the timing circuit 111 starts a timing operation. In this embodiment, the timing circuit 111 enables the trigger signal TMO every fixed time TF1. When the trigger signal TMO is enabled, the level of the trigger signal TMO changes, such as changing from a low level to a high level and maintaining a fixed time TF2, and then returning from the high level to the low level. Then, the timing circuit 111 performs a timing operation again.

When the trigger signal TMO is enabled, the level of the reference signal Q1 changes. In this embodiment, the initial level of the reference signal Q1 is a low level. Therefore, when the trigger signal TMO is enabled, the reference signal Q1 changes from a low level to a high level, and remains at a high level until the trigger signal TMO is enabled again. In other embodiments, if the initial level of the reference signal Q1 is a high level, when the trigger signal TMO is enabled, the reference signal Q1 changes from a high level to a low level.

Since the delay circuit 220 delays the reference signal Q1, the delay signal Q1_delay lags behind the reference signal Q1. In this embodiment, since the delay circuit 220 receives the operating voltage VDDR, when the operating voltage VDDR gradually rises, the delay time between the delay signal Q1_delay and the reference signal Q1 gradually decreases. When the operating voltage VDDR reaches a desired voltage, the delay time between the delay signal Q1_delay and the reference signal Q1 is maintained at a fixed value.

In addition, since the delay circuit 240 delays the trigger signal TMO, the delay signal TMO_delay lags behind the trigger signal TMO. At time a, since the delay signal TMO_delay changes from a low level to a high level, the determining circuit 230 determines whether the level of the reference signal Q1 is the same as the level of the delay signal Q1_delay. At this time, since the level of the reference signal Q1 is different from the level of the delay signal Q1_delay, the level of the judgment signal Q2 remains unchanged. In this embodiment, the judgment signal Q2 is maintained at a high level.

At time b, since the delay signal TMO_delay changes from a low level to a high level again, the determining circuit 230 again determines whether the level of the reference signal Q1 is the same as the level of the delay signal Q1_delay. At this time, since the level of the reference signal Q1 is the same as the level of the delay signal Q1_delay, it indicates that the operating voltage VDDR has reached an expected voltage. therefore. The level of the judgment signal Q2 changes. At this time, the wake-up signal WKU is enabled.

The present invention does not limit the level when the wake-up signal WKU is enabled. In a possible embodiment, when the wake-up signal WKU is enabled, the wake-up signal WKU is also equal to a specific level (such as a low level). In this embodiment, there is a delay time between the wake-up signal WKU and the external signal SLEEP, where the delay time depends on the time for the operating voltage VDDR to reach an expected voltage. For example, when the operating voltage VDDR reaches the expected voltage, the longer the delay time between the wake-up signal WKU and the external signal SLEEP is.

Figure 4A is a schematic diagram of the timing circuit of the present invention. As shown in the figure, the timing circuit 400 includes a counting circuit 410, a judging circuit 420, and a reset circuit 440. The counting circuit 410 determines whether a wake-up event occurs according to the level of the external signal SLEEP. In this embodiment, the counting circuit 410 includes a judging circuit 411 and a counter 412. The judging circuit 411 receives a clock signal CLK, and determines whether to provide the clock signal CLK to the counter 412 according to the external signal SLEEP. For example, when the external signal SLEEP is equal to a specific level, it indicates that a wake-up event has occurred. Therefore, the judging circuit 411 outputs the clock signal CLK to the counter 412. However, when the external signal SLEEP is not equal to a specific level, it means that no wake-up event has occurred. Therefore, the judging circuit 411 does not output the clock signal CLK to the counter 412.

The counter 412 performs a counting operation according to the clock signal CLK to adjust a count value VLC. The invention does not limit the type of the counter 412. In one possible embodiment, the counter 412 is an up counter. In another possible embodiment, the counter 412 is a down counter.

The judging circuit 420 judges whether the count value VLC reaches a target value VLT. When the count value VLC reaches the target value VLT, it means that the duration of the counting operation performed by the counter 412 has reached a preset value (for example, the fixed time TF1 in FIG. 3). Therefore, the judgment circuit 420 enables the trigger signal TMO. When the count value VLC does not reach the target value VLT, it means that the duration of the counting operation performed by the counter 412 has not reached a preset value. Therefore, the judgment circuit 420 cannot enable the trigger signal TMO. In one possible embodiment, the timing circuit 400 further includes a register 430 for storing the target value VLT. The register 430 sets its own value according to a setting signal SET. The judgment circuit 420 reads the register 430 and the counter 412 to obtain the target value VLT and the count value VLC.

The reset circuit 440 resets the counter 412 according to the trigger signal TMO, so that the count value VLC returns to an initial value. In this embodiment, when the determination circuit 420 enables the trigger signal TMO, it indicates that the duration of the counting operation performed by the counter 412 has reached a fixed time. Therefore, the reset circuit 440 resets the counter 412. The present invention does not limit the structure of the reset circuit 440. In a possible embodiment, the reset circuit 440 includes a logic circuit 441. The logic circuit 441 inverts the trigger signal TMO to generate an inverted signal TMO_inv. The present invention does not limit the structure of the logic circuit 441. The logic circuit 441 may be a NOT gate.

Figure 4B is another schematic diagram of the timing circuit of the present invention. Fig. 4B is similar to Fig. 4A, except that Fig. 4B has an additional delay circuit 450. The delay circuit 450 is coupled to the judgment circuit 420. When the trigger signal TMO is enabled, the delay circuit 450 delays the external signal SLEEP to generate a delay signal SL_latch (or called a latch signal). The invention does not limit the structure of the delay circuit 450. In a possible embodiment, the delay circuit 450 is a D-type flip-flop 451. The input terminal D of the D-type flip-flop 451 receives the external signal SLEEP. The clock terminal CK of the D-type flip-flop 451 receives the trigger signal TMO. The output terminal Q of the D-type flip-flop 451 provides the delay signal SL_latch.

In addition, the reset circuit 440 in FIG. 4B further includes logic circuits 442 and 443. The logic circuit 443 inverts the external signal SLEEP to generate an inverted signal SL_inv. In one possible embodiment, the logic circuit 443 is a flip-flop. The logic circuit 442 enables a reset signal CLR according to the inverted signals SL_inv and TMO_inv. For example, when one of the inverted signals SL_inv and TMO_inv is equal to a specific level, the logic circuit 442 enables the reset signal CLR to reset the counter 412. When the inverted signals SL_inv and TMO_inv are not equal to a specific level, the logic circuit 442 does not enable the reset signal CLR. In one possible embodiment, the logic circuit 442 is an AND gate.

Fig. 5 is a signal schematic diagram of the counting circuit in Fig. 4B. In a possible embodiment, when the register 430 receives the setting signal SET, the register 430 stores a value (such as 2). In this example, the target value VLT is the value 2. When the external signal SLEEP is not equal to a specific level (such as a low level), the determining circuit 411 does not output the clock signal CLK to the counter 412. Therefore, the output signal O411 of the judgment circuit 411 remains unchanged, such as at a low level.

When the external signal SLEEP is equal to a specific level, it indicates that a wake-up event has occurred. Therefore, the judging circuit 411 outputs the clock signal CLK to the counter 412. At this time, the output signal O411 of the judgment circuit 411 is equal to the clock signal CLK. After the counter 412 receives the clock signal CLK, the counter 412 starts a counting operation and adjusts the count value VLC. When the count value VLC is equal to the value 2, the trigger signal TMO is enabled, and the reset circuit 440 resets the count value VLC. Therefore, the count value VLC returns to an initial value, such as zero. In addition, when the trigger signal TMO is enabled, the delay circuit 450 sets the level of the delay signal SL_latch to be equal to the level of the external signal SLEEP (such as a low level).

Since the counting circuit 400 enables the trigger signal TMO at regular intervals (that is, the time when the count value VLC of the counter 412 increases from a value of 0 to a value of 2), the voltage monitoring module at the back end can activate the trigger signal TMO when the trigger signal TMO is enabled. It is determined whether the operating voltage VDDR reaches an expected voltage. When the operating voltage VDDR reaches an expected voltage, the voltage monitoring module enables a wake-up signal WKU to wake up the subsequent circuit (ie, the circuit that receives the wake-up signal WKU). When the subsequent circuit operates according to the operating voltage VDDR, since the operating voltage VDDR has reached an expected voltage, the subsequent malfunction of the circuit can be avoided.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in an article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice. Although terms such as "first" and "second" can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method described in the embodiment of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

100: operating system 110: control circuit 120: Micro control circuit SLEEP: external signal WKU: Wake-up signal 111, 400: timing circuit 112, 200: Voltage monitoring module TMO: trigger signal VDDR: Operating voltage SL_latch: Delayed signal VDDQ: operating voltage 210: signal generating circuit 220, 240, 450: delay circuit 230, 411, 420: judgment circuit Q1: Reference signal Q2: Judgment signal 211: Inverter 212, 233, 451: D-type flip-flop Q1_delay, TMO_delay: Delay signal Tune_1, Tune_2: adjust the signal 231, 232, 441~443: logic circuit CKO: output signal 410: Counting Circuit 412: Counter 430: register 440: reset circuit VLT: target value VLC: count value SL_inv, TMO_ivn: inverted signal

Figure 1 is a schematic diagram of the operating system of the present invention. Figure 2 is a possible schematic diagram of the voltage monitoring module of the present invention. Figure 3 is a schematic diagram of the signals of the voltage monitoring module of the present invention. Figure 4A is a schematic diagram of the timing circuit of the present invention. Figure 4B is another schematic diagram of the timing circuit of the present invention. Fig. 5 is a signal schematic diagram of the counting circuit in Fig. 4B.

100: operating system

110: control circuit

120: Micro control circuit

SLEEP: external signal

WKU: Wake-up signal

111: Timing circuit

112: Voltage monitoring module

TMO: trigger signal

VDDR, VDDQ: operating voltage

SL_latch: Delayed signal

Claims (10)

A control circuit, including: A timing circuit that enables a trigger signal at regular intervals when a wake-up event occurs; and A voltage monitoring module is used to monitor whether an operating voltage reaches an expected voltage, and includes: A signal generating circuit generates a reference signal according to the trigger signal; A first delay circuit that receives the operating voltage and delays the reference signal to generate a first delay signal; A second delay circuit for delaying the trigger signal to generate a second delay signal; and A first judgment circuit, when the wake-up event occurs, enables a wake-up signal according to the reference signal, the first delay signal and the second delay signal. Such as the control circuit of claim 1, wherein the signal generating circuit includes: A first D-type flip-flop with a first input terminal, a first clock terminal and a first output terminal, the first clock terminal receiving the trigger signal; and A first inverter is coupled between the first input terminal and the first output terminal. For example, the control circuit of claim 1, wherein the first judgment circuit includes: A first logic circuit receives the reference signal and the first delay signal to generate an output signal. When the reference signal is equal to the first delay signal, the output signal is equal to a first level, and when the reference signal is equal to the first delay signal, the output signal is equal to a first level. When the signal is not equal to the first delayed signal, the output signal is equal to a second level, and the second level is relative to the first level; A second D-type flip-flop with a second input terminal, a second clock terminal, and a second output terminal. The second input terminal receives the output signal, and the second clock terminal receives the second delay Signal; and A second logic circuit is coupled to the second output terminal of the second D-type flip-flop. Such as the control circuit of claim 3, wherein when the second delay signal changes from the first level to the second level, the second D-type flip-flop provides the output signal to the second logic circuit. For example, the control circuit of claim 4, wherein when the wake-up event occurs and the output signal is equal to the first level, the second logic circuit enables the wake-up signal, and when the wake-up event does not occur or the output signal is equal to the first level When the two bits are on time, the second logic circuit does not enable the wake-up signal. Such as the control circuit of claim 5, where: There is a first delay time between the reference signal and the first delayed signal, and There is a second delay time between the trigger signal and the second delay signal, and the first delay time is different from the second delay time. Such as the control circuit of claim 1, wherein the timing circuit includes: A counting circuit, when the wake-up event occurs, adjust a count value according to a clock signal; A second judgment circuit for judging whether the count value reaches a target value, and when the count value reaches the target value, the second judgment circuit enables the trigger signal; and A reset circuit resets the count value when the second judgment circuit enables the trigger signal. Such as the control circuit of claim 7, wherein the reset circuit includes: A second inverter to invert the trigger signal to generate an inverted signal; The counting circuit resets the count value according to the inverted signal. An operating system including: A micro-control circuit receives a first operating voltage, when the first operating voltage is less than an expected voltage, the micro-control circuit enters a sleep mode, and when a wake-up signal is enabled, the micro-control circuit leaves the sleep mode And enter a normal mode, in which the micro-control circuit operates according to the first operating voltage; and A control circuit, when a wake-up event occurs, determines whether the first operating voltage reaches the expected voltage, and when the first operating voltage reaches the expected voltage, the control circuit enables the wake-up signal, wherein the control circuit includes: A timing circuit that enables a trigger signal at regular intervals when the wake-up event occurs; and A voltage monitoring module monitors whether the first operating voltage reaches an expected voltage according to the trigger signal, and when the first operating voltage reaches the expected voltage, the voltage monitoring module enables the wake-up signal. For example, the operating system of claim 9, wherein the voltage monitoring module includes: A signal generating circuit generates a reference signal according to the trigger signal; A first delay circuit that receives the first operating voltage and delays the reference signal to generate a first delay signal; A second delay circuit for delaying the trigger signal to generate a second delay signal; and A judgment circuit, when the wake-up event occurs, enables the wake-up signal according to the reference signal, the first delay signal and the second delay signal.

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