TWI528156B - Computing system having wake-up circuit - Google Patents

Description

Computer system with wake-up circuit

The present invention relates to a computer system having a wake-up circuit, and more particularly to a computer system having a wake-up circuit that transitions from a wake-up state to a power-up state in a delay time interval.

With the rapid advancement of technology, the development of the Internet has made various electronic devices full of people's lives, and the devices needed to construct the network are servers such as computer systems, in which the existing computer system switches from sleep state to wake-up. After the state, the wake-up device needs to wake up to enable the computer system to be powered on. However, the necessary condition for waking up the device to be awakened requires a delay time, and when the circuit designed in the computer system fails to reach the delay time, the wake-up is triggered. When the device is woken up, the device to be woken up cannot be woken up, and the computer system cannot be powered on normally. However, the circuit designed in the existing computer system generally cannot ensure the wake-up condition of the delay time. Therefore, the prior art still There is room for improvement.

In view of the fact that circuits in computer systems cannot guarantee reachable delay time Awakening the device to be awakened generally has the problem of not being able to stabilize the power-on work. Accordingly, the present invention mainly provides a computer system having a wake-up circuit, which mainly solves the above problem by ensuring that the computer system wakes up the device to be awakened by a delay time interval by a delay circuit in the wake-up circuit.

Based on the above objective, the main technical means adopted by the present invention is to provide a computer system with a wake-up circuit, comprising a reset device, a wake-up circuit and a wake-up device, and the reset device sends a wake-up signal to wake up the circuit. A first inverting logic circuit, a delay circuit, an AND gate circuit and a second inverting logic circuit are included. The first inverting logic circuit is electrically connected to the reset device, the delay circuit is electrically connected to the first inverting logic circuit, and the AND circuit is electrically connected to the first inverting logic circuit and the delay circuit, and the second The phase logic circuit is electrically connected to the AND circuit, and the device to be awakened is electrically connected to the second inverter logic circuit. The first inverting logic circuit receives the wake-up signal sent by the reset device, and generates an inverted wake-up signal, and the delay circuit receives the inverted wake-up signal and transmits an inverted delayed wake-up signal in a first delay time interval, and The gate circuit receives the wake-up signal and the inverted delay wake-up signal for logical and functional processing, and then sends an AND gate wake-up signal, and the second inverted logic circuit receives the AND gate wake-up signal to invert and transmits a terminal wake-up signal, and the wake-up device is to be awakened. The terminal wake-up signal is received to perform a wake-up action. Wherein, when the computer system transitions from a sleep state to an awake state, the reset device transmits a wake-up signal at a first level state, and after a second delay time interval, the computer system enters a system power-on state and wakes up. The signal transitions from a first level state to a second level state.

Among them, the above-mentioned technical means of the computer system with the wake-up circuit In a preferred embodiment, in the awake state, the first inverting logic circuit receives and inverts the wake-up signal in the first level state, thereby generating and transmitting the inverted wake-up signal in the second level state, The delay circuit receives the inverted wake-up signal in the second level state, and transmits the inverted delayed wake-up signal in the second level state in a third delay time interval, and the AND gate receives the first level state. A wake-up signal and an inverted delay wake-up signal in a second level state and transmitting an AND gate wake-up signal in a first level state, the second inverting logic circuit receiving an AND gate wake-up signal in a first level state The phase wake-up signal of the terminal in the second level state is output to the device to be woken up. In addition, when the computer system enters the system power-on state and the wake-up signal transitions from the first level state to the second level state, the first inverting logic circuit receives and inverts the wake-up signal in the second level state, thereby generating and Transmitting an inverted wake-up signal in a first level state, the delay circuit receiving an inverted wake-up signal in a first level state, and transmitting an inverted delay in a second level state in a fourth delay time interval Wake-up signal, the AND circuit receives the wake-up signal in the second level state and the inverted delayed wake-up signal in the second level state and transmits an AND gate wake-up signal in the second level state, the second inversion logic The circuit receives the terminal wake-up signal in a first level state after receiving the inversion of the gate wake-up signal in the second level state to the device to be woken up.

In a preferred embodiment of the above-mentioned auxiliary technical means for a computer system having a wake-up circuit, the wake-up device is one of a south bridge chip, a north bridge chip, a processor, and a baseboard management controller (BMC). First reverse logic The circuit and the second inverting logic circuit are NOT GATE, and the device to be woken up is a chip with a Peripheral Component Interconnect (PCI) interface and a high-speed peripheral interconnect standard (Peripheral Component Interconnect Express). One of the chips of the PCIE) interface, the first level state is a logic low level, the second level state is a logic high level, and the delay circuit is a RC delay circuit, and the wake-up device is One of a processor, a memory, and a storage device.

After the main technical means of the computer system with the wake-up circuit used in the present invention, the computer system can surely wake up from the wake-up state by the delay circuit in the wake-up circuit to ensure that the computer system wakes up the device to be awakened through the delay time interval. It is powered on, so it can work effectively and effectively solve the problems of the prior art.

The specific embodiments of the present invention will be further described by the following examples and drawings.

1‧‧‧Computer system with wake-up circuit

11‧‧‧Reset device

12‧‧‧Wake-up circuit

121‧‧‧First Inverting Logic Circuit

122‧‧‧Delay circuit

1221‧‧‧resistance

1222‧‧‧ Capacitance

12221‧‧‧ first end

12222‧‧‧ second end

123‧‧‧With gate

124‧‧‧Second inverting logic circuit

13‧‧‧Awaiting device

S1‧‧‧ wake up signal

S2‧‧‧ reverse wake-up signal

S3‧‧‧Inverse delayed wake-up signal

S4‧‧‧With door wake-up signal

S5‧‧‧ terminal wake-up signal

T1‧‧‧First delay time interval

T2‧‧‧second delay time interval

T3‧‧‧ third delay time interval

T4‧‧‧4th delay time interval

T1, t2, t3, t4‧‧‧ time

1 is a block diagram showing a computer system having a wake-up circuit in accordance with a preferred embodiment of the present invention; a second diagram showing a waveform of a state of a computer system in accordance with a preferred embodiment of the present invention; and a third diagram showing the present invention. A schematic diagram of the waveform of the delay time interval of the preferred embodiment.

In the computer system with the wake-up circuit provided by the present invention, the combined implementation manners are numerous, and therefore will not be further described herein, and only a preferred embodiment will be specifically described.

Please refer to the first figure, which is a block diagram showing a computer system with a wake-up circuit in accordance with a preferred embodiment of the present invention. As shown in the figure, a computer system 1 having a wake-up circuit according to a preferred embodiment of the present invention includes a reset device 11, a wake-up circuit 12, and a wake-up device 13. The reset device 11 is one of a south bridge chip, a north bridge chip, a processor, and a baseboard management controller (BMC), but other embodiments are not limited thereto.

The wake-up circuit 12 includes a first inverting logic circuit 121, a delay circuit 122, an AND circuit 123, and a second inverting logic circuit 124. The first inverting logic circuit 121 is electrically connected to the reset device 11 (the electrical connection point is labeled as A), and is a NOT gate (NOT gate), and the delay circuit 122 is electrically connected to the first counter. The phase logic circuit 121 (the electrical connection point is labeled as B), and the delay circuit 122 is a RC delay. Specifically, the delay circuit 122 includes a resistor 1221 and a capacitor 1222. The resistor 1221 is electrically connected. Connected to the first inverting logic circuit 121, one of the first ends 12221 of the capacitor 1222 is electrically connected to the resistor 1221 and the AND circuit 123 (the electrical connection point is labeled C), and the second end 12222 of the capacitor 1222 is grounded. .

The gate circuit 123 is electrically connected to the first inverting logic circuit 121 (the electrical connection point is labeled as A), and is electrically connected to the first end 12221 of the capacitor 1222 of the delay circuit 122 (the electrical connection point is marked as C). And the AND gate circuit 123 is an AND gate. Second inverted logic The circuit 124 is electrically connected to the AND circuit 123 (the electrical connection point is marked as D) and is a NOT gate (NOT gate).

The wake-up device 13 is electrically connected to the second inverting logic circuit 124 (the electrical connection point is marked as E), and is a chip with a Peripheral Component Interconnect (PCI) interface and a high-speed peripheral device. One of the chips of the Peripheral Component Interconnect Express (PCIE) interface, or one of a processor, a memory and a storage device, and the above processor is, for example, a central processing unit (Central Processing) Unit, CPU) or Graphic Processing Unit (GPU) or Accelerated Processing Unit (APU), and memory (memory) such as non-volatile memory (Non-Volatile Memory) or volatile memory Volatile Memory, and the storage device is, for example, a hard disk (HDD).

Please refer to the first to third figures. The second figure shows the waveform diagram of the state of the computer system of the preferred embodiment of the present invention. The third figure shows the waveform diagram of the delay time interval of the preferred embodiment of the present invention. .

As shown in the figure, in the operation of the computer system 1, the reset device 11 sends a wake-up signal S1, and the first inverting logic circuit 121 receives the wake-up signal S1 from the reset device 11 to generate a reverse wake-up signal S2. The delay circuit 122 receives the inverted wake-up signal S2 and transmits an inverted delayed wake-up signal S3 in a first delay time interval T1, and the AND circuit 123 receives the wake-up signal S1 and the inverted delayed wake-up signal S3 for logical AND functional processing. An AND gate wake-up signal S4 is transmitted, and the second inverting logic circuit 124 receives the AND gate wake-up signal S4 to invert and transmit A terminal wakes up signal S5, and the wake-up device 13 is triggered to perform a wake-up action after receiving the terminal wake-up signal S5.

Here, it should be noted that, in the following description, the first level state is a logic low level (that is, "0" in the digital signal, which can be called a low potential), and the second level state is a logic high power. Flat (that is, "1" in the digital signal, can be called high potential). When the computer system 1 transitions from a sleep status to a wake-up status (as shown in the second and third times, t1), the reset device 11 transmits the first After the wake-up signal S1 of a level state passes through a second delay time interval T2 (as shown in the second figure), the computer system 1 enters a system power on state and wakes up the signal S1 from the first level. The state transitions to the second level state, that is, the first delay time interval T1 described above is equal to the second delay time interval T2.

Specifically, in the awake state (that is, in the first delay time interval T1), the first inverting logic circuit 121 receives and inverts the wake-up signal S1 in the first level state, thereby generating and transmitting The inverted wake-up signal S2 of the second level state (refer to the waveform of the electrical connection point B in the third figure), the delay circuit 122 receives the inverted wake-up signal S2 in the second level state, and at a third delay The time interval T3 transmits the inverted delayed wake-up signal S3 in the second level state (refer to the waveform of the electrical connection point C in the third figure). It should be noted that, since the delay circuit 122 includes the capacitor 1222, the capacitor 1222 continues to be charged after receiving the inverted wake-up signal S2 of the second level state, and reaches the set first voltage threshold. When triggered, the inverted delayed wake-up signal S3 in the second level state is transmitted, and the present invention preferably In the embodiment, the inverted delayed wake-up signal S3 in the second level state is transmitted at time t2, that is, the charging time is t2-t1, and in the preferred embodiment of the present invention, the third delay In the time interval T3, the inverted delayed wake-up signal S3 in the second level state is transmitted, which is hereby described.

In addition, the AND circuit 123 receives the wake-up signal S1 in the first level state and the inverted delayed wake-up signal S3 in the second level state and transmits the AND gate wake-up signal S4 in the first level state (see The three-phase electrical connection point D waveform), the second inverting logic circuit 124 receives the terminal wake-up signal S5 in the second level state after the inversion of the gate wake-up signal S4 in the first level state (see The third figure is electrically connected to the waveform of the point E) to the device 13 to be awakened.

In addition, when the computer system 1 enters the system power-on state and the wake-up signal S1 transitions from the first level state to the second level state (as shown in the second and third times, time t3), the first inversion logic The circuit 121 receives and inverts the wake-up signal S1 in the second level state, thereby generating and transmitting the inverted wake-up signal S2 in the first level state (refer to the waveform of the electrical connection point B in the third figure), the delay The circuit 122 receives the inverted wake-up signal S2 in the first level state, and transmits the inverted delayed wake-up signal S3 in the second level state in a fourth delay time interval T4 (refer to the third figure electrical connection) Point C waveform). It should be noted that, since the delay circuit 122 includes the capacitor 1222, the capacitor 1222 continues to discharge after receiving the inverted wake-up signal S2 of the first level state, and reaches the set second voltage threshold. (for example, 0V) triggers the transmission of the opposite state at the first level The phase delay wake-up signal S3, and in the preferred embodiment of the present invention, the inverted delay wake-up signal S3 in the first level state is transmitted at time t4, that is, the time of the discharge is t4-t3 (may also It is T4=t4-t3), so in fact, the fourth delay time interval T4 transmits the inverted delay wake-up signal S3 in the second level state, and transmits the first level state after the time t4. Inverted delay wake-up signal S3, hereby stated

After the AND circuit 123 receives the wake-up signal S1 in the second level state and the inverted delay wake-up signal S3 in the second level state, the AND gate wake-up signal S4 in the second level state is transmitted (please Referring to the waveform of the electrical connection point D in the third figure, the second inverting logic circuit 124 receives the terminal wake-up signal S5 in the first level state after the inversion of the gate wake-up signal S4 in the second level state. The device 13 is to be awakened. In general, T1=T3+T4, and T1=T2, and T4 is about 10ms, that is, t2-t1 is also about 10ms, but it is not limited to this in other embodiments, depending on the practical design. .

In summary, after the computer system with the wake-up circuit provided by the present invention is used, the computer system ensures that the computer system wakes up the device to be awakened by the delay time interval by using the delay circuit and the AND gate circuit in the wake-up circuit. It can be sure to enter the system power-on state from the awake state, so that it can work effectively and effectively solve the problems of the prior art.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. Rather, its purpose is to accommodate various changes and equivalence arrangements in the present invention. Within the scope of the patent scope to be applied for.

1‧‧‧Computer system with wake-up circuit

11‧‧‧Reset device

12‧‧‧Wake-up circuit

121‧‧‧First Inverting Logic Circuit

122‧‧‧Delay circuit

1221‧‧‧resistance

1222‧‧‧ Capacitance

12221‧‧‧ first end

12222‧‧‧ second end

123‧‧‧With gate

124‧‧‧Second inverting logic circuit

13‧‧‧Awaiting device

S1‧‧‧ wake up signal

S2‧‧‧ reverse wake-up signal

S3‧‧‧Inverse delayed wake-up signal

S4‧‧‧With door wake-up signal

S5‧‧‧ terminal wake-up signal

Claims (9)

A computer system with a wake-up circuit, comprising: a reset device, which sends out a wake-up signal; a wake-up circuit comprising: a first inverting logic circuit electrically connected to the reset device; a delay circuit, Electrically connected to the first inverting logic circuit; an AND gate circuit electrically connected to the first inverting logic circuit and the delay circuit; and a second inverting logic circuit electrically connected to the And a wake-up device electrically connected to the second inverting logic circuit; wherein the first inverting logic circuit receives the wake-up signal from the reset device and generates an inverted wake-up signal The delay circuit receives the inverted wake-up signal and transmits an inverted delayed wake-up signal in a first delay time interval, and the AND circuit receives the wake-up signal and the inverted delayed wake-up signal to perform logical and functional processing and then transmit An AND gate wake-up signal, the second inverting logic circuit receives the AND gate wake-up signal and inverts and transmits a terminal wake-up signal, and the to-be-awake device receives the terminal wake-up signal a wake-up action; wherein, when the computer system transitions from a sleep state to an awake state, the reset device transmits the wake-up signal in a first level state, and after a second delay time interval, the computer system A system power-on state is entered and the wake-up signal transitions from the first level state to a second level state. The computer system with a wake-up circuit according to claim 1, wherein in the awake state, the first inverting logic circuit receives and inverts the wake-up signal in the first level state, thereby Generating and transmitting the inverted wake-up signal in the second level state, the delay circuit receiving the reverse wake-up signal in the second level state, and transmitting in the third delay time interval The inverting delay wake-up signal of the two-level state, the AND circuit receiving the wake-up signal in the first level state and the inverting delayed wake-up signal in the second level state and transmitting the first The AND gate wake-up signal of the level state, the second inverting logic circuit receiving the wake-up signal of the terminal in the first level state and outputting the wake-up signal of the terminal in the second level state to the Waiting for the device to wake up. A computer system having a wake-up circuit as described in claim 1, wherein the computer system enters a power-on state of the system and the wake-up signal transitions from the first level state to the second level state, The first inverting logic circuit receives and inverts the wake-up signal in the second level state, thereby generating and transmitting the inverted wake-up signal in the first level state, and the delay circuit is receiving the first The inverted wake-up signal of the level state, and transmitting the inverted delayed wake-up signal in the second level state in a fourth delay time interval, the AND circuit receiving the wake-up in the second level state And the inversion delayed wake-up signal in the second level state and transmitting the AND gate wake-up signal in the second level state, the second inverting logic circuit receiving the second level state The in-phase wake-up signal is inverted to output the end of the first level state The wake-up signal is sent to the device to be woken up. The computer system with a wake-up circuit according to claim 1, wherein the wake-up device is one of a south bridge chip, a north bridge chip, a processor, and a baseboard management controller (BMC). By. A computer system with a wake-up circuit as described in claim 1, wherein the first inverting logic circuit and the second inverting logic circuit are NOT GATE. The computer system with a wake-up circuit according to claim 1, wherein the device to be woken up is a chip with a Peripheral Component Interconnect (PCI) interface and a high-speed peripheral interconnect standard (Peripheral) One of the components of the Component Interconnect Express (PCIE) interface. A computer system with a wake-up circuit as described in claim 1, wherein the first level state is a logic low level and the second level state is a logic high level. A computer system with a wake-up circuit as described in claim 1, wherein the delay circuit is a RC delay circuit. A computer system with a wake-up circuit as described in claim 1 The device to be woken up is one of a processor, a memory and a storage device.