TW201351123A - Save energy circuit - Google Patents

Abstract

The present invention discloses a save energy circuit which including a voltage control terminal, a first transistor, a second transistor, a Field Effect Transistor (FET), and a voltage output terminal. A base of the first transistor is connected to the voltage control terminal via a resistor. An emitter of the first transistor is connected to ground, and a collector of the first transistor is connected to a first power supply. A base of the second transistor is connected to the collector of the first transistor. An emitter of the second transistor is connected to ground. A collector of the second transistor is connected to the first power supply. A gate of the FET is connected to the collector of the second transistor. A drain of the FET is connected to a second power supply, and a source of the FET is connected to the voltage output terminal.

Description

Energy saving circuit

The invention relates to an energy-saving circuit, in particular to an energy-saving circuit capable of realizing a deep sleep state of a computer (S5+).

According to the Advanced Configuration and Power Interface (ACPI) specification, the computer power management system can divide the working status of the computer into S0-S5, which means the following:

S0: The computer works normally, and all hardware devices are in the state of being open or working normally;

S1: Also known as POS (Power on Suspend), other hardware devices still work normally;

S2: The CPU is turned off, but the remaining hardware devices are still running;

S3: Usually called STR (Suspend to RAM, suspend to memory), write the running data into the memory and turn off the hard disk drive;

S4: Also known as STD (Suspend to Disk), the memory information is written to the hard disk drive, and then all the components stop working;

S5: All hardware devices (including power supplies) are turned off, that is, the computer is turned off.

Among them, when the computer is in the S5 state, since the chipset on the computer motherboard is still in working state, it may be detrimental to the saving of computer energy and the reduction of power consumption. Therefore, in order to solve the above problem, the working state of the computer has added a new state, that is, a deep sleep state (S5+). However, the conventional energy-saving circuit for realizing the S5+ state generally has a complicated circuit, and involves many components and a large space, which is disadvantageous for the reduction of the computer cost.

In view of this, it is necessary to provide an energy-saving circuit that is simple in structure, low in cost, and capable of realizing the S5+ state.

An energy-saving circuit is disposed in a computer, comprising a voltage control terminal, a first transistor, a second transistor, a field effect transistor and a voltage output terminal, wherein a base of the first transistor is connected to the voltage control by a resistor The emitter of the first transistor is grounded, the collector is connected to a first power source by a resistor, and the base of the second transistor is connected to the collector of the first transistor, the second transistor The emitter is grounded, and the collector is connected to the first power source by a resistor, the gate of the FET is connected to the collector of the second transistor, and the drain of the FET is connected to a second power source. The source of the FET is connected to the voltage output.

The above energy-saving circuit involves fewer electronic components and simple lines, which can effectively reduce the cost of the computer, and does not occupy too much space inside the computer, and is convenient for the user to use.

Referring to FIG. 1, a preferred embodiment of the present invention provides an energy saving circuit 100 for use in a computer (not shown). The energy saving circuit 100 includes a voltage control terminal SLP_SUS#, a first transistor Q1, a second transistor Q2, a field effect transistor M1, and a voltage output terminal 3V_S5.

The voltage control terminal SLP_SUS# is connected to a control chip in the computer, such as a Platform Controller Hub (PCH) (not shown), when the computer enters the S5+ state, under the control of the control chip. A first control signal (such as a low level signal) is output. When the computer exits the S5+ state, a second control signal (for example, a high level signal) opposite to the first control signal is output under the control of the control chip.

The first transistor Q1 is an NPN type transistor. The base of the first transistor Q1 is connected to the voltage control terminal SLP_SUS# by a resistor R1. The emitter of the first transistor Q1 is grounded, and the collector is connected to a first power source 5VSB by a resistor R2. The second transistor Q2 is an NPN type transistor. The base of the second transistor Q2 is coupled to the collector of the first transistor Q1. The emitter of the second transistor Q2 is grounded, and the collector is connected to the first power source 5VSB via a resistor R3. The gate of the FET M1 is connected to the collector of the second transistor Q2, and the drain of the FET M2 is connected to a second power source 3V_DUAL. The source of the FET M2 is connected to the voltage output terminal 3V_S5.

The voltage output terminal 3V_S5 is electrically connected to a chip set on the computer motherboard, such as a PCH, a Peripheral Component Interconnection (PCI), or the like, for supplying power to the chip set. Generally, when the computer is in the S5+ state, the voltage output terminal 3V_S5 outputs a low level to turn off the power of the chip set, so that the chip group stops working, thereby achieving energy saving. When the computer exits the S5+ state, the voltage output terminal 3V_S5 outputs a high level, thereby supplying power to the chip set, so that the chip group continues to operate normally.

The working principle of the energy saving circuit 100 in the preferred embodiment of the present invention will be described in detail below.

First, according to the above principle, when the computer enters the S5+ state, the voltage control terminal SLP_SUS# will output the first control signal (ie, a low level signal). The first control signal turns off the first transistor Q1, so that the base of the second transistor Q2 is turned on by being connected to the first power source 5VSB by the resistor R1. At this time, the gate of the FET M1 is turned off by the grounding of the turned-on second transistor Q2, so that the voltage output terminal 3V_S5 outputs a low level, so as to turn off the power of the chip set, so that The chipset stops working to achieve energy savings.

Correspondingly, when the computer exits the S5+ state, the voltage control terminal SLP_SUS# outputs the second control signal (ie, a high level signal). The second control signal turns on the first transistor Q1, so that the base of the second transistor Q2 is turned off by grounding the turned-on first transistor Q1. At this time, the gate of the FET M1 is turned on by being directly connected to the first power source 5VSB through the resistor R2, so that the voltage output terminal 3V_S5 is connected to the first via the FET M1. The second power supply, 3V_DUAL, outputs a high level to provide power to the chip set such that the chip set continues to operate normally.

It can be understood that, in other embodiments of the present invention, the power-saving circuit 100 further includes a delay circuit 101 connected between the collector of the second transistor Q2 and the gate of the field effect transistor M1. In order to prevent the FET M1 from being turned on, the voltage output terminal 3V_S5 outputs a large instantaneous current to the chip group, thereby preventing the second power source 3V_DUAL from generating a large voltage drop and making the second Other devices with the power supply 3V_DUAL are not working properly. Specifically, the delay circuit 101 includes a delay resistor R4 and a capacitor C1. One end of the delay resistor R4 is connected to the collector of the second transistor Q2, and the other end is grounded by the capacitor C1. Thus, when the computer exits the S5+ state, the second control signal output by the voltage control terminal SLP_SUS# will control the first transistor Q1 to be turned on, and the second transistor Q2 to be turned off. The voltage outputted by the first power supply 5V_SB will first charge the capacitor C1 by the delay resistor R4, and the field is controlled only when the voltage across the capacitor C1 reaches the turn-on voltage of the FET M1. The effect tube M1 is turned on, thereby preventing the field effect transistor M1 from being guided faster.

Obviously, the energy-saving circuit 100 of the present invention involves fewer electronic components and simple lines, which can effectively reduce the cost of the computer, and does not occupy too much space inside the computer, and is convenient for the user to use.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

100. . . Energy saving circuit

SLP_SUS#. . . Voltage control terminal

Q1. . . First transistor

Q2. . . Second transistor

M1. . . Field effect transistor

3V_S5. . . Voltage output

R1-R3. . . resistance

5VSB. . . First power supply

3V_DUAL. . . Second power supply

101. . . Delay circuit

R4. . . Time delay resistor

C1. . . capacitance

1 is a circuit diagram of an energy saving circuit in accordance with a preferred embodiment of the present invention.

100. . . Energy saving circuit

SLP_SUS#. . . Voltage control terminal

Q1. . . First transistor

Q2. . . Second transistor

M1. . . Field effect transistor

3V_S5. . . Voltage output

R1-R3. . . resistance

5VSB. . . First power supply

3V_DUAL. . . Second power supply

101. . . Delay circuit

R4. . . Time delay resistor

C1. . . capacitance

Claims (8)

An energy-saving circuit is disposed in a computer, comprising a voltage control terminal, a first transistor, a second transistor, a field effect transistor and a voltage output terminal, wherein a base of the first transistor is connected to the voltage control by a resistor The emitter of the first transistor is grounded, the collector is connected to a first power source by a resistor, and the base of the second transistor is connected to the collector of the first transistor, the second transistor The emitter is grounded, and the collector is connected to the first power source by a resistor, the gate of the FET is connected to the collector of the second transistor, and the drain of the FET is connected to a second power source. The source of the FET is connected to the voltage output. The energy-saving circuit of claim 1, wherein the voltage output terminal is electrically connected to the chip set on the computer motherboard, and when the computer enters a deep sleep (S5+) state, the voltage control terminal A first control signal is output, the first transistor is turned off and the second transistor is turned on, and the FET is turned off, so that the voltage output terminal outputs a low level to turn off the power of the chip set. The energy-saving circuit of claim 2, wherein when the computer exits the S5+ state, the voltage control terminal outputs a second control signal, and the second control signal causes the first transistor to be turned on. The second transistor is turned off, and the FET is turned on, so that the voltage output terminal outputs a high level to supply power to the chip set. The energy-saving circuit of claim 3, wherein the voltage control terminal is connected to a control chip in the computer for outputting the first control signal and the first control under the control of the control chip Two control signals. The energy-saving circuit of claim 1, wherein the energy-saving circuit further comprises a delay circuit connected between the collector of the second transistor and the gate of the FET for Preventing the FET from being fast, so that the voltage output terminal outputs a large instantaneous current, thereby preventing the second power source from generating a large voltage drop, so that other devices electrically connected to the second power source cannot be normal work. The energy-saving circuit of claim 5, wherein the delay circuit comprises a delay resistor and a capacitor, one end of the delay resistor is connected to the collector of the second transistor, and the other end is grounded by the capacitor. The energy-saving circuit of claim 1, wherein the first transistor is an NPN-type transistor. The energy-saving circuit of claim 1, wherein the second transistor is an NPN-type transistor.