WO2022032526A1

WO2022032526A1 - Monitoring sensor and chip

Info

Publication number: WO2022032526A1
Application number: PCT/CN2020/108708
Authority: WO
Inventors: 赛高乐; 欧勇盛; 段圣宇; 王志扬; 徐升; 熊荣; 刘超; 冯伟; 吴新宇
Original assignee: 深圳先进技术研究院
Priority date: 2020-08-12
Filing date: 2020-08-12
Publication date: 2022-02-17

Abstract

A monitoring sensor and a chip. The monitoring sensor comprises: a logical operation circuit (110) used to perform a logical XOR operation on multiple input signals to be monitored, and to output an operation result signal, wherein the signals to be monitored are digital signals; and a monitoring circuit (120) connected to the logical operation circuit (110) and used to monitor for a transition of the operation result signal, thereby performing monitoring of the multiple signals. Using the above method, the monitoring sensor can monitor for signal transitions for multiple data paths, thereby improving monitoring efficiency.

Description

Monitoring sensors and chips

【Technical field】

The present application relates to the technical field of integrated circuits, in particular to monitoring sensors and chips.

【Background technique】

Digital integrated circuits are widely used in key fields such as production, life and military. Driven by market demand, the feature size of integrated circuits has been greatly reduced, with the accompanying increase in process variation in production, voltage and temperature variation during operation, and aging phenomenon (PVTA) during its life cycle. As a result, the reliability of integrated circuits faces severe challenges.

For this problem, engineers proposed adding a soft-error monitoring sensor at the end of the critical path (the path with the longest propagation delay) in the digital integrated circuit, triggering the "error" when the propagation delay is about to exceed or just exceeds the system clock cycle Warning" signal. Combined with the dynamic voltage and frequency adjustment (Dynamic Voltage and Frequency Scaling, DVFS) mechanism, the system will increase the circuit supply voltage or reduce the frequency of circuit operation after receiving a "false warning" to ensure the normal operation of the system.

The DVFS system dynamically adjusts the operating frequency and voltage of the chip according to the different needs of the applications running on the chip for computing power (for the same chip, the higher the frequency, the higher the required voltage), so as to achieve the purpose of energy saving.

However, the ordering of critical paths in digital integrated circuits is affected by aging mechanisms and process variations. In other words, there may be multiple potential critical paths in the same circuit. However, the current soft error monitoring sensors on the market can only monitor a single critical path, which cannot meet the needs of users.

[Content of the invention]

The present application provides a monitoring sensor and a chip to solve the problem in the prior art that multi-channel data cannot be monitored for jumps.

In order to solve the above-mentioned technical problems, the present application proposes a monitoring sensor, including a logic operation circuit, which is used to perform an XOR logic operation on a plurality of input signals to be monitored, and output an operation result signal; wherein, the signal to be monitored is It is a digital signal; a monitoring circuit, which is connected to a logic operation circuit, is used to monitor the jumping situation of the operation result signal, so as to monitor multiple monitoring signals.

In order to solve the above technical problem, the present application proposes a chip including the above monitoring sensor.

The present application discloses a monitoring sensor, comprising a logic operation circuit and a monitoring circuit, wherein the logic operation circuit is used to perform an XOR logic operation on a plurality of input signals to be monitored, and output an operation result signal, and the to-be-monitored signal is a digital signal; The monitoring circuit is connected to the logic operation circuit, and is used for monitoring the jumping situation of the operation result signal, so as to monitor multiple monitoring signals. Since the probability of the same propagation delay of the data of different paths is close to zero, the monitoring sensor in this application can use the logic operation circuit to perform XOR logic operation on a plurality of signals to be monitored to obtain the operation result signal. When the signal to be monitored is not At the same time, the operation result signal jumps, and the monitoring circuit detects that the operation result signal jumps, that is, a corresponding error prompt signal is generated.

Through the above method, the monitoring sensor of the present application can perform jump monitoring on multiple channels of data at the same time, thereby improving the monitoring efficiency; in addition, the monitoring sensor has a simple circuit, high compatibility, low space cost during construction, and no additional fault tolerance in the circuit. circuit.

【Description of drawings】

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of an embodiment of a monitoring sensor of the present application;

Fig. 2 is the time sequence waveform schematic diagram of the monitoring sensor in Fig. 1;

3 is a schematic structural diagram of an embodiment of a monitoring circuit of the present application;

4 is a schematic diagram of a circuit structure of an embodiment of the monitoring circuit in FIG. 1;

5 is a schematic structural diagram of an embodiment of an XOR gate unit of the present application;

6 is a schematic diagram of the circuit structure of an embodiment of the XOR gate unit of the present application;

7 is a schematic structural diagram of an embodiment of a multiplexed logic operation circuit of the present application;

8 is a schematic structural diagram of another embodiment of a multiplexed logic operation circuit of the present application;

9 is a schematic structural diagram of another embodiment of a multiplexed logic operation circuit of the present application;

10 is a waveform diagram of the present application when monitoring a plurality of signals to be monitored at the same time;

11 is a probability analysis diagram of the transition of a plurality of signals to be monitored in the present application;

FIG. 12 is a schematic diagram of an application scenario of the monitoring sensor of the present application.

【detailed description】

In order to make those skilled in the art better understand the technical solutions of the present application, the monitoring sensor and chip provided by the invention are further described in detail below with reference to the accompanying drawings and specific embodiments.

Existing monitoring sensors can only monitor a single critical path. Driven by the market demand for high performance of integrated circuits, the propagation delays between the optimized paths of integrated circuits are often almost the same. However, under the combined effect of aging mechanism and process deviation. It is highly likely that these class critical paths will turn into critical paths after production or during use. At this time, only monitoring the original critical path will make the DVFS system ineffective. However, if the existing monitoring sensors are used to monitor all potential critical paths, the cost and complexity of the system will be greatly increased. Therefore, the related application is impractical in the existing nano-scale process integrated circuit application with strong aging mechanism and process deviation.

Based on the above problems, the present application proposes a monitoring sensor, which can monitor multiple signal paths simultaneously by a single sensor. Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a schematic structural diagram of an embodiment of a monitoring sensor of the present application, and FIG. 2 is a schematic diagram of a timing waveform of the monitoring sensor in FIG. 1 . In this embodiment, the monitoring sensor 100 may include a logic operation circuit 110 and a monitoring circuit 120 .

The logic operation circuit 110 can be used to perform an exclusive OR logic operation on a plurality of input signals to be monitored, and output an operation result signal X. The signal to be monitored may be a digital signal. In this embodiment, a plurality of to-be-monitored signals P ₁ _˜PN may be included. The signal to be monitored is the information to be monitored in the critical path in the corresponding digital integrated circuit.

The monitoring circuit 120 may be connected to the logic operation circuit 110 . The monitoring circuit 120 can be used to monitor the transition of the operation result signal X, so as to monitor a plurality of monitoring signals P ₁ _˜PN .

Please refer to FIG. 1 and FIG. 3 . FIG. 3 is a schematic structural diagram of an embodiment of a monitoring circuit of the present application. The monitoring circuit 120 may include a first input terminal and a second input terminal.

The first input terminal can be connected to the logic operation circuit 110, the second input terminal can be used to input the clock signal CLK, and the monitoring circuit 120 can be used to monitor the transition of the operation result signal X during the high level of the clock signal CLK, and generate a corresponding signal. The error prompt signal Error.

Further, during the low level period of the clock signal CLK, the monitoring circuit 120 does not work and cannot generate the corresponding error prompt signal Error; during the high level period of the clock signal CLK, the monitoring circuit 120 does not monitor the jump of the operation result signal X. If it changes, the corresponding error prompt signal Error will not be generated.

Theoretically, the rising edge of the error prompt signal Error can correspond to the transition time of the operation result signal X, and the falling edge of the error prompt signal Error can correspond to the falling edge of the clock signal CLK. Therefore, in fact, the rising edge of the error prompt signal Error is slightly later than the transition time of the operation result signal X, and the falling edge of the error prompt signal Error is slightly later than the falling edge of the clock signal CLK.

In addition, theoretically, the working time of the monitoring circuit 120 is half a clock cycle, the starting point corresponds to the rising edge of the clock signal CLK, and the ending point corresponds to the falling edge of the clock signal CLK. The monitoring circuit 120 monitors the operation result signal X during the working time. However, because the logic operation circuit 110 has a propagation delay, the monitoring interval of the monitoring circuit 120 for the signal to be monitored in this embodiment is earlier than the working time of the monitoring circuit 120 by an XOR gate unit propagation delay. time. The time after the signal to be monitored actually jumps to when the operation result signal X is received by the monitoring circuit 120 is regarded as the propagation delay of an XOR gate unit.

If the monitored signal is inverted at a certain point in time, it will cause

Level inversion occurs, that is, the operation result signal X is inverted. When the to-be-monitored signal flips within the monitoring interval, the error prompt signal Error of the monitoring circuit 120 will be triggered, and the error prompt signal Error will be cleared after the falling edge of the clock signal CLK.

Specifically, please refer to FIG. 4 , which is a schematic diagram of a circuit structure of an embodiment of the monitoring circuit in FIG. 1 . In this embodiment, the monitoring circuit may include 10 transistors and 1 inverter.

The control end of the first transistor T1 receives the clock signal CLK, and the first end of the first transistor T1 is connected to the working power supply VDD; the control end of the second transistor T2 receives the clock signal CLK, and the first end of the second transistor T2 is connected to the working power supply VDD; The control terminal of the third transistor T3 receives the operation result signal X, and the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1.

The first end of the fourth transistor T4 is connected to the second end of the first transistor T1; the input end of the first inverter N1 receives the operation result signal X; the control end of the fifth transistor T5 is connected to the output end of the first inverter N1 , the first end of the fifth transistor T5 is connected to the second end of the second transistor T2.

The first end of the sixth transistor T6 is connected to the second end of the second transistor T2; the control end of the seventh transistor T7 receives the clock signal CLK, and the first end of the seventh transistor T7 is connected to the second end of the fifth transistor T5 and the sixth The second end of the transistor T6 and the second end of the seventh transistor T7 are grounded.

The control end of the eighth transistor T8 is connected between the second end of the first transistor T1, the first end of the third transistor T3, and the first end of the fourth transistor T4, and the first end of the eighth transistor T8 is connected to the working power supply VDD .

The control terminal of the ninth transistor T9 is connected between the second terminal of the second transistor T2, the first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6, and the first terminal of the ninth transistor T9 is connected to the eighth transistor The second end of T8.

The control end of the tenth transistor T10 is connected to the second end of the third transistor T3, the second end of the fourth transistor T4, the second end of the fifth transistor T5, the second end of the sixth transistor T6 and the first end of the seventh transistor T7. One end, the first end of the tenth transistor T10 is connected to the second end of the ninth transistor T9, and the second end of the tenth transistor T10 is grounded.

Wherein, the control terminal of the fourth transistor T4, the control terminal of the sixth transistor T6, the second terminal of the ninth transistor T9 and the first terminal of the tenth transistor T10 are connected, and the node thereof serves as the first output terminal.

In this embodiment, the first transistor T1, the second transistor T2, the eighth transistor T8 and the ninth transistor T9 may be PMOS transistors, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, The seventh transistor T7 and the tenth transistor T10 may be NMOS transistors.

The second end of the first transistor T1, the first end of the third transistor T3, the first end of the fourth transistor T4, and the control end of the eighth transistor T8 are connected, and the node is a; the second end of the second transistor T2 terminal, the first terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 and the control terminal of the ninth transistor T9 are connected, and the node is b; the second terminal of the third transistor T3, the second terminal of the fourth transistor T4 The terminal, the second terminal of the fifth transistor T5, the second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7 and the control terminal of the tenth transistor T10 are connected, and the node is c.

When the clock signal CLK is at a low level, the first transistor T1 and the second transistor T2 are turned on, and the seventh transistor T7 is turned off. Nodes a and b are charged and are high. The eighth transistor T8 and the ninth transistor T9 are turned off. One of the third transistor T3 and the fifth transistor T5 is turned on (the third transistor T3 is turned on when the operation result signal X is at a high level, and the fifth transistor T5 is turned on when the operation result signal X is at a low level), the node c is charged (high level), the tenth transistor T10 is turned on, and the first output terminal is discharged and cleared. Therefore, when the clock signal CLK is at a low level, regardless of whether the first input terminal inputs a high level or a low level, the first output terminal is cleared.

When the clock signal CLK is at a high level, the first transistor T1 and the second transistor T2 are turned off, the seventh transistor T7 is turned on, the node c is discharged and cleared, and the tenth transistor T10 is turned off. One of the third transistor T3 and the fifth transistor T5 is turned on (the third transistor T3 is turned on when the operation result signal X is at a high level, and the fifth transistor T5 is turned on when the operation result signal X is at a low level), that is, the node Either a or b will be cleared by discharge. At this time, one of the eighth transistor T8 and the ninth transistor T9 is not turned on and the tenth transistor T10 is turned off, the first output terminal cannot be charged or discharged, so the value of the first output terminal remains unchanged. It is monitored that the operation result signal X jumps, and the nodes a and b that have not been discharged and cleared will be cleared, resulting in the eighth transistor T8 and the ninth transistor T9 being turned on at the same time, and the first output terminal is charged at this time, that is Output a high level signal to generate the corresponding error prompt signal Error. Therefore, when the clock signal CLK is at a high level, the operation result signal X jumps, and the first output terminal outputs a high level.

Continuing to refer to FIG. 1 , the logic operation circuit 110 may include N XOR gate units 111 , and the logic operation circuit 110 may be used to perform XOR logic operation on M to-be-monitored signals, where N=M+1. In this embodiment, the XOR gate unit may be a 2-input XOR gate.

The logic operation circuit 110 responds that the total number of high levels of the M signals to be monitored is an even number, and the output operation result signal X is a low level; the logic operation circuit 110 outputs an odd number in response to the total number of high levels of the M signals to be monitored. The operation result signal X is high level.

Please refer to FIG. 5 and FIG. 6 , FIG. 5 is a schematic structural diagram of an XOR gate unit according to an embodiment of the present application, and FIG. 6 is a schematic circuit structure diagram of an XOR gate unit according to an embodiment of the present application. In this embodiment, the XOR gate unit 111 includes a first XOR input terminal A, a second XOR input terminal B, and a first XOR output terminal Z.

Wherein, the first XOR input terminal A and the second XOR input terminal B may be used for receiving the signal to be monitored or the first XOR output terminal of other XOR gate units. The first XOR output terminal Z can be connected to the first XOR input terminal or the second XOR input terminal of other XOR gate units, or connected to the monitoring circuit 120 to output the operation result signal X.

As shown in FIG. 6 , the circuit structure of the XOR gate unit 111 may include a second inverter N2 and four transistors T11-T14.

Specifically, the input terminal of the second inverter N2 is connected to the first XOR input terminal. The control terminals of the eleventh transistor T11 and the twelfth transistor T12 are connected to the second XOR input terminal, the first terminal of the eleventh transistor T11 is connected to the first XOR input terminal, and the first terminal of the twelfth transistor T12 is connected to the first XOR input terminal. The second terminal of the eleven transistor T11. The second terminal of the twelfth transistor T12, the control terminal of the fourteenth transistor T14 and the output terminal of the second inverter N2 are connected. The first terminal of the eleventh transistor T11 and the control terminal of the thirteenth transistor T13 are connected to the first XOR input terminal.

The first end of the thirteenth transistor T13 is connected to the first end of the fourteenth transistor, and its node is connected between the first end of the eleventh transistor T11 and the second end of the twelfth transistor T12, and the node of the four A first XOR output can be connected. The second terminal of the thirteenth transistor T13 is connected to the second terminal of the fourteenth transistor T14, and the node thereof is connected to the second XOR input terminal.

When the first XOR input terminal is at a low level, the eleventh transistor T11 and the twelfth transistor T12 are turned off, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the first XOR output terminal and the second XOR The levels at the inputs are the same. When the first XOR input terminal is at a high level, the thirteenth transistor T13 and the fourteenth transistor T14 are turned off, the inverter composed of the eleventh transistor T11 and the twelfth transistor T12 is turned on, and the first XOR output terminal is turned on. Opposite to the level of the second XOR input. which is

In this embodiment, the eleventh transistor T11 and the thirteenth transistor T13 may be PMOS transistors, and the twelfth transistor T12 and the fourteenth transistor T14 may be NMOS transistors.

Optionally, the path from the input to the output of each signal to be monitored passes through the number of XOR gate units as

to

indivual. Please refer to FIG. 7-FIG. 9. FIG. 7 is a schematic structural diagram of an embodiment of the multi-path logic operation circuit of the present application; FIG. 8 is a structural schematic diagram of another embodiment of the multi-path logic operation circuit of the present application; FIG. 9 is a multi-path logic operation circuit of the present application. A schematic structural diagram of another embodiment of a logic operation circuit.

Among them, Figure 7 is a 3-input XOR gate, Figure 8 is a 4-input XOR gate, and Figure 9 is a 10-input XOR gate. In Figures 7-9, Z represents the output terminal of the multiple-input XOR gate, and A-J represent each input terminal of the multiple-input XOR gate.

In the 3-input XOR gate of FIG. 7, two XOR gate units 111 may be included, and the output end of the first XOR gate unit may be connected to the input end of the second XOR gate unit, thus obtaining

In the 4-input XOR gate of FIG. 8, three XOR gate units 111 may be included, and the output terminal of the first XOR gate unit and the output terminal of the second XOR gate unit may be respectively connected to the third XOR gate unit. the first input and the second input, resulting in

In the 10-input XOR gate in FIG. 9 , nine XOR gate units 111 may be included, and the two input terminals of the fifth XOR gate unit are respectively connected to the output terminal of the first XOR gate unit and the second XOR gate unit. The output terminal of the sixth XOR gate unit is respectively connected to the output terminal of the signal to be monitored and the third XOR gate unit, and the two input terminals of the seventh XOR gate unit are respectively connected to the signal to be monitored and the fourth XOR gate unit. The output terminal of the XOR gate unit; the two input terminals of the eighth XOR gate unit are respectively connected to the output terminal of the sixth XOR gate unit and the output terminal of the seventh XOR gate unit, and the two input terminals of the ninth XOR gate unit are respectively connected. The input terminals are respectively connected to the output terminal of the fifth XOR gate unit and the output terminal of the eighth XOR gate unit, thus obtaining

In this embodiment, when the total number of high levels of the M signals to be monitored is an even number, the operation result signal X output by the logic operation circuit 110 is a low level. For example, when only I and J input a high level, the fourth XOR gate unit outputs a low level, and finally the output terminal Z of the ninth XOR gate unit also outputs a low level, that is, when the same XOR gate unit receives When the two signals to be monitored are both input high level, the operation result signal X output by the logic operation circuit 110 is also low level.

When only B, C, E, and F input high level, the first XOR gate unit outputs a high level, the second XOR gate unit outputs a high level, and the fifth XOR gate unit outputs a low level; the third XOR gate unit outputs a low level; The XOR gate unit outputs a high level, the sixth XOR gate unit outputs a low level, and finally the output terminal Z of the ninth XOR gate unit also outputs a low level; that is, when different XOR gate units receive even numbers to be monitored When the signals are all input at a high level, the operation result signal X output by the logic operation circuit 110 is also at a low level.

When the total number of high levels of the M signals to be monitored is an odd number, the operation result signal X output by the logic operation circuit 110 is a high level. For example, when only A inputs a high level, the first XOR gate unit outputs a high level, the fifth XOR gate unit also outputs a high level, and finally the output terminal Z of the ninth XOR gate unit also outputs a high level .

When only A, C, and H input high level, the first XOR gate unit outputs a high level, the second XOR gate unit outputs a high level, the fifth XOR gate unit outputs a low level, and the seventh XOR gate unit outputs a low level. The gate unit outputs a high level, the eighth XOR gate unit outputs a high level, and finally the output terminal Z of the ninth XOR gate unit also outputs a high level, that is, as long as the total number of high levels of the signals to be monitored is odd, the logic The operation result signal X output by the operation circuit 110 is a high level.

Through the above method, the number of XOR gate units passing through the path from the input to the output of each signal to be monitored can be

(rounded down) to

(rounded up).

Please refer to FIGS. 10-11 , FIG. 10 is a waveform diagram of the present application when multiple signals to be monitored are simultaneously monitored, and FIG. 11 is a probability analysis diagram of the transition of multiple signals to be monitored in the present application. In Figure 10, Pi and Pj are two signals to be monitored.

In (a), two signals to be monitored, Pi and Pj, are inverted, wherein Pi is inverted within the monitoring interval, and Pj is inverted outside the monitoring interval. The inversion causes the operation result signal X to change when the signal CLK is always at a high level, causing the error prompt signal Error to be triggered.

In addition, it should be noted that the above-mentioned “the logic operation circuit 110 responds that the total number of high levels of the M signals to be monitored is an even number, and the output operation result signal X is a low level” and the situation in FIG. (a) Not contradictory: this is due to the propagation delay in the logic operation circuit 110 . In the ideal case without considering the propagation delay, the rising edge of the operation result signal X corresponds to the rising edge of Pj (at this time Pi is low level, Pj is high level), and the falling edge of the operation result signal X corresponds to Pi The rising edge of (Pi is high level at this time, Pj is high level). However, due to the propagation delay, in Figure (a), "Pi is low level, Pj is high level, the total number of high levels of the signal to be monitored is an even number, but the operation result signal X is low level. Case".

In (b), there are two signals to be monitored, Pi and Pj, which are inverted, wherein Pi and Pj are inverted in the monitoring interval at the same time. The inversion causes the signal operation result signal X to generate a small pulse signal when the clock signal CLK is at a high level, and the signal is sensed by the monitoring circuit 120 to trigger an error prompt signal Error.

In (c), two signals to be monitored, Pi and Pj, are inverted, wherein Pi and Pj are inverted in the monitoring interval at the same time and are very close (almost simultaneously inverted). At this time, since the sensitivity of the exclusive OR gate unit is not enough, a strong pulse signal cannot be triggered, so that the monitoring circuit 120 cannot sense the signal.

However, it can be seen from the probability analysis diagram in FIG. 11 that when the even number of the signals to be monitored in this embodiment changes and the propagation delay difference between each signal is almost 0, the monitoring sensor of this embodiment will be affected. failure, as shown in Figure (c).

Assuming that each signal monitoring point has a 50% probability of receiving a signal of '0' or '1', in the worst case, the probability of signal flipping is 25%. As shown in FIG. 11 , when there are more than 20 monitored paths, the probability of an even number of data in the to-be-monitored signal being inverted is 50%. In DVFS applications, voltage and frequency are not adjusted for a single false early warning signal. If the adjustment period is 1000 clock cycles, the probability that the signal flips are all even numbers is (50%) ¹⁰⁰⁰ (close to 0).

Among them, the probabilities of changes are:

odd change

even change

(1-α) ⁿ No change

In addition, this will be an extreme case where the propagation delay difference of all flipped data approaches 0, which is almost impossible to exist in practical applications. Therefore, the monitoring sensor of this embodiment is feasible.

Based on the above monitoring sensor 100, the present application also proposes a chip. The monitoring sensor 100 can be applied in a chip.

Please refer to FIG. 12 , which is a schematic diagram of an application scenario of the monitoring sensor of the present application. The chip may further include a D flip-flop 200, the D flip-flop 200 may be connected to the signal to be monitored, and the input end of the monitoring sensor 100 may be connected between the interface of the D flip-flop 200 and the signal to be monitored.

The present application discloses a monitoring sensor and a chip. The monitoring sensor includes a logic operation circuit and a monitoring circuit, wherein the logic operation circuit is used to perform XOR logic operation on a plurality of input signals to be monitored, and output the operation result signal. It is a digital signal; the monitoring circuit is connected to the logic operation circuit for monitoring the jumping situation of the operation result signal, so as to monitor multiple monitoring signals. Since the probability of the same propagation delay of data in different paths is close to zero, the monitoring sensor in this application can use the XOR gate to perform the XOR logic operation on multiple signals to be monitored, and the output of the XOR gate will be reversed by using a single signal transition It extracts the information of the transition of multiple signals to be monitored at the same time, and obtains the operation result signal. When the signals to be monitored are different, the operation result signal jumps, and the monitoring circuit detects that the operation result signal jumps, that is, a corresponding error is generated. cue signal.

Compared with related technologies, the current single sensor can only monitor one potential critical path. Under the existing technology with strong boss mechanism and process deviation, with the increase of the number of potential critical paths, the system construction cost of DVFS and related applications will increase. and increased complexity. In the above manner, the monitoring sensor of the present application can use a single sensor to monitor multiple signals to be monitored, that is, multiple potential critical paths, so as to reduce the construction cost and complexity of DVFS and related application scenarios.

Secondly, the monitoring sensor circuit of the present application is simple, the number of transistors is greatly reduced, and the input and output signals are simplified. The monitoring sensor of the present application can reduce the system construction cost and complexity in various application scenarios; and the monitoring sensor of the present application can be built without replacing any components of the original circuit, so the monitored circuit can be reserved in the design. The initial optimal solution.

It should be noted that the monitoring sensor of the present application can not only be used in the DVFS system, but also can be used to monitor other soft errors, such as single event flipping and the like.

It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, for the convenience of description, the drawings only show some but not all structures related to the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims

A monitoring sensor, characterized in that the monitoring sensor comprises:

a logic operation circuit, the logic operation circuit is used to perform XOR logic operation on a plurality of input signals to be monitored, and output an operation result signal; wherein, the to-be-monitored signal is a digital signal;

A monitoring circuit, which is connected to the logic operation circuit, is used for monitoring the jumping condition of the operation result signal, so as to monitor the plurality of monitoring signals.
The monitoring sensor according to claim 1, wherein the monitoring circuit comprises:

a first input terminal, connected to the logic operation circuit;

a second input terminal for inputting a clock signal;

The monitoring circuit is used to monitor the transition of the operation result signal during the high level period of the clock signal, and generate a corresponding error prompt signal.
The monitoring sensor according to claim 2, wherein,

The rising edge of the error prompt signal corresponds to the transition time of the operation result signal, and the falling edge of the error prompt signal corresponds to the falling edge of the clock signal.
The monitoring sensor according to claim 1, wherein the monitoring circuit comprises:

a first transistor, the control end of the first transistor receives the clock signal, and the first end of the first transistor is connected to the working power supply;

a second transistor, the control end of the second transistor receives the clock signal, and the first end of the second transistor is connected to the working power supply;

a third transistor, the control end of the third transistor receives the operation result signal, and the first end of the third transistor is connected to the second end of the first transistor;

a fourth transistor, the first end of the fourth transistor is connected to the second end of the first transistor;

a first inverter, the input end of the first inverter receives the operation result signal;

a fifth transistor, the control end of the fifth transistor is connected to the output end of the first inverter, and the first end of the fifth transistor is connected to the second end of the second transistor;

a sixth transistor, the first end of the sixth transistor is connected to the second end of the second transistor;

a seventh transistor, the control end of the seventh transistor receives the clock signal, the first end of the seventh transistor is connected to the second end of the fifth transistor and the second end of the sixth transistor, the seventh transistor The second terminal of the transistor is grounded;

an eighth transistor, the control end of the eighth transistor is connected between the second end of the first transistor, the first end of the third transistor, and the first end of the fourth transistor, and the first end of the eighth transistor is connected the working power supply;

A ninth transistor, the control end of the ninth transistor is connected between the second end of the second transistor, the first end of the fifth transistor, and the first end of the sixth transistor, and the first end of the ninth transistor is connected the second end of the eighth transistor;

A tenth transistor, the control end of the tenth transistor is connected to the second end of the third transistor, the second end of the fourth transistor, the second end of the fifth transistor, the second end of the sixth transistor and the seventh transistor The first end of the tenth transistor is connected to the second end of the ninth transistor, and the second end of the tenth transistor is grounded;

Wherein, the control terminal of the fourth transistor, the control terminal of the sixth transistor, the second terminal of the ninth transistor and the first terminal of the tenth transistor are connected, and the node thereof serves as the first output terminal .
The monitoring sensor of claim 1, wherein:

The logic operation circuit includes N XOR gate units, and the logic operation circuit is used to perform XOR logic operation on the M signals to be monitored, where N=M+1.
The monitoring sensor of claim 5, wherein:

The number of the XOR gate units passing through the path from the input to the output of each signal to be monitored is:
to
indivual.
The monitoring sensor according to claim 5, wherein the XOR gate unit comprises:

The first XOR input terminal and the second XOR input terminal are used to receive the signal to be monitored or the first XOR output terminal of other XOR gate units;

The first XOR output terminal is used for connecting to the first XOR input terminal or the second XOR input terminal of the other XOR gate units, or connecting to the monitoring circuit to output the operation result signal.
The monitoring sensor of claim 5, wherein:

In response to the total number of high levels of the M signals to be monitored being an even number, the operation result signal output by the logic operation circuit is a low level; in response to the total number of high levels of the M signals to be monitored being an odd number, the The operation result signal output by the logic operation circuit is a high level.
A chip, characterized in that it comprises the monitoring sensor according to any one of the above claims 1-8.
The chip according to claim 9, characterized in that, the chip further comprises a D flip-flop, the D flip-flop is connected to the signal to be monitored, and the monitoring sensor input terminal is connected to the interface of the D flip-flop and the signal to be monitored.