CN115529052B - High-frequency digital signal down-conversion modulation system - Google Patents
High-frequency digital signal down-conversion modulation system Download PDFInfo
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Abstract
The application discloses a high-frequency digital signal down-conversion modulation system, which relates to the field of electronic circuits, and aims to realize reduction of signal attenuation under the conditions that a PCB (printed Circuit Board) is not required to be upgraded and the link length is not required to be shortened. The method is also beneficial to obtaining more stable signal quality in the same link, thereby ensuring that the jump rate of the signal is unchanged, but the same bit number can be transmitted. Therefore, the PCB board is not required to be upgraded, the link length is not required to be shortened, and the signal quality can still be ensured.
Description
Technical Field
The application relates to the field of electronic circuits, in particular to a high-frequency digital signal down-conversion modulation system.
Background
High-speed serial signals have been developed for many years, and are widely used in the field of high-tech hardware such as servers, which are used in large quantities with extremely high reliability and interference resistance. However, as the signal rate is also higher, attenuation becomes more serious at the same transmission distance, and even after the signal reaches the receiving end, the amplitude of the signal cannot be recognized normally, so that the system is crashed. Higher frequency data is now typically transmitted by lifting the board of the printed circuit board (Printed Circuit Board, PCB) or reducing the signal transmission distance.
Along with the continuous promotion of data rate, through upgrading panel or reduction transmission link length, can reduce signal attenuation, guarantee signal quality's effect, but often this kind of promotion panel can bring huge increase in the cost, in reality, because physical architecture's restriction, also hardly shorten the length, guarantee signal quality.
Therefore, how to reduce signal attenuation without upgrading the PCB board and shortening the link length is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The application aims to provide a high-frequency digital signal down-conversion modulation system, which does not need to upgrade a PCB (printed circuit board) board, shortens the length of a link, reduces signal attenuation and improves signal quality.
In order to solve the above technical problems, the present application provides a high frequency digital signal down-conversion modulation system, comprising:
The device comprises a digital signal modulation circuit, a high-frequency signal input end, a voltage signal output end and a voltage signal identification device;
the high-frequency signal input end is connected with the digital signal modulation circuit, the digital signal modulation circuit is connected with the voltage signal output end, the voltage signal output end is connected with the voltage signal identification device, the digital signal modulation circuit converts the two-byte level signal input by the high-frequency signal input end into a voltage signal, the voltage signal is output to the voltage signal identification device from the voltage signal output end, and the voltage signal identification device is used for identifying the voltage signal.
Preferably, in the above-mentioned high frequency digital signal down-conversion modulation system,
The digital signal modulation circuit (11) includes: exclusive-or gate, first not gate, second not gate, third not gate, fourth not gate, fifth not gate, first and gate, second and gate, first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, first operational amplifier circuit, second operational amplifier circuit, third operational amplifier circuit;
Two input ends of the high-frequency signal input end (12) are connected with the input end of an exclusive-or gate, one input end of the exclusive-or gate is connected with the second input end of a first AND gate, the first input end of a second AND gate, the input end of a fifth transistor and the input end of a sixth transistor, the output end of the exclusive-or gate is connected with the input end of a first NOT gate, the control end and the input end of the first transistor and the input end of a second transistor, the output end of the first NOT gate is connected with the control end of the second transistor, the output end of the second NOT gate is connected with the first input end of the first AND gate, the output end of the first AND gate is connected with the input end of a third NOT gate and the control end of the fifth transistor, the output end of the third NOT gate is connected with the control end of the sixth transistor, the output end of the sixth transistor is connected with the voltage signal output end (13),
The output end of the fifth transistor is connected with a first operational amplification circuit, and the first operational amplification circuit is connected with a voltage signal output end (13);
The output end of the first transistor is connected with the second input end of the second AND gate, the output end of the second AND gate is connected with the input end of the fourth NOT gate, the input end of the third transistor, the input end of the fourth transistor and the control end, the output end of the fourth transistor is connected with the second operational amplifier circuit, and the second operational amplifier circuit is connected with the voltage signal output end (13);
the output end of the fourth NOT gate is connected with the control end of the third transistor, the output end of the third transistor is connected with the input end of the fifth NOT gate, the output end of the fifth NOT gate is connected with the third operational amplifier circuit, and the third operational amplifier circuit is connected with the voltage signal output end (13);
the gain values of the first operational amplifier circuit, the second operational amplifier circuit and the third operational amplifier circuit are different.
Preferably, in the above high frequency digital signal down-conversion modulation system, the first operational amplifier circuit includes: the first resistor, the second resistor and the first operational amplifier; the second operational amplifier circuit includes: the third resistor, the fourth resistor and the second operational amplifier; the third operational amplifier circuit includes: the fifth resistor, the sixth resistor and the third operational amplifier;
The output end of the fifth transistor is connected with the non-inverting input end of the first operational amplifier, the inverting input end of the first operational amplifier is connected with the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is grounded, and the output end of the first operational amplifier is connected with the second end of the second resistor and the voltage signal output end (13);
The output end of the fourth transistor is connected with the non-inverting input end of the second operational amplifier, the inverting input end of the second operational amplifier is connected with the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is grounded, and the output end of the second operational amplifier is connected with the second end of the second resistor and the voltage signal output end (13);
The output end of the fifth NOT gate is connected with the non-inverting input end of the third operational amplifier, the inverting input end of the third operational amplifier is connected with the first end of the fifth resistor and the first end of the sixth resistor, the second end of the fifth resistor is grounded, and the output end of the third operational amplifier is connected with the second end of the sixth resistor and the voltage signal output end (13).
Preferably, in the above high frequency digital signal down-conversion modulation system, the method further includes: a seventh resistor;
The output end of the fifth transistor is connected with the non-inverting input end of the first operational amplifier through a seventh resistor.
Preferably, in the high frequency digital signal down modulation system, an eighth resistor;
the output end of the fourth transistor is connected with the non-inverting input end of the second operational amplifier through an eighth resistor.
Preferably, in the high frequency digital signal down modulation system, a ninth resistor;
the output end of the fifth NOT gate is connected with the non-inverting input end of the third operational amplifier through a ninth resistor.
Preferably, in the high frequency digital signal down-conversion modulation system, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are N-type MOS transistors.
Preferably, in the high frequency digital signal down-conversion modulation system, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NPN transistors.
Preferably, in the above high frequency digital signal down-conversion modulation system, the first operational amplifier, the second operational amplifier, and the third operational amplifier are LM307.
Preferably, in the above high frequency digital signal down modulation system, the xor gate is 74S86.
Preferably, in the above high frequency digital signal down modulation system, the first not gate, the second not gate, the third not gate, the fourth not gate, and the fifth not gate are CD4069.
The high frequency digital signal down-conversion modulation system provided by the application comprises: the device comprises a digital signal modulation circuit, a high-frequency signal input end, a voltage signal output end and a voltage signal identification device; the high-frequency signal input end is connected with the digital signal modulation circuit, the digital signal modulation circuit is connected with the voltage signal output end, the voltage signal output end is connected with the voltage signal identification device, the digital signal modulation circuit converts the two-byte level signal input by the high-frequency signal input end into a voltage signal, the voltage signal is output to the voltage signal identification device from the voltage signal output end, and the voltage signal identification device is used for identifying the voltage signal. The digital signal modulation circuit converts the two-byte level signal into a voltage signal, and outputs the voltage signal from the voltage signal output end to the voltage signal identification device, combines the two-byte level signals, and displays the two-byte level signals by using one level, thus reducing the signal hopping frequency, that is to say, the two bits can only carry out one-level hopping, thus reducing the signal hopping frequency, but the transmitted information quantity is unchanged, and the signal attenuation degree is reduced due to the reduction of the signal hopping frequency, thereby being beneficial to the improvement of the signal quality. The method is also beneficial to obtaining more stable signal quality in the same link, thereby ensuring that the jump rate of the signal is unchanged, but the same bit number can be transmitted. Therefore, the PCB board is not required to be upgraded, the link length is not required to be shortened, and the signal quality can still be ensured.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram of a high frequency digital signal down-conversion modulation system according to an embodiment of the present application;
fig. 2 is a circuit diagram of a high frequency digital signal down-conversion modulation system according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The application aims at providing a high-frequency digital signal down-conversion modulation system.
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.
With the continuous development of communication technology, the signal transmission speed of the equipment is faster and faster, and the data volume is also continuously increased; high-speed serial signals have been developed for many years, and are widely used in the field of high-tech hardware such as servers, which are used in large quantities with extremely high reliability and interference resistance. However, as the signal rate is also higher, attenuation becomes more serious at the same transmission distance, and even after the signal reaches the receiving end, the amplitude of the signal cannot be recognized normally, so that the system is crashed.
Signal attenuation is the most common term when high-speed signals propagate on a circuit board. It is one of the main factors of signal attenuation that causes signal integrity problems. The attenuation of the signal refers to the degree of signal amplitude transformation transmitted from a source end to a terminal, the higher the signal frequency is, the larger the attenuation is, the worse the quality of the signal reaching the terminal is, and the signal is not easy to be identified stably.
Under the same conditions, the higher the signal rate, the larger the loss, and the signal quality is reduced due to the increase of the signal loss, thereby influencing the performance and the service life of the product. It becomes very important to reduce the loss of signals, particularly high-speed signals, on the PCB transmission path and to ensure the quality of the high-speed signals.
Along with the continuous promotion of data rate, through upgrading panel or reduction transmission link length, can reduce signal attenuation, guarantee signal quality's effect, but often this kind of promotion panel can bring huge increase in the cost, in reality, because physical architecture's restriction, also hardly shorten the length, guarantee signal quality.
In order to solve the above-mentioned problem, the present embodiment provides a high frequency digital signal down-conversion modulation system, including:
A digital signal modulation circuit 11, a high-frequency signal input terminal 12, a voltage signal output terminal 13, and a voltage signal recognition device 14;
the high-frequency signal input terminal 12 is connected to the digital signal modulation circuit 11, the digital signal modulation circuit 11 is connected to the voltage signal output terminal 13, the voltage signal output terminal 13 is connected to the voltage signal recognition device 14, the digital signal modulation circuit 11 converts the two-byte level signal input from the high-frequency signal input terminal 12 into a voltage signal, and outputs the voltage signal from the voltage signal output terminal 13 to the voltage signal recognition device 14, and the voltage signal recognition device 14 is used for recognizing the voltage signal.
The digital signal modulation circuit 11 according to the present embodiment is used for implementing digital signal modulation, and digital signal modulation refers to a combination of digital bits 0 and 1, and can be combined into four modes of 00, 01, 10 and 11, and modulation is that for each of these four modes, a level is adopted to represent a certain combination, for example, 00 is replaced by level 0, 01 is replaced by level V1, 10 is replaced by level V2, 11 is replaced by level VH, so that the modulated signal can represent two bits by a level, and the amount of information to be transmitted is increased. In other words, the signal transmission hopping frequency can be reduced, and signal attenuation can be reduced.
In this embodiment, the high-frequency signal input terminal 12 outputs two-byte level signals to the digital signal modulation circuit 11, the digital signal modulation circuit 11 converts the two-byte level signals into a voltage signal, and outputs the voltage signal from the voltage signal output terminal 13 to the voltage signal recognition device 14, and the voltage signal recognition device 14 can analyze the corresponding original level signal data according to the preset recognition voltage signal.
The high frequency digital signal down modulation system provided in this embodiment includes: a digital signal modulation circuit 11, a high-frequency signal input terminal 12, a voltage signal output terminal 13, and a voltage signal recognition device 14; the high-frequency signal input terminal 12 is connected to the digital signal modulation circuit 11, the digital signal modulation circuit 11 is connected to the voltage signal output terminal 13, the voltage signal output terminal 13 is connected to the voltage signal recognition device 14, the digital signal modulation circuit 11 converts the two-byte level signal input from the high-frequency signal input terminal 12 into a voltage signal, and outputs the voltage signal from the voltage signal output terminal 13 to the voltage signal recognition device 14, and the voltage signal recognition device 14 is used for recognizing the voltage signal. The digital signal modulation circuit 11 converts the two-byte level signal into a voltage signal, and outputs the voltage signal from the voltage signal output terminal 13 to the voltage signal identification device 14, combines the two-byte level signals, and displays the two-byte level signals with one level, which is equivalent to reducing the hopping frequency of the signal, that is, the two bits can perform one-level hopping, which is equivalent to reducing the frequency of signal hopping, but the transmitted information amount is unchanged, and the signal attenuation degree is reduced due to the reduction of the signal hopping frequency, so that the improvement of the signal quality is facilitated. The method is also beneficial to obtaining more stable signal quality in the same link, thereby ensuring that the jump rate of the signal is unchanged, but the same bit number can be transmitted. Therefore, the PCB board is not required to be upgraded, the link length is not required to be shortened, and the signal quality can still be ensured.
According to the above embodiment, the present embodiment provides a preferred scheme of the digital signal modulation circuit 11, fig. 2 is a circuit diagram of a high frequency digital signal down-conversion modulation system provided in the embodiment of the present application, as shown in fig. 2, the digital signal modulation circuit (11) includes: exclusive-or gate U1, first not gate U4, second not gate U5, third not gate U6, fourth not gate U7, fifth not gate U8, first and gate U2, second and gate U3, first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4, fifth transistor Q5, sixth transistor Q6, first operational amplifier circuit, second operational amplifier circuit, third operational amplifier circuit;
Two input ends bit (n) of a high-frequency signal input end (12), bit (n+1) are connected with the input end of an exclusive-or gate U1, one input end bit (n+1) of the exclusive-or gate U1 is connected with the second input end of a first AND gate U2, the first input end of a second AND gate U3, the input end of a fifth transistor Q5 and the input end of a sixth transistor Q6, the output end of the exclusive-or gate U1 is connected with the input end of a first NOT gate U4, the control end and the input end of the first transistor Q1 and the input end of the second transistor Q2, the output end of the first NOT gate U4 is connected with the control end of the second transistor Q2, the output end of the second NOT gate U5 is connected with the first input end of the first AND gate U2, the output end of the first AND gate U2 is connected with the input end of a third NOT gate U6, the control end of the fifth transistor Q5, the output end of the third NOT gate U6 is connected with the output end of the sixth transistor Q6, the output end of the third NOT gate U6 is connected with the output end of the sixth transistor Q13,
The output end of the fifth transistor Q5 is connected with a first operational amplifier circuit, and the first operational amplifier circuit is connected with a voltage signal output end 13;
The output end of the first transistor Q1 is connected with the second input end of the second AND gate U3, the output end of the second AND gate U3 is connected with the input end of the fourth NOT gate U7, the input end of the third transistor Q3, the input end of the fourth transistor Q4 and the control end, the output end of the fourth transistor Q4 is connected with a second operational amplifier circuit, and the second operational amplifier circuit is connected with a voltage signal output end (13);
The output end of the fourth NOT gate U7 is connected with the control end of the third transistor Q3, the output end of the third transistor Q3 is connected with the input end of the fifth NOT gate U8, the output end of the fifth NOT gate U8 is connected with a third operational amplifier circuit, and the third operational amplifier circuit is connected with a voltage signal output end (13);
the gain values of the first operational amplifier circuit, the second operational amplifier circuit and the third operational amplifier circuit are different.
In the present embodiment, it is known that the high frequency digital signal bit (n), bit (n+1), is input 00 at time T1, so that the exclusive or gate U1 outputs 0, so that the gate voltage of the first transistor Q1 is 0, so that the first transistor Q1 is turned off, so that the output U4 (out) =1 of the first not gate U4, so that the gate voltage of the second transistor Q2 is 1, so that the second transistor Q2 is turned on. The output U5 (out) =1 of the second not gate U5, so that at this time the input of the first and gate U2 is 0 and one is 1, so that the output U2 (out) =0 of the first and gate U2, so that the fifth transistor Q5 is turned off, the output of the third not gate U6 is 1, so that the sixth transistor Q6 is turned on, so that the output of the sixth transistor Q6 is bit (n+1) =0, so that at this time T1, vout=0.
At time T2, bit (n), bit (n+1) is 01, so the output of the exclusive or gate U1 is 1, and at this time, the first transistor Q1 is turned on, so the output of the first not gate U4 is 0, and the second transistor Q2 is turned off. At this time, the inputs of the second and gate U3 are 1 and bit (n+1) =1, so the output of the second and gate U3 is 1, so the output of the fourth not gate U7 is 0, so the third transistor Q3 is turned off. The gate of the fourth transistor Q4 is 1, so the fourth transistor Q4 is turned on, and the output of the fourth transistor Q4 is 1.
At time T3, bit (n), bit (n+1) is 10, so the output of exclusive or gate U1 is also 1, so the first transistor Q1 is on, the second transistor Q2 is off, bit (n+1) =0, so the output of the second and gate U3 is 0, so the fourth transistor Q4 is off, so the output of the fourth not gate U7 is 1, so the third transistor Q3 is on, so the output of the fifth not gate U8 is 1,
At time T4, bit (n), bit (n+1) is 11, so that the output of the exclusive or gate U1 is 0, at this time the first transistor Q1 is off, the second transistor Q2 is on, so that the output of the second not gate U5 is 1, so that the output of the first and gate U2 is 1,
The gain values of the first operational amplifier circuit, the second operational amplifier circuit and the third operational amplifier circuit are different, so that the output voltage values are also different, and the different voltage values correspond to different two-byte level signals, which is equivalent to reducing the frequency of signal jump, but the transmitted information amount is unchanged, and the signal attenuation degree is reduced due to the reduction of the signal jump frequency, thereby being beneficial to the improvement of the signal quality.
Specifically, the first operational amplifier circuit includes: the first resistor R1, the second resistor R2 and the first operational amplifier W1; the second operational amplifier circuit includes: the third resistor R3, the fourth resistor R4 and the second operational amplifier W2; the third operational amplifier circuit includes: a fifth resistor R5, a sixth resistor R6 and a third operational amplifier W3;
The output end of the fifth transistor Q5 is connected with the non-inverting input end of the first operational amplifier W1, the inverting input end of the first operational amplifier W1 is connected with the first end of the first resistor R1 and the first end of the second resistor R2, the second end of the first resistor R1 is grounded, and the output end of the first operational amplifier W1 is connected with the second end of the second resistor R2 and the voltage signal output end 13;
The output end of the fourth transistor Q4 is connected with the non-inverting input end of the second operational amplifier W2, the inverting input end of the second operational amplifier W2 is connected with the first end of the third resistor R3 and the first end of the fourth resistor R4, the second end of the third resistor R3 is grounded, and the output end of the second operational amplifier W2 is connected with the second end of the second resistor R2 and the voltage signal output end 13;
The output end of the fifth NOT gate U8 is connected with the non-inverting input end of the third operational amplifier W3, the inverting input end of the third operational amplifier W3 is connected with the first end of the fifth resistor R5 and the first end of the sixth resistor R6, the second end of the fifth resistor R5 is grounded, and the output end of the third operational amplifier W3 is connected with the second end of the sixth resistor R6 and the voltage signal output end 13.
Therefore, when the high frequency digital signal bit (n), bit (n+1) is input to 00, vout=0;
When the high frequency digital signal bit (n) is input, bit (n+1) is input as 01, and the second op-amp W2 is in a virtual short and virtual off state due to negative feedback, so that the voltage at the inverting input end=the positive input end=1 of the second op-amp W2, and the magnitude of the current flowing through the third resistor R3 is equal to the magnitude of the current flowing through the fourth resistor R4, so that the output voltage of the second op-amp W2 is a (1+r4/R3). So vout=v1=a (1+r4/R3) at this time.
When the high frequency digital signal bit (n) is input, bit (n+1) is input to 10, and similarly, the output of vout=v2=b (1+r6/R5) is obtained.
When the high frequency digital signal bit (n) is input, bit (n+1) is input to 11, and similarly, the output of vout=vh=c (1+r2/R1) is obtained.
In summary, at the time T1 to T4, the output Vout output represents two kinds of bit data with one level at the time T1 to T4, which is equivalent to reducing the frequency of signal hopping, but the amount of information transmitted is unchanged, and the attenuation degree of the signal is reduced due to the reduction of the frequency of signal hopping, which is beneficial to the improvement of the signal quality. The method is favorable for obtaining more stable signal quality in the same link, thereby ensuring that the jump rate of the signal is unchanged, but the same bit number can be transmitted equally. Therefore, the PCB board is not required to be upgraded, the link length is not required to be shortened, and the signal quality can still be ensured.
According to the above embodiment, in order to protect the operational amplifier element, the present embodiment provides a preferred solution, further including: a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9;
The output terminal of the fifth transistor Q5 is connected to the non-inverting input terminal of the first op-amp W1 through a seventh resistor R7. The output end of the fourth transistor Q4 is connected to the non-inverting input end of the second op-amp W2 through an eighth resistor R8. The output end of the fifth NOT gate U8 is connected with the non-inverting input end of the third operational amplifier W3 through a ninth resistor R9.
The seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 are respectively connected in series with the non-inverting input ends of the first operational amplifier W1, the second operational amplifier W2 and the third operational amplifier W3 so as to avoid burning out the operational amplifier element due to overlarge current.
In this embodiment, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 may be N-type MOS transistors or NPN-type transistors. The present embodiment is not particularly limited, and may be set according to actual needs.
For a better understanding of the present solution, a specific preferred embodiment is now provided by those skilled in the art, bit (n), bit (n+1) logic level of 1.1v, vcc of 3.3v, R1, R3, R5 of 1k, r2=0k, r4=1k, r6=2k, R7, R8, R9 of 10k. The first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are N-type MOS transistors.
In this embodiment, at time T1, the high frequency digital signal bit (n), bit (n+1) is 0V, and 0V is input, so that the output of the exclusive or gate U1 is 0, and therefore the gate voltage of the first MOS transistor Q1 is 0, so that the first MOS transistor Q1 is turned off, and therefore the output U4 (out) =1.1v of the first not gate U4, and therefore the gate voltage of the second MOS transistor Q2 is 1, and therefore the second MOS transistor Q2 is turned on. The output U5 (out) =1.1v of the second not gate U5, so that at this time, the input of the first and gate U2 is 0 and 1, so that the output U2 (out) =0v of the first and gate U2, therefore, the fifth MOS transistor Q5 is turned off, the output of the third not gate U6 is 1, so that the sixth MOS transistor Q6 is turned on, and therefore, the output of the sixth MOS transistor Q6 is bit (n+1) =0v, therefore, at this time, T1, vout=0.
At time T2, bit (n), bit (n+1) is 0V,1.1V, so that the output of the exclusive-or gate U1 is 1.1V, and therefore the first MOS transistor Q1 is turned on at this time, and the output of the first not gate U4 is 0, and therefore the second MOS transistor Q2 is turned off. At this time, the inputs of the second and gate U3 are 1.1V and bit (n+1) =1.1v, so the output of the second and gate U3 is 1.1V, so the output of the fourth not gate U7 is 0, so the third MOS transistor Q3 is turned off. The gate level of the fourth MOS transistor Q4 is 1.1V, so that the fourth MOS transistor Q4 is conducted, and the output of the fourth MOS transistor Q4 is 1.1V. The second op-amp W2 is in a virtual short-to-virtual-off state due to negative feedback, so that the voltage at the reverse input terminal=the forward input terminal=1.1V of the second op-amp W2 is equal to the current flowing through the third resistor R3 and the current flowing through the fourth resistor R4, and the output voltage of the second op-amp W2 is a (1+r4/R3) =1.1v (1+0k/1K). Vout=1.1v at this time.
At time T3, bit (n), bit (n+1) is 1.1V,0V, so the output of the exclusive-or gate U1 is also 1.1V, so the first MOS transistor Q1 is turned on, the second MOS transistor Q2 is turned off, at this time, bit (n+1) =0v, so the output of the second and gate U3 is 0V, so the fourth MOS transistor Q4 is turned off, so the output of the fourth not gate U7 is 1.1V, so the third MOS transistor Q3 is turned on, so the output of the fifth not gate U8 is 1.1V, at this time, the third op-amp W3 is in a virtual-off state, and thus the output of vout=v2=b (1+r6/R5) =1.1v (1+1k/1K) =2.2v can be obtained. .
At time T4, bit (n), bit (n+1) is 1.1V, so that the output of the exclusive-or gate U1 is 0V, at this time, the first MOS transistor is turned off, the second MOS transistor Q2 is turned on, so that the output of the second not gate U5 is 1.1V, so that the output of the first and gate U2 is 1.1V, at this time, the fifth MOS transistor Q5 is turned on, the sixth MOS transistor Q6 is turned off, and similarly, the output of vout=vh=c (1+r2/R1) =1.1V (1+2k/1K) =3.3V can be obtained.
In summary, the output of 0V at time T1 represents a 00 digital signal, the output of 1.1V at time T2 represents a 01 signal, the output of 2.2V at time T3 represents a 10 signal, and the output of 3.3V at time T4 represents an 11 signal, so that the four level signals represent 8 kinds of bit information, which is equivalent to the signal frequency being half of the original frequency, but the amount of bit information transmitted is unchanged, and the signal attenuation is reduced due to the reduction of the frequency, which is more beneficial to the improvement of the signal quality. The method is favorable for obtaining more stable signal quality in the same link, thereby ensuring that the jump rate of the signal is unchanged, but the same bit number can be transmitted equally. Therefore, the PCB board is not required to be upgraded, the link length is not required to be shortened, and the signal quality can still be ensured.
In addition, preferably, the first operational amplifier W1, the second operational amplifier W2, and the third operational amplifier W3 are LM307.
Exclusive or gate U1 is 74S86. The first NOT gate U4, the second NOT gate U5, the third NOT gate U6, the fourth NOT gate U7 and the fifth NOT gate U8 are CD4069. The first and gate U2 and the second and gate U3 are CD4081. The first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are Si2302 NMOS transistors.
The high-frequency digital signal down-conversion modulation system provided by the application is described in detail above. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A high frequency digital signal down modulation system, comprising:
a digital signal modulation circuit (11), a high-frequency signal input end (12), a voltage signal output end (13) and a voltage signal identification device (14);
The high-frequency signal input end (12) is connected with the digital signal modulation circuit (11), the digital signal modulation circuit (11) is connected with the voltage signal output end (13), the voltage signal output end (13) is connected with the voltage signal identification device (14), the digital signal modulation circuit (11) converts a two-byte level signal input by the high-frequency signal input end (12) into a voltage signal, the voltage signal is output to the voltage signal identification device (14) from the voltage signal output end (13), and the voltage signal identification device (14) is used for identifying the voltage signal;
Wherein the digital signal modulation circuit (11) includes: exclusive-or gate, first not gate, second not gate, third not gate, fourth not gate, fifth not gate, first and gate, second and gate, first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, first operational amplifier circuit, second operational amplifier circuit, third operational amplifier circuit;
Two input ends of the high-frequency signal input end (12) are connected with the input end of the exclusive-or gate, one input end of the exclusive-or gate is connected with the second input end of the first AND gate, the first input end of the second AND gate, the input end of the fifth transistor and the input end of the sixth transistor, the output end of the exclusive-or gate is connected with the input end of the first NOT gate, the control end and the input end of the first transistor and the input end of the second transistor, the output end of the first NOT gate is connected with the control end of the second transistor, the output end of the second NOT gate is connected with the first input end of the first AND gate, the output end of the first AND gate is connected with the input end of the third NOT gate and the control end of the fifth transistor, the output end of the third NOT gate is connected with the control end of the sixth transistor, and the output end of the sixth transistor is connected with the output end of the voltage (13);
The output end of the fifth transistor is connected with the first operational amplification circuit, and the first operational amplification circuit is connected with the voltage signal output end (13);
The output end of the first transistor is connected with the second input end of the second AND gate, the output end of the second AND gate is connected with the input end of the fourth NOT gate, the input end of the third transistor, the input end of the fourth transistor and the control end, the output end of the fourth transistor is connected with the second operational amplifier circuit, and the second operational amplifier circuit is connected with the voltage signal output end (13);
The output end of the fourth NOT gate is connected with the control end of the third transistor, the output end of the third transistor is connected with the input end of the fifth NOT gate, the output end of the fifth NOT gate is connected with the third operational amplifier circuit, and the third operational amplifier circuit is connected with the voltage signal output end (13);
The gain values of the first operational amplifier circuit, the second operational amplifier circuit and the third operational amplifier circuit are different.
2. The high frequency digital signal down modulation system of claim 1, wherein the first operational amplifier circuit comprises: the first resistor, the second resistor and the first operational amplifier; the second operational amplifier circuit includes: the third resistor, the fourth resistor and the second operational amplifier; the third operational amplifier circuit includes: the fifth resistor, the sixth resistor and the third operational amplifier;
the output end of the fifth transistor is connected with the non-inverting input end of the first operational amplifier, the inverting input end of the first operational amplifier is connected with the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is grounded, and the output end of the first operational amplifier is connected with the second end of the second resistor and the voltage signal output end (13);
The output end of the fourth transistor is connected with the non-inverting input end of the second operational amplifier, the inverting input end of the second operational amplifier is connected with the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is grounded, and the output end of the second operational amplifier is connected with the second end of the second resistor and the voltage signal output end (13);
the output end of the fifth NOT gate is connected with the non-inverting input end of the third operational amplifier, the inverting input end of the third operational amplifier is connected with the first end of the fifth resistor and the first end of the sixth resistor, the second end of the fifth resistor is grounded, and the output end of the third operational amplifier is connected with the second end of the sixth resistor and the voltage signal output end (13).
3. The high frequency digital signal down modulation system of claim 2, further comprising: a seventh resistor;
And the output end of the fifth transistor is connected with the non-inverting input end of the first operational amplifier through the seventh resistor.
4. The high frequency digital signal down modulation system of claim 2, further comprising: an eighth resistor;
And the output end of the fourth transistor is connected with the non-inverting input end of the second operational amplifier through the eighth resistor.
5. The high frequency digital signal down modulation system of claim 2, further comprising: a ninth resistor;
And the output end of the fifth NOT gate is connected with the non-inverting input end of the third operational amplifier through the ninth resistor.
6. The system according to any one of claims 1 to 5, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type MOS transistors.
7. The high frequency digital signal down modulation system of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NPN transistors.
8. The high frequency digital signal down modulation system of claim 2, wherein the first, second, and third op-amps are LM307.
9. The high frequency digital signal down modulation system of claim 1, wherein the first not gate, the second not gate, the third not gate, the fourth not gate, and the fifth not gate are CD4069.
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