WO2022032526A1 - Capteur de surveillance et puce - Google Patents

Capteur de surveillance et puce Download PDF

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Publication number
WO2022032526A1
WO2022032526A1 PCT/CN2020/108708 CN2020108708W WO2022032526A1 WO 2022032526 A1 WO2022032526 A1 WO 2022032526A1 CN 2020108708 W CN2020108708 W CN 2020108708W WO 2022032526 A1 WO2022032526 A1 WO 2022032526A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal
monitored
monitoring
xor
Prior art date
Application number
PCT/CN2020/108708
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English (en)
Chinese (zh)
Inventor
赛高乐
欧勇盛
段圣宇
王志扬
徐升
熊荣
刘超
冯伟
吴新宇
Original Assignee
深圳先进技术研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 深圳先进技术研究院 filed Critical 深圳先进技术研究院
Priority to PCT/CN2020/108708 priority Critical patent/WO2022032526A1/fr
Publication of WO2022032526A1 publication Critical patent/WO2022032526A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to monitoring sensors and chips.
  • Digital integrated circuits are widely used in key fields such as production, life and military. Driven by market demand, the feature size of integrated circuits has been greatly reduced, with the accompanying increase in process variation in production, voltage and temperature variation during operation, and aging phenomenon (PVTA) during its life cycle. As a result, the reliability of integrated circuits faces severe challenges.
  • the DVFS system dynamically adjusts the operating frequency and voltage of the chip according to the different needs of the applications running on the chip for computing power (for the same chip, the higher the frequency, the higher the required voltage), so as to achieve the purpose of energy saving.
  • the present application provides a monitoring sensor and a chip to solve the problem in the prior art that multi-channel data cannot be monitored for jumps.
  • the present application proposes a monitoring sensor, including a logic operation circuit, which is used to perform an XOR logic operation on a plurality of input signals to be monitored, and output an operation result signal; wherein, the signal to be monitored is It is a digital signal; a monitoring circuit, which is connected to a logic operation circuit, is used to monitor the jumping situation of the operation result signal, so as to monitor multiple monitoring signals.
  • the present application proposes a chip including the above monitoring sensor.
  • the present application discloses a monitoring sensor, comprising a logic operation circuit and a monitoring circuit, wherein the logic operation circuit is used to perform an XOR logic operation on a plurality of input signals to be monitored, and output an operation result signal, and the to-be-monitored signal is a digital signal;
  • the monitoring circuit is connected to the logic operation circuit, and is used for monitoring the jumping situation of the operation result signal, so as to monitor multiple monitoring signals. Since the probability of the same propagation delay of the data of different paths is close to zero, the monitoring sensor in this application can use the logic operation circuit to perform XOR logic operation on a plurality of signals to be monitored to obtain the operation result signal.
  • the operation result signal jumps
  • the monitoring circuit detects that the operation result signal jumps, that is, a corresponding error prompt signal is generated.
  • the monitoring sensor of the present application can perform jump monitoring on multiple channels of data at the same time, thereby improving the monitoring efficiency; in addition, the monitoring sensor has a simple circuit, high compatibility, low space cost during construction, and no additional fault tolerance in the circuit. circuit.
  • FIG. 1 is a schematic structural diagram of an embodiment of a monitoring sensor of the present application.
  • Fig. 2 is the time sequence waveform schematic diagram of the monitoring sensor in Fig. 1;
  • FIG. 3 is a schematic structural diagram of an embodiment of a monitoring circuit of the present application.
  • FIG. 4 is a schematic diagram of a circuit structure of an embodiment of the monitoring circuit in FIG. 1;
  • FIG. 5 is a schematic structural diagram of an embodiment of an XOR gate unit of the present application.
  • FIG. 6 is a schematic diagram of the circuit structure of an embodiment of the XOR gate unit of the present application.
  • FIG. 7 is a schematic structural diagram of an embodiment of a multiplexed logic operation circuit of the present application.
  • FIG. 8 is a schematic structural diagram of another embodiment of a multiplexed logic operation circuit of the present application.
  • FIG. 9 is a schematic structural diagram of another embodiment of a multiplexed logic operation circuit of the present application.
  • FIG. 10 is a waveform diagram of the present application when monitoring a plurality of signals to be monitored at the same time;
  • 11 is a probability analysis diagram of the transition of a plurality of signals to be monitored in the present application.
  • FIG. 12 is a schematic diagram of an application scenario of the monitoring sensor of the present application.
  • FIG. 1 is a schematic structural diagram of an embodiment of a monitoring sensor of the present application
  • FIG. 2 is a schematic diagram of a timing waveform of the monitoring sensor in FIG. 1
  • the monitoring sensor 100 may include a logic operation circuit 110 and a monitoring circuit 120 .
  • the logic operation circuit 110 can be used to perform an exclusive OR logic operation on a plurality of input signals to be monitored, and output an operation result signal X.
  • the signal to be monitored may be a digital signal.
  • a plurality of to-be-monitored signals P 1 ⁇ PN may be included.
  • the signal to be monitored is the information to be monitored in the critical path in the corresponding digital integrated circuit.
  • the monitoring circuit 120 may be connected to the logic operation circuit 110 .
  • the monitoring circuit 120 can be used to monitor the transition of the operation result signal X, so as to monitor a plurality of monitoring signals P 1 ⁇ PN .
  • FIG. 3 is a schematic structural diagram of an embodiment of a monitoring circuit of the present application.
  • the monitoring circuit 120 may include a first input terminal and a second input terminal.
  • the first input terminal can be connected to the logic operation circuit 110, the second input terminal can be used to input the clock signal CLK, and the monitoring circuit 120 can be used to monitor the transition of the operation result signal X during the high level of the clock signal CLK, and generate a corresponding signal.
  • the error prompt signal Error Error.
  • the monitoring circuit 120 does not work and cannot generate the corresponding error prompt signal Error; during the high level period of the clock signal CLK, the monitoring circuit 120 does not monitor the jump of the operation result signal X. If it changes, the corresponding error prompt signal Error will not be generated.
  • the rising edge of the error prompt signal Error can correspond to the transition time of the operation result signal X
  • the falling edge of the error prompt signal Error can correspond to the falling edge of the clock signal CLK. Therefore, in fact, the rising edge of the error prompt signal Error is slightly later than the transition time of the operation result signal X, and the falling edge of the error prompt signal Error is slightly later than the falling edge of the clock signal CLK.
  • the working time of the monitoring circuit 120 is half a clock cycle, the starting point corresponds to the rising edge of the clock signal CLK, and the ending point corresponds to the falling edge of the clock signal CLK.
  • the monitoring circuit 120 monitors the operation result signal X during the working time.
  • the monitoring interval of the monitoring circuit 120 for the signal to be monitored in this embodiment is earlier than the working time of the monitoring circuit 120 by an XOR gate unit propagation delay. time. The time after the signal to be monitored actually jumps to when the operation result signal X is received by the monitoring circuit 120 is regarded as the propagation delay of an XOR gate unit.
  • the monitored signal If the monitored signal is inverted at a certain point in time, it will cause Level inversion occurs, that is, the operation result signal X is inverted.
  • the error prompt signal Error of the monitoring circuit 120 When the to-be-monitored signal flips within the monitoring interval, the error prompt signal Error of the monitoring circuit 120 will be triggered, and the error prompt signal Error will be cleared after the falling edge of the clock signal CLK.
  • FIG. 4 is a schematic diagram of a circuit structure of an embodiment of the monitoring circuit in FIG. 1 .
  • the monitoring circuit may include 10 transistors and 1 inverter.
  • the control end of the first transistor T1 receives the clock signal CLK, and the first end of the first transistor T1 is connected to the working power supply VDD; the control end of the second transistor T2 receives the clock signal CLK, and the first end of the second transistor T2 is connected to the working power supply VDD; The control terminal of the third transistor T3 receives the operation result signal X, and the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1.
  • the first end of the fourth transistor T4 is connected to the second end of the first transistor T1; the input end of the first inverter N1 receives the operation result signal X; the control end of the fifth transistor T5 is connected to the output end of the first inverter N1 , the first end of the fifth transistor T5 is connected to the second end of the second transistor T2.
  • the first end of the sixth transistor T6 is connected to the second end of the second transistor T2; the control end of the seventh transistor T7 receives the clock signal CLK, and the first end of the seventh transistor T7 is connected to the second end of the fifth transistor T5 and the sixth The second end of the transistor T6 and the second end of the seventh transistor T7 are grounded.
  • the control end of the eighth transistor T8 is connected between the second end of the first transistor T1, the first end of the third transistor T3, and the first end of the fourth transistor T4, and the first end of the eighth transistor T8 is connected to the working power supply VDD .
  • the control terminal of the ninth transistor T9 is connected between the second terminal of the second transistor T2, the first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6, and the first terminal of the ninth transistor T9 is connected to the eighth transistor The second end of T8.
  • the control end of the tenth transistor T10 is connected to the second end of the third transistor T3, the second end of the fourth transistor T4, the second end of the fifth transistor T5, the second end of the sixth transistor T6 and the first end of the seventh transistor T7.
  • One end, the first end of the tenth transistor T10 is connected to the second end of the ninth transistor T9, and the second end of the tenth transistor T10 is grounded.
  • control terminal of the fourth transistor T4 the control terminal of the sixth transistor T6, the second terminal of the ninth transistor T9 and the first terminal of the tenth transistor T10 are connected, and the node thereof serves as the first output terminal.
  • the first transistor T1, the second transistor T2, the eighth transistor T8 and the ninth transistor T9 may be PMOS transistors
  • the seventh transistor T7 and the tenth transistor T10 may be NMOS transistors.
  • the second end of the first transistor T1, the first end of the third transistor T3, the first end of the fourth transistor T4, and the control end of the eighth transistor T8 are connected, and the node is a; the second end of the second transistor T2 terminal, the first terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 and the control terminal of the ninth transistor T9 are connected, and the node is b; the second terminal of the third transistor T3, the second terminal of the fourth transistor T4 The terminal, the second terminal of the fifth transistor T5, the second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7 and the control terminal of the tenth transistor T10 are connected, and the node is c.
  • the first transistor T1 and the second transistor T2 are turned on, and the seventh transistor T7 is turned off. Nodes a and b are charged and are high.
  • the eighth transistor T8 and the ninth transistor T9 are turned off.
  • One of the third transistor T3 and the fifth transistor T5 is turned on (the third transistor T3 is turned on when the operation result signal X is at a high level, and the fifth transistor T5 is turned on when the operation result signal X is at a low level), the node c is charged (high level), the tenth transistor T10 is turned on, and the first output terminal is discharged and cleared. Therefore, when the clock signal CLK is at a low level, regardless of whether the first input terminal inputs a high level or a low level, the first output terminal is cleared.
  • the first transistor T1 and the second transistor T2 are turned off, the seventh transistor T7 is turned on, the node c is discharged and cleared, and the tenth transistor T10 is turned off.
  • One of the third transistor T3 and the fifth transistor T5 is turned on (the third transistor T3 is turned on when the operation result signal X is at a high level, and the fifth transistor T5 is turned on when the operation result signal X is at a low level), that is, the node Either a or b will be cleared by discharge.
  • one of the eighth transistor T8 and the ninth transistor T9 is not turned on and the tenth transistor T10 is turned off, the first output terminal cannot be charged or discharged, so the value of the first output terminal remains unchanged. It is monitored that the operation result signal X jumps, and the nodes a and b that have not been discharged and cleared will be cleared, resulting in the eighth transistor T8 and the ninth transistor T9 being turned on at the same time, and the first output terminal is charged at this time, that is Output a high level signal to generate the corresponding error prompt signal Error. Therefore, when the clock signal CLK is at a high level, the operation result signal X jumps, and the first output terminal outputs a high level.
  • the XOR gate unit may be a 2-input XOR gate.
  • the logic operation circuit 110 responds that the total number of high levels of the M signals to be monitored is an even number, and the output operation result signal X is a low level; the logic operation circuit 110 outputs an odd number in response to the total number of high levels of the M signals to be monitored.
  • the operation result signal X is high level.
  • FIG. 5 is a schematic structural diagram of an XOR gate unit according to an embodiment of the present application
  • FIG. 6 is a schematic circuit structure diagram of an XOR gate unit according to an embodiment of the present application.
  • the XOR gate unit 111 includes a first XOR input terminal A, a second XOR input terminal B, and a first XOR output terminal Z.
  • first XOR input terminal A and the second XOR input terminal B may be used for receiving the signal to be monitored or the first XOR output terminal of other XOR gate units.
  • the first XOR output terminal Z can be connected to the first XOR input terminal or the second XOR input terminal of other XOR gate units, or connected to the monitoring circuit 120 to output the operation result signal X.
  • the circuit structure of the XOR gate unit 111 may include a second inverter N2 and four transistors T11-T14.
  • the input terminal of the second inverter N2 is connected to the first XOR input terminal.
  • the control terminals of the eleventh transistor T11 and the twelfth transistor T12 are connected to the second XOR input terminal, the first terminal of the eleventh transistor T11 is connected to the first XOR input terminal, and the first terminal of the twelfth transistor T12 is connected to the first XOR input terminal.
  • the second terminal of the twelfth transistor T12, the control terminal of the fourteenth transistor T14 and the output terminal of the second inverter N2 are connected.
  • the first terminal of the eleventh transistor T11 and the control terminal of the thirteenth transistor T13 are connected to the first XOR input terminal.
  • the first end of the thirteenth transistor T13 is connected to the first end of the fourteenth transistor, and its node is connected between the first end of the eleventh transistor T11 and the second end of the twelfth transistor T12, and the node of the four A first XOR output can be connected.
  • the second terminal of the thirteenth transistor T13 is connected to the second terminal of the fourteenth transistor T14, and the node thereof is connected to the second XOR input terminal.
  • the eleventh transistor T11 and the twelfth transistor T12 are turned off, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the first XOR output terminal and the second XOR The levels at the inputs are the same.
  • the first XOR input terminal is at a high level, the thirteenth transistor T13 and the fourteenth transistor T14 are turned off, the inverter composed of the eleventh transistor T11 and the twelfth transistor T12 is turned on, and the first XOR output terminal is turned on. Opposite to the level of the second XOR input. which is
  • the eleventh transistor T11 and the thirteenth transistor T13 may be PMOS transistors, and the twelfth transistor T12 and the fourteenth transistor T14 may be NMOS transistors.
  • FIG. 7 is a schematic structural diagram of an embodiment of the multi-path logic operation circuit of the present application
  • FIG. 8 is a structural schematic diagram of another embodiment of the multi-path logic operation circuit of the present application
  • FIG. 9 is a multi-path logic operation circuit of the present application.
  • Figure 7 is a 3-input XOR gate
  • Figure 8 is a 4-input XOR gate
  • Figure 9 is a 10-input XOR gate.
  • Z represents the output terminal of the multiple-input XOR gate
  • A-J represent each input terminal of the multiple-input XOR gate.
  • two XOR gate units 111 may be included, and the output end of the first XOR gate unit may be connected to the input end of the second XOR gate unit, thus obtaining
  • three XOR gate units 111 may be included, and the output terminal of the first XOR gate unit and the output terminal of the second XOR gate unit may be respectively connected to the third XOR gate unit. the first input and the second input, resulting in
  • nine XOR gate units 111 may be included, and the two input terminals of the fifth XOR gate unit are respectively connected to the output terminal of the first XOR gate unit and the second XOR gate unit.
  • the output terminal of the sixth XOR gate unit is respectively connected to the output terminal of the signal to be monitored and the third XOR gate unit, and the two input terminals of the seventh XOR gate unit are respectively connected to the signal to be monitored and the fourth XOR gate unit.
  • the output terminal of the XOR gate unit; the two input terminals of the eighth XOR gate unit are respectively connected to the output terminal of the sixth XOR gate unit and the output terminal of the seventh XOR gate unit, and the two input terminals of the ninth XOR gate unit are respectively connected.
  • the input terminals are respectively connected to the output terminal of the fifth XOR gate unit and the output terminal of the eighth XOR gate unit, thus obtaining
  • the operation result signal X output by the logic operation circuit 110 is a low level.
  • the fourth XOR gate unit outputs a low level
  • the output terminal Z of the ninth XOR gate unit also outputs a low level, that is, when the same XOR gate unit receives
  • the operation result signal X output by the logic operation circuit 110 is also low level.
  • the first XOR gate unit When only B, C, E, and F input high level, the first XOR gate unit outputs a high level, the second XOR gate unit outputs a high level, and the fifth XOR gate unit outputs a low level; the third XOR gate unit outputs a low level; The XOR gate unit outputs a high level, the sixth XOR gate unit outputs a low level, and finally the output terminal Z of the ninth XOR gate unit also outputs a low level; that is, when different XOR gate units receive even numbers to be monitored When the signals are all input at a high level, the operation result signal X output by the logic operation circuit 110 is also at a low level.
  • the operation result signal X output by the logic operation circuit 110 is a high level.
  • the first XOR gate unit outputs a high level
  • the fifth XOR gate unit also outputs a high level
  • the output terminal Z of the ninth XOR gate unit also outputs a high level .
  • the first XOR gate unit When only A, C, and H input high level, the first XOR gate unit outputs a high level, the second XOR gate unit outputs a high level, the fifth XOR gate unit outputs a low level, and the seventh XOR gate unit outputs a low level.
  • the gate unit outputs a high level, the eighth XOR gate unit outputs a high level, and finally the output terminal Z of the ninth XOR gate unit also outputs a high level, that is, as long as the total number of high levels of the signals to be monitored is odd, the logic
  • the operation result signal X output by the operation circuit 110 is a high level.
  • the number of XOR gate units passing through the path from the input to the output of each signal to be monitored can be (rounded down) to (rounded up).
  • FIG. 10 is a waveform diagram of the present application when multiple signals to be monitored are simultaneously monitored
  • FIG. 11 is a probability analysis diagram of the transition of multiple signals to be monitored in the present application.
  • Pi and Pj are two signals to be monitored.
  • the logic operation circuit 110 responds that the total number of high levels of the M signals to be monitored is an even number, and the output operation result signal X is a low level” and the situation in FIG. (a) Not contradictory: this is due to the propagation delay in the logic operation circuit 110 .
  • the rising edge of the operation result signal X corresponds to the rising edge of Pj (at this time Pi is low level, Pj is high level), and the falling edge of the operation result signal X corresponds to Pi
  • the rising edge of (Pi is high level at this time, Pj is high level).
  • the propagation delay in Figure (a)
  • "Pi is low level, Pj is high level the total number of high levels of the signal to be monitored is an even number, but the operation result signal X is low level. Case".
  • each signal monitoring point has a 50% probability of receiving a signal of '0' or '1'
  • the probability of signal flipping is 25%.
  • the probability of an even number of data in the to-be-monitored signal being inverted is 50%.
  • voltage and frequency are not adjusted for a single false early warning signal. If the adjustment period is 1000 clock cycles, the probability that the signal flips are all even numbers is (50%) 1000 (close to 0).
  • the present application also proposes a chip.
  • the monitoring sensor 100 can be applied in a chip.
  • FIG. 12 is a schematic diagram of an application scenario of the monitoring sensor of the present application.
  • the chip may further include a D flip-flop 200, the D flip-flop 200 may be connected to the signal to be monitored, and the input end of the monitoring sensor 100 may be connected between the interface of the D flip-flop 200 and the signal to be monitored.
  • the present application discloses a monitoring sensor and a chip.
  • the monitoring sensor includes a logic operation circuit and a monitoring circuit, wherein the logic operation circuit is used to perform XOR logic operation on a plurality of input signals to be monitored, and output the operation result signal. It is a digital signal; the monitoring circuit is connected to the logic operation circuit for monitoring the jumping situation of the operation result signal, so as to monitor multiple monitoring signals.
  • the monitoring sensor in this application can use the XOR gate to perform the XOR logic operation on multiple signals to be monitored, and the output of the XOR gate will be reversed by using a single signal transition It extracts the information of the transition of multiple signals to be monitored at the same time, and obtains the operation result signal.
  • the operation result signal jumps, and the monitoring circuit detects that the operation result signal jumps, that is, a corresponding error is generated. cue signal.
  • the current single sensor can only monitor one potential critical path.
  • the system construction cost of DVFS and related applications will increase. and increased complexity.
  • the monitoring sensor of the present application can use a single sensor to monitor multiple signals to be monitored, that is, multiple potential critical paths, so as to reduce the construction cost and complexity of DVFS and related application scenarios.
  • the monitoring sensor circuit of the present application is simple, the number of transistors is greatly reduced, and the input and output signals are simplified.
  • the monitoring sensor of the present application can reduce the system construction cost and complexity in various application scenarios; and the monitoring sensor of the present application can be built without replacing any components of the original circuit, so the monitored circuit can be reserved in the design. The initial optimal solution.
  • the monitoring sensor of the present application can not only be used in the DVFS system, but also can be used to monitor other soft errors, such as single event flipping and the like.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Capteur de surveillance et puce. Le capteur de surveillance comprend : un circuit d'opération logique (110) utilisé pour effectuer une opération OU exclusif logique sur de multiples signaux d'entrée à surveiller, et pour émettre en sortie un signal de résultat d'opération, les signaux à surveiller constituant des signaux numériques ; et un circuit de surveillance (120) connecté au circuit d'opération logique (110) et utilisé pour surveiller une transition du signal de résultat d'opération, ce qui permet d'effectuer une surveillance des multiples signaux. Grâce au procédé précité, le capteur de surveillance peut surveiller des transitions de signal de multiples trajets de données, ce qui permet d'améliorer l'efficacité de surveillance.
PCT/CN2020/108708 2020-08-12 2020-08-12 Capteur de surveillance et puce WO2022032526A1 (fr)

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PCT/CN2020/108708 WO2022032526A1 (fr) 2020-08-12 2020-08-12 Capteur de surveillance et puce

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Application Number Priority Date Filing Date Title
PCT/CN2020/108708 WO2022032526A1 (fr) 2020-08-12 2020-08-12 Capteur de surveillance et puce

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115529052A (zh) * 2022-09-28 2022-12-27 苏州浪潮智能科技有限公司 一种高频数字信号降频调制系统

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US5449960A (en) * 1992-03-30 1995-09-12 Nec Corporation Sample-and-hold circuit
US6016564A (en) * 1996-08-28 2000-01-18 Matsushita Electric Industrial Co., Ltd. Method of design for testability, method of design for avoiding bus error and integrated circuit
CN101841237A (zh) * 2009-03-19 2010-09-22 恩益禧电子股份有限公司 包括电源可控区域的半导体集成电路
US20120049875A1 (en) * 2010-08-30 2012-03-01 Belser Mitchell A Schmitt trigger with test circuit and method for testing
CN102798815A (zh) * 2011-05-27 2012-11-28 Arm有限公司 状态保留电路中状态完整性的检验
CN105631077A (zh) * 2014-11-07 2016-06-01 飞思卡尔半导体公司 具有增大的故障覆盖率的集成电路
US9513335B1 (en) * 2015-06-12 2016-12-06 Cadence Design Systems, Inc. Method for using XOR trees for physically efficient scan compression and decompression logic
CN112230130A (zh) * 2020-08-12 2021-01-15 深圳先进技术研究院 监测传感器及芯片

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449960A (en) * 1992-03-30 1995-09-12 Nec Corporation Sample-and-hold circuit
US6016564A (en) * 1996-08-28 2000-01-18 Matsushita Electric Industrial Co., Ltd. Method of design for testability, method of design for avoiding bus error and integrated circuit
CN101841237A (zh) * 2009-03-19 2010-09-22 恩益禧电子股份有限公司 包括电源可控区域的半导体集成电路
US20120049875A1 (en) * 2010-08-30 2012-03-01 Belser Mitchell A Schmitt trigger with test circuit and method for testing
CN102798815A (zh) * 2011-05-27 2012-11-28 Arm有限公司 状态保留电路中状态完整性的检验
CN105631077A (zh) * 2014-11-07 2016-06-01 飞思卡尔半导体公司 具有增大的故障覆盖率的集成电路
US9513335B1 (en) * 2015-06-12 2016-12-06 Cadence Design Systems, Inc. Method for using XOR trees for physically efficient scan compression and decompression logic
CN112230130A (zh) * 2020-08-12 2021-01-15 深圳先进技术研究院 监测传感器及芯片

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115529052A (zh) * 2022-09-28 2022-12-27 苏州浪潮智能科技有限公司 一种高频数字信号降频调制系统
CN115529052B (zh) * 2022-09-28 2024-04-30 苏州浪潮智能科技有限公司 一种高频数字信号降频调制系统

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