CN111273722B - Double-ring control band-gap reference circuit with high power supply rejection ratio - Google Patents

Double-ring control band-gap reference circuit with high power supply rejection ratio Download PDF

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CN111273722B
CN111273722B CN202010080566.5A CN202010080566A CN111273722B CN 111273722 B CN111273722 B CN 111273722B CN 202010080566 A CN202010080566 A CN 202010080566A CN 111273722 B CN111273722 B CN 111273722B
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nmos
transistor
pmos
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CN111273722A (en
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明鑫
刘媛媛
范子威
张志文
王卓
张波
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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Abstract

A double-ring control band-gap reference circuit with high power supply rejection ratio belongs to the technical field of power supply management. According to the invention, a double-loop control mode is provided to generate band-gap reference voltage, the first loop ensures that the collector potentials of the second NPN bipolar junction transistor and the third NPN bipolar junction transistor are the same by using the high-gain characteristic of the first operational amplifier, so that reference voltage with accurate temperature characteristic is generated, the second loop generates local power supply voltage irrelevant to power supply voltage fluctuation by using the negative feedback characteristic of the second operational amplifier after the reference is established, the disturbance of the power supply voltage is subjected to negative feedback isolation, and the power supply rejection ratio of the reference circuit is improved. The invention can ensure the accuracy of the reference voltage, obtain high power supply rejection ratio and realize the output of the reference voltage with the change rate of 20.38 ppm/DEG C.

Description

Double-ring control band-gap reference circuit with high power supply rejection ratio
Technical Field
The invention belongs to the technical field of Power Supply management, and particularly relates to a double-loop control band-gap reference circuit which has a high Power Supply Rejection Ratio (PSRR).
Background
Analog circuits widely use various reference voltages and reference currents as signal biases for the circuits. The reference is a current or a dc voltage that is not affected by a power supply change and has a specific change relationship with an absolute temperature. In the digital-analog hybrid circuit, the power supply voltage fluctuation is large, so the local power supply voltage of the core circuit generally employs a low-sensitivity voltage generated by the reference circuit. Since most process parameters vary with temperature, the design of the bandgap reference circuit is required to control to ensure that the required bias voltage or current is not affected by ambient temperature.
It has been proven that the physical parameters of the bipolar transistor are the most reproducible in experiments and have parameters of positive and negative temperature coefficients, so that the reference circuit related to temperature generally consists of bipolar transistors. The bipolar transistor consists of two PN junctions, wherein the forward voltage drop of the PN junction, i.e. the base-emitter voltage VBEIs inversely proportional to the temperature T and satisfies:
Figure DEST_PATH_IMAGE002
wherein VBERefers to bipolar transistor base-emitter voltage; m is a parameter of the carrier mobility in the bipolar transistor changing along with the temperature; vTRefers to the threshold voltage of a bipolar transistor and VT= kT/q; eg refers to the band gap energy of silicon and Eg is approximately equal to 1.12 eV; q denotes the charge amount of a single electron;
Figure DEST_PATH_IMAGE004
finger pair VBECalculating a partial derivative of T; k denotes the Boltzmann constant
From this, V is knownBEInversely proportional to temperature and to VBEThe size of the device is related to the size of the device. Two bipolar transistors have a base-emitter voltage V when they are operated at different collector or emitter currentsBEDifference value Δ V ofBEIs in direct proportion to the temperature and satisfies the following conditions:
Figure DEST_PATH_IMAGE006
wherein n is the ratio of the collector areas of the two bipolar transistors, and the reference voltage V which is a physical parameter independent of temperature can be generated by connecting the two physical parameters with temperature in opposite trend changes with a certain proportionality coefficientref：
Figure DEST_PATH_IMAGE008
Wherein
Figure DEST_PATH_IMAGE010
、
Figure DEST_PATH_IMAGE012
Refers to any parameter. A conventional bandgap reference circuit is shown in FIG. 1, operational amplifier A0Provide a large loop gain when it isWhen the output is established, the differential operational amplifier A0Are clamped to the same potential, so the difference Δ V between the base-emitter voltages of Q1 and Q2BEIs a resistance RPTATVoltage drop on the reference voltage VrefAnd satisfy
Figure DEST_PATH_IMAGE014
，VBE2Is the base-emitter voltage of Q2. And obtaining the reference voltage by designing the resistance value of the resistor and the value of n. However, when the input power voltage changes, the reference voltage is directly affected by the power ripple, which causes the drift of the reference voltage and the poor power supply rejection ratio of the circuit.
Disclosure of Invention
Aiming at the problem that the reference voltage generated by the traditional single-ring controlled band-gap reference circuit is affected by power supply ripple waves to cause poor power supply rejection ratio, the invention provides the double-ring controlled band-gap reference circuit, wherein the first loop utilizes the high gain characteristic of an operational amplifier to ensure that the collector potentials of a second NPN bipolar junction transistor NPN2 and a third NPN bipolar junction transistor NPN3 are the same so as to generate the reference voltage with accurate temperature characteristic, and the second loop utilizes the negative feedback characteristic of the operational amplifier to generate the local power supply voltage irrelevant to the fluctuation of the input power supply voltage after the reference is established, so that the disturbance of the input power supply voltage is subjected to negative feedback isolation, and the power supply rejection ratio of the reference circuit is improved.
The technical scheme of the invention is as follows:
a double-ring control band gap reference circuit with a high power supply rejection ratio comprises a first NPN bipolar junction transistor, a second NPN bipolar junction transistor, a third NPN bipolar junction transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a plurality of fourth NMOS tubes, an eighth NMOS tube, a ninth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NLDMOS tube, a second NLDMOS tube, a third NLDMOS tube, a fourth DMOS NLDMOS tube, a first PLDMOS tube, a first operational amplifier and a second operational amplifier;
the grid electrode of the fifth PMOS tube is connected with a first bias voltage, the source electrode of the fifth PMOS tube is connected with the drain electrodes of the third NLDMOS tube and the fourth NLDMOS tube and is connected with an input power voltage, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the first PLDMOS tube;
the grid electrode of the first PLDMOS is connected with a second bias voltage, and the drain electrode of the first PLDMOS is connected with the grid electrode and the drain electrode of the second NLDMOS tube and the grid electrode of the third NLDMOS tube;
the grid-drain short circuit of the sixth PMOS tube is connected with the drain electrodes of the eighth NMOS tube and the ninth NMOS tube, and the source electrode of the sixth PMOS tube is connected with the source electrode of the third NLDMOS tube and the local power supply voltage and is grounded through the second capacitor;
the grid electrode and the drain electrode of each fourth NMOS tube are connected with the source electrode of the previous fourth NMOS tube, the drain electrode of the first fourth NMOS tube is connected with the drain electrode of the first NLDMOS tube, the source electrode of the second NLDMOS tube, the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube, and is grounded through the first capacitor, and the source electrode of the last fourth NMOS tube is grounded;
the negative input end of the first operational amplifier is connected with the source electrode of the eighth NMOS transistor, the collector electrode of the second NPN bipolar junction transistor and one end of the second resistor, the positive input end of the first operational amplifier is connected with the source electrode of the ninth NMOS transistor, the collector electrode of the third NPN bipolar junction transistor and one end of the third resistor, and the output end of the first operational amplifier is connected with the base electrode of the second NPN bipolar junction transistor, the base electrode of the third NPN bipolar junction transistor and the positive input end of the second operational amplifier and outputs reference voltage;
the other ends of the second resistor and the third resistor are connected with the local power supply voltage;
one end of the fourth resistor is connected with the emitter of the second NPN bipolar junction transistor, and the other end of the fourth resistor is connected with the emitter of the third NPN bipolar junction transistor and is grounded through the fifth resistor;
the grid electrode of the fourth NLDMOS tube is connected with the output end of the second operational amplifier, and the source electrode of the fourth NLDMOS tube generates the local power supply voltage and is connected with one end of the sixth resistor;
one end of the seventh resistor is connected with the other end of the sixth resistor and the negative input end of the second operational amplifier, and the other end of the seventh resistor is grounded;
the base electrode of the first NPN bipolar junction transistor is connected with the reference voltage, the emitter electrode of the first NPN bipolar junction transistor is grounded after passing through the first resistor, and the collector electrode of the first NPN bipolar junction transistor is connected with the grid electrode and the drain electrode of the third PMOS tube and the base electrode of the fourth PMOS tube;
the grid-drain short circuit of the first PMOS tube is connected with the source electrode of the third PMOS tube and the grid electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with the local power supply voltage;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube and the grid electrode of the first NLDMOS tube;
the grid electrode of the third NMOS tube is connected with the grid electrode and the drain electrode of the second NMOS tube and the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the first NLDMOS tube, and the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube and grounded.
Specifically, the first operational amplifier comprises a fourth NPN bipolar junction transistor, a fifth NPN bipolar junction transistor, a third capacitor, a fourth capacitor, an eighth resistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor;
a base electrode of the fourth NPN bipolar junction transistor is used as a negative input end of the first operational amplifier, an emitter electrode of the fourth NPN bipolar junction transistor is connected with an emitter electrode of the fifth NPN bipolar junction transistor and a drain electrode of the eighteenth NMOS transistor, and a collector electrode of the fourth NPN bipolar junction transistor is connected with a grid electrode and a drain electrode of the eleventh PMOS transistor and a grid electrode of the ninth PMOS transistor;
a base electrode of the fifth NPN bipolar junction transistor is used as a positive input end of the first operational amplifier, and a collector electrode of the fifth NPN bipolar junction transistor is connected with a grid electrode and a drain electrode of the twelfth PMOS tube and a grid electrode of the thirteenth PMOS tube;
the grid electrode of the eighteenth NMOS tube is connected with the grid electrode of the tenth NMOS tube and the third bias voltage, and the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the nineteenth NMOS tube;
the grid electrode of the nineteenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube and the fourth bias voltage, and the source electrode of the nineteenth NMOS tube is connected with the source electrodes of the eleventh NMOS tube, the thirteenth NMOS tube and the fifteenth NMOS tube and is grounded;
the source electrode of the tenth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the fourteenth PMOS tube and the grid electrode and the drain electrode of the eighth PMOS tube;
the grid drain of the seventh PMOS tube is in short circuit connection with the source electrode of the eighth PMOS tube, and the source electrode of the seventh PMOS tube is connected with the source electrodes of the ninth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fifteenth PMOS tube and is connected with the local power supply voltage;
the source electrode of the tenth PMOS tube is connected with the drain electrode of the ninth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the grid electrode and the drain electrode of the twelfth NMOS tube and the grid electrode of the fourteenth NMOS tube;
the grid electrode of the fifteenth NMOS tube is connected with the grid electrode and the drain electrode of the thirteenth NMOS tube and the source electrode of the twelfth NMOS tube, and the drain electrode of the fifteenth NMOS tube is connected with the source electrode of the fourteenth NMOS tube;
a source electrode of the fourteenth PMOS tube is connected with a drain electrode of the thirteenth PMOS tube, a drain electrode of the fourteenth PMOS tube is used as an output end of the first operational amplifier, is connected with a drain electrode of the fourteenth NMOS tube and a grid electrode of the seventeenth NMOS tube, and is connected with a source electrode of the sixteenth NMOS tube through an eighth resistor;
the grid electrode of the sixteenth NMOS tube is connected with the source electrode of the second NLDMOS tube, and the drain electrode of the sixteenth NMOS tube is connected with the grid electrode and the drain electrode of the fifteenth PMOS tube and is grounded through the third capacitor;
the drain electrode of the seventeenth NMOS tube is connected with the local power supply voltage, and the source electrode of the seventeenth NMOS tube is grounded through the fourth capacitor.
Specifically, the second operational amplifier comprises a fifth capacitor, a sixth capacitor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a second PLDMOS transistor, a third PLDMOS transistor, a fourth PLDMOS transistor, a fifth NLDMOS transistor, a sixth NLDMOS transistor, a seventh NLDMOS transistor and an eighth NLDMOS transistor;
a grid electrode of a twentieth NMOS tube is used as a positive input end of the second operational amplifier, a source electrode of the twentieth NMOS tube is connected with a source electrode of a twenty-first NMOS tube, a drain electrode of the twenty-second NMOS tube and a grid electrode of a seventeenth PMOS tube, and a drain electrode of the twentieth NMOS tube is connected with a source electrode of a fifth PLDMOS tube;
the grid electrode of the twenty-first NMOS tube is used as the negative input end of the second operational amplifier and is connected with one end of a sixth capacitor, and the drain electrode of the twenty-first NMOS tube is connected with the source electrode of a sixth NLDMOS tube;
the other end of the sixth capacitor is connected with a source electrode of a fourth NLDMOS tube;
the grid electrode of the twenty-second NMOS tube is connected with a fourth bias voltage, and the source electrode of the twenty-second NMOS tube is connected with the drain electrode of the seventeenth PMOS tube and is grounded;
the grid-drain short circuit of the second PLDMOS tube is connected with the drain electrode of the fifth PLDMOS tube and the grid electrode of the third PLDMOS tube, and the source electrode of the second PLDMOS tube is connected with the source electrode of the third PLDMOS tube, the source electrode of the sixteenth PMOS tube and the drain electrode of the eighth NLDMOS tube and is connected with an input power supply voltage;
the grid electrode of the sixteenth PMOS tube is connected with the first bias voltage, and the drain electrode of the sixteenth PMOS tube is connected with the source electrode of the fourth PLDMOS tube;
the grid electrode of the fourth PLDMOS tube is connected with a second bias voltage, and the drain electrode of the fourth PLDMOS tube is connected with the grid electrode and the drain electrode of the seventh NLDMOS tube, the grid electrode of the fifth PLDMOS tube and the grid electrode of the sixth NLDMOS tube;
the source electrode of the seventh NLDMOS tube is connected with the source electrode of the seventeenth PMOS tube;
the grid electrode of the eighth NLDMOS tube is connected with the grid electrode of the third NLDMOS tube, the source electrode of the eighth NLDMOS tube is connected with the drain electrode of the third PLDMOS tube, the drain electrode of the sixth NLDMOS tube and one end of the fifth capacitor and serves as the output end of the second operational amplifier, and the other end of the fifth capacitor is grounded.
The invention has the beneficial effects that: the band-gap reference circuit provided by the invention is in a double-loop control mode, the first loop utilizes the high-gain characteristic of the first operational amplifier to ensure that the potentials of the collectors of the two NPN bipolar junction transistors NPN2 and NPN3 are the same so as to generate a reference voltage with accurate temperature characteristic, and the second loop utilizes the negative feedback characteristic of the second operational amplifier to generate a local power supply voltage which is irrelevant to the fluctuation of the input power supply voltage after the reference is established, so that the disturbance of the input power supply voltage is subjected to negative feedback isolation, and the power supply rejection ratio of the reference circuit is improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional bandgap reference circuit.
Fig. 2 is a schematic structural diagram of a dual-loop control bandgap reference circuit with a high power supply rejection ratio according to the present invention.
FIG. 3 shows a first operational amplifier A in a dual-loop control bandgap reference circuit with high power supply rejection ratio according to the present invention0A circuit implementation schematic of (1).
FIG. 4 shows a second operational amplifier A in a dual-loop control bandgap reference circuit with high power supply rejection ratio according to the present invention1And a specific circuit diagram of the negative feedback loop.
Fig. 5 is a waveform diagram illustrating an established relationship between a local power supply voltage L1, a source voltage L2 of a second NLDMOS transistor, and a reference voltage L3 according to the present invention.
FIG. 6 is a simulated waveform diagram of the reference voltage variation with temperature generated by the present invention.
Fig. 7 is a simulation diagram of the power supply rejection capability of the double-loop control bandgap reference circuit with high power supply rejection ratio according to the present invention.
Wherein MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16 and MP17 are PMOS (P-Metal-Oxide-Semiconductor) tubes; MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21 and MN22 are NMOS (N-Metal-Oxide-Semiconductor) tubes; r1, R2, R3, R4, R5, R6, R7, R8 are resistors; c1, C2, C3, C4, C5 and C6 are capacitors; the NPN1, the NPN2, the NPN3, the NPN4 and the NPN5 are NPN Bipolar-Junction-Transistor (N-Bipolar-Junction-Transistor) tubes; MHP1, MHP2, MHP3, MHP4 and MHP5 are PLDMOS (P-Laterally-Diffused-Metal-Oxide-Semiconductor) tubes; MHN1, MHN2, MHN3, MHN4, MHN5, MHN6, MHN7 and MHN8 are NLDMOS (N-Laterally-Diffused-Metal-Oxide-Semiconductor) tubes.
Detailed Description
The following further illustrates the principles and embodiments of the present invention with reference to the drawings.
Fig. 2 shows a double-ring control bandgap reference circuit with high power supply rejection ratio according to the present invention, which includes a first NPN bipolar junction transistor NPN1, a second NPN bipolar junction transistor NPN2, a third NPN bipolar junction transistor NPN3, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor 6, a seventh resistor R7, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a plurality of fourth NMOS transistors, an eighth NMOS transistor MN8, a sixth NMOS transistor MN8, a first PMOS transistor MP8, a second PMOS transistor MP8, a third PMOS transistor MP8, a fourth PMOS transistor MP8, a fifth PMOS transistor MP8, a sixth PMOS transistor MP8, a first MHN nln 8, a second PMOS transistor nln 8, a third dmos p8, a fourth dmos p8, a p n p8, a p dmos 8, a p n p80And a second operational amplifier A1The grid electrode of the fifth PMOS pipe MP5 is connected with a first bias voltage bias _1, the source electrode thereof is connected with the drain electrodes of the third NLDMOS pipe MHN3 and the fourth NLDMOS pipe MHN4 and is connected with an input power voltage VDD, and the drain electrode thereof is connected with the source electrode of the first PLDMOS pipe; the grid electrode of the first PLDMOS is connected with a second bias voltage bias _2, and the drain electrode of the first PLDMOS is connected with the grid electrode and the drain electrode of a second NLDMOS tube MHN2 and the grid electrode of a third NLDMOS tube MHN 3; the gate-drain short circuit of the sixth PMOS transistor MP6 is connected to the drains of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9, and the source thereof is connected to the source of the third NLDMOS transistor MHN3 and the local power supply voltage L1 and grounded through the second capacitor C2; as shown in fig. 2, in this embodiment, four fourth NMOS transistors (MN 4-MN 7) are sampled, the drain of the first fourth NMOS transistor, that is, MN4, is connected to the drain of the first NLDMOS transistor MHN1, the source of the second NLDMOS transistor MHN2, the gate of the eighth NMOS transistor MN8, and the gate of the ninth NMOS transistor MN9, and is grounded through the first capacitor C1, and the source of the last fourth NMOS transistor, that is, MN7, is grounded. The negative input end of the first operational amplifier is connected with the source of the eighth NMOS transistor MN8, the collector of the second NPN bipolar junction transistor NPN2, and one end of the second resistor R2, the positive input end of the first operational amplifier is connected with the source of the ninth NMOS transistor MN9, the collector of the third NPN bipolar junction transistor NPN3, and one end of the third resistor R3, and the output end of the first operational amplifier is connected with the second NPN bipolar junction transistor MN9The base of the transistor NPN2, the base of the third NPN bipolar junction transistor NPN3 and the positive input end of the second operational amplifier output a reference voltage; the other ends of the second resistor R2 and the third resistor R3 are connected with a local power supply voltage L1; one end of the fourth resistor R4 is connected to the emitter of the second NPN bipolar junction transistor NPN2, and the other end thereof is connected to the emitter of the third NPN bipolar junction transistor NPN3 and grounded through the fifth resistor R5; the gate of the fourth NLDMOS tube MHN4 is connected to the output terminal of the second operational amplifier, and the source thereof generates a local power supply voltage L1 and is connected to one end of a sixth resistor R6; one end of the seventh resistor R7 is connected with the other end of the sixth resistor R6 and the negative input end of the second operational amplifier, and the other end of the seventh resistor R7 is grounded; the base electrode of the first NPN bipolar junction transistor NPN1 is connected with a reference voltage, the emitter electrode of the first NPN bipolar junction transistor NPN1 is grounded after passing through the first resistor R1, and the collector electrode of the first NPN bipolar junction transistor NPN1 is connected with the grid electrode and the drain electrode of the third PMOS transistor MP3 and the base electrode of the fourth PMOS transistor MP 4; the grid-drain short circuit of the first PMOS transistor MP1 is connected with the source electrode of the third PMOS transistor MP3 and the grid electrode of the second PMOS transistor MP2, and the source electrode of the first PMOS transistor MP1 is connected with the source electrode of the second PMOS transistor MP2 and is connected with the local power supply voltage L1; the source electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the second PMOS transistor MP2, and the drain electrode thereof is connected to the gate electrode and the drain electrode of the first NMOS transistor MN1 and the gate electrode of the first NLDMOS transistor MHN 1; the grid electrode of the third NMOS transistor MN3 is connected with the grid electrode and the drain electrode of the second NMOS transistor MN2 and the source electrode of the first NMOS transistor MN1, the drain electrode of the third NMOS transistor MN3 is connected with the source electrode of the first NLDMOS transistor MHN1, and the source electrode of the third NMOS transistor MN2 is connected with the source electrode of the second NMOS transistor MN2 and grounded.
Substrates of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected with a local power supply voltage L1; substrates of a fifth PMOS pipe MP5 and a first PLDMOS pipe MHP1 are connected with an input power supply voltage VDD; the substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded; the substrate and the source of the first NLDMOS tube MHN1, the second NLDMOS tube MHN2, the third NLDMOS tube MHN3, the fourth LDMOS tube and the sixth PMOS tube MP6 are short-circuited.
The voltage allowable amplitude range of the input power voltage VDD is large, and in order to prevent the MOS tube from being broken down, a high-voltage tube, namely a PLDMOS tube and an NLDMOS tube, is used for high-voltage isolation in the circuit. First bias voltagebias _1 and bias voltage bias _2 are fixed voltage biases, the fifth PMOS transistor MP5 and the first PLDMOS transistor MHP1 are connected to a fixed bias, and then mirror the current to the reference voltage generating part through the current mirror formed by the second NLDMOS transistor MHN2 and the third NLDMOS transistor MHN3, and at the same time charge the first capacitor C1 and the second capacitor C2, wherein the potential L2, i.e., the source end voltage of the second NLDMOS transistor MHN2, is clamped to a higher potential by the serial fourth NMOS transistor (e.g., four fourth NMOS transistors MN4-MN7 in this embodiment) connected by a plurality of diodes, and the potential L2 simultaneously ensures the turn-on of the third NLDMOS transistor MHN3, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN 9. The eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 clamp the collectors of the second NPN bipolar junction transistor NPN2 and the third NPN bipolar junction transistor NPN3 to the same potential, and the first loop operational amplifier, namely the first operational amplifier A0Base potentials are provided for second NPN bipolar junction transistor NPN2 and third NPN bipolar junction transistor NPN3 so that the reference is normally established.
When the reference voltage L3 is established, the second operational amplifier A1The second loop operational amplifier consisting of the fourth NLDMOS tube MHN4, the sixth resistor R6 and the seventh resistor R7 generates a potential which is not influenced by the fluctuation of the input power voltage VDD, namely a local power voltage L1. Meanwhile, the reference voltage L3 is established to turn on the first NPN bipolar junction transistor NPN1, the generated current discharges the L2 potential, that is, the source potential of the second NLDMOS transistor MHN2 through two sets of cascode current mirrors (respectively, a set of cascode current mirror formed by the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4, and a set of cascode current mirror formed by the first NMOS transistor MN1, the first NLDMOS transistor MHN1, the second NMOS transistor MN2, and the third NMOS transistor MN 3), discharges the L2 potential to a potential close to zero, and turns off the third NLDMOS transistor MHN3, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9 to reduce power consumption, and at this time, the reference-generated partial reference voltage power is provided by the local power supply voltage L1. Since the local power supply voltage L1 is a potential that is not affected by fluctuations in the input power supply voltage VDD, the power supply rejection ratio of the reference voltage can be improved. The potential of the nodes L1, L3 and L2 are established as shown in FIG. 5.
Base-emitter voltage difference Δ V of second NPN bipolar junction transistor NPN2 and third NPN bipolar junction transistor NPN3BEFor the voltage drop across the fourth resistor R4, since the currents flowing through the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are the same, and the ratio of the parallel connection of the second NPN bipolar junction transistor NPN2 and the third NPN bipolar junction transistor NPN3 in this embodiment is preferably 8:1, the reference voltage, i.e., the potential of L3 is:
Figure DEST_PATH_IMAGE016
wherein VBE3Is the base-emitter voltage of a third NPN bipolar junction transistor NPN3, and as can be seen from the analysis in the background section, VTlnn is the difference between the base-emitter voltages of the second NPN BJT NPN2 and the third NPN BJT NPN3BE，2△VBEThe current flowing through the fifth resistor R5 is/R4, and the current is positively correlated with Absolute Temperature (PTAT), i.e. 2R5 Δ VBEThe voltage obtained by/R4 is also positively correlated with absolute temperature. Analysis also in conjunction with the background section can yield VBESince the resistance is inversely related to the absolute temperature, a reference voltage value having a specific relationship with the absolute temperature can be obtained by adjusting the ratio of the resistance. The reference voltage temperature coefficient is:
Figure DEST_PATH_IMAGE018
the fifth PMOS pipe MP5 and the first PLDMOS pipe MHP1 provide bias current for the reference circuit through a current mirror formed by the third NLDMOS pipe MHN3 and the second NLDMOS pipe MHN2 after being connected with bias voltage. The rate of change of the reference circuit with temperature is shown in FIG. 6, and the rate of change of the reference voltage is 20.38 ppm/deg.C when the temperature is changed from-40 deg.C to 125 deg.C.
A first operational amplifier a is shown in fig. 30Includes a fourth NPN bipolar junction transistor NPN4, a fifth NPN bipolar junction transistor NPN5, a third capacitor C3, and a fourth capacitor C4. An eighth resistor R8, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a twelfth PMOS tube MP12, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a sixteenth NMOS tube MN16, a seventeenth NMOS tube MN17, an eighteenth NMOS tube MN18 and a nineteenth NMOS tube MN19, and a base of the fourth NPN bipolar junction transistor NPN4 is used as the first operational amplifier A0An emitter of the negative input terminal of (1) is connected with an emitter of a fifth NPN bipolar junction transistor NPN5 and a drain of the eighteenth NMOS transistor MN18, and a collector of the negative input terminal of (2) is connected with a gate and a drain of the eleventh PMOS transistor MP11 and a gate of the ninth PMOS transistor MP 9; the base of a fifth NPN bipolar junction transistor NPN5 is used as the first operational amplifier A0A collector of the positive input terminal of (1) is connected with the gate and the drain of the twelfth PMOS transistor MP12 and the gate of the thirteenth PMOS transistor MP 13; the gate of the eighteenth NMOS transistor MN18 is connected to the gate of the tenth NMOS transistor MN10 and the third bias voltage bias _3, and the source thereof is connected to the drain of the nineteenth NMOS transistor MN 19; the gate of the nineteenth NMOS transistor MN19 is connected to the gate of the eleventh NMOS transistor MN11 and the fourth bias voltage bias _4, and the source thereof is connected to the sources of the eleventh NMOS transistor MN11, the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor MN15 and grounded; the source electrode of the tenth NMOS transistor MN10 is connected to the drain electrode of the eleventh NMOS transistor MN11, and the drain electrode thereof is connected to the gate electrode of the tenth PMOS transistor MP10, the gate electrode of the fourteenth PMOS transistor MP14, and the gate electrode and the drain electrode of the eighth PMOS transistor MP 8; the gate drain of the seventh PMOS transistor MP7 is shorted and connected to the source of the eighth PMOS transistor MP8, and the source thereof is connected to the sources of the ninth PMOS transistor MP9, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the fifteenth PMOS transistor MP15 and connected to the local supply voltage L1; the source electrode of the tenth PMOS transistor MP10 is connected to the drain electrode of the ninth PMOS transistor MP9, and the drain electrode thereof is connected to the gate electrode and the drain electrode of the twelfth NMOS transistor MN12 and the gate electrode of the fourteenth NMOS transistor MN 14; the grid electrode of the fifteenth NMOS tube MN15 is connected with the grid electrode and the drain electrode of the thirteenth NMOS tube MN13 and the source electrode of the twelfth NMOS tube MN12, and the drain electrode of the fifteenth NMOS tube MN15 is connected with the source electrode of the fourteenth NMOS tube MN 14; the source of the fourteenth PMOS transistor MP14 is connected to the drain of the thirteenth PMOS transistor MP13A drain of the first operational amplifier serving as an output end of the first operational amplifier is connected with the drain of the fourteenth NMOS transistor MN14 and the gate of the seventeenth NMOS transistor MN17, and is connected with the source of the sixteenth NMOS transistor MN16 through an eighth resistor R8; the gate of a sixteenth NMOS transistor MN16 is connected to the source of the second NLDMOS transistor, and the drain is connected to the gate and drain of a fifteenth PMOS transistor MP15 and grounded through a third capacitor C3; the drain of the seventeenth NMOS transistor MN17 is connected to the local power supply voltage L1, and the source thereof is grounded through the fourth capacitor C4.
In this embodiment, the third bias voltage bias _3 and the fourth bias voltage bias _4 are fixed bias voltages, and provide bias currents for the operational amplifier. First operational amplifier A0The working process and the working principle in the embodiment are as follows: when the reference voltage L3 has not been established, the local supply voltage L1 has not been supplied by the second operational amplifier A1The negative feedback circuit is clamped, but the potentials of L1 and L2 are charged high and the fifteenth PMOS transistor MP15 and the sixteenth NMOS transistor MN16 are switched on, and the seventeenth NMOS transistor MN17 is switched on by the current generated after the switching on through the eighth resistor R8. The seventeenth NMOS transistor MN17 charges the fourth capacitor C4 and charges the reference voltage L3 high, and provides a base voltage for the second NPN bipolar junction transistor NPN2 and the third NPN bipolar junction transistor NPN3 of the reference generation part to ensure normal generation of the reference voltage, and at this time, the first operational amplifier a0It has not been established normally. When the reference voltage L3 is completely built, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are turned off, and the potential of the node L4 (i.e. the first operational amplifier A) is at this time0Negative input terminal of) and the potential of the node L5 (i.e., the first operational amplifier a)0Positive input terminal of) through a first operational amplifier a0Is clamped to the same voltage. The first operational amplifier A given in this embodiment0The amplifier consists of two stages, the first stage provides high gain for the symmetrical amplifier, and the second stage reduces the output voltage for the source follower. The operational amplifier structure of this embodiment has two advantages: firstly, the differential pair transistors are NPN transistors, and compared with MOS transistors, the triode reduces imbalance of operational amplifier; second, the fully symmetrical form avoids operational amplifier imbalance caused by circuit asymmetry, both of which result in a reference current being generatedThe pressing is more accurate. Therefore, the first operational amplifier A proposed in this embodiment0The structure of (2) can provide high gain and low bandwidth.
A second operational amplifier A is shown in FIG. 41The specific implementation structure of (1) and the specific circuit implementation manner of the negative feedback loop thereof comprise a fifth capacitor C5, a sixth capacitor C6, a twentieth NMOS transistor MN20, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, a second PLDMOS transistor MHP2, a third PLDMOS transistor MHP3, a fourth PLDMOS transistor MHP4, a fifth NLDMOS transistor MHN5, a sixth NLDMOS transistor MHN6, a seventh NLDMOS transistor MHN7 and an eighth NLDMOS transistor MHN8, wherein a gate of the twentieth NMOS transistor MN20 is used as a forward input end of the second operational amplifier, a source of the twentieth NMOS transistor MN21 is connected to the source of the twenty-first NMOS transistor MN21, a drain of the twenty-second NMOS transistor MN22 and a gate of the seventeenth PMOS transistor MP17, and a drain of the twentieth NMOS transistor MN17 is connected to the source; the grid electrode of the twenty-first NMOS tube MN21 is used as the negative input end of the second operational amplifier and is connected with one end of a sixth capacitor C6, and the drain electrode of the twenty-first NMOS tube MN21 is connected with the source electrode of a sixth NLDMOS tube MHN 6; the other end of the sixth capacitor C6 is connected with the source of a fourth NLDMOS tube MHN 4; the gate of the twenty-second NMOS transistor MN22 is connected to the fourth bias voltage bias _4, and the source thereof is connected to the drain of the seventeenth PMOS transistor MP17 and grounded; the grid-drain of the second PLDMOS tube MHP2 is in short circuit and is connected with the drain of the fifth PLDMOS tube and the grid of the third PLDMOS tube MHP3, and the source of the second PLDMOS tube MHP2 is connected with the source of the third PLDMOS tube MHP3, the source of the sixteenth PMOS tube MP16 and the drain of the eighth NLDMOS tube MHN8 and is connected with the input power supply voltage VDD; the gate of the sixteenth PMOS transistor MP16 is connected to the first bias voltage bias _1, and the drain thereof is connected to the source of the fourth PLDMOS transistor MHP 4; the grid of the fourth PLDMOS tube MHP4 is connected with a second bias voltage bias _2, and the drain of the fourth PLDMOS tube MHP4 is connected with the grid and the drain of the seventh NLDMOS tube MHN7, the grid of the fifth PLDMOS tube MHN and the grid of the sixth NLDMOS tube MHN 6; the source electrode of the seventh NLDMOS tube MHN7 is connected with the source electrode of the seventeenth PMOS tube MP 17; the grid electrode of the eighth NLDMOS tube MHN8 is connected with the grid electrode of the third NLDMOS tube MHN3, the source electrode of the eighth NLDMOS tube MHN8 is connected with the drain electrode of the third PLDMOS tube MHP3, the drain electrode of the sixth NLDMOS tube MHN6 and one end of a fifth capacitor C5 and serves as the output end of the second operational amplifier, and the other end of the fifth capacitor C5 is grounded.
Second operational amplifier A1The working process and the working principle in the embodiment are as follows: when the reference voltage L3 is not established, the voltage L1 passes through a third NLDMOS tube MHN3 and a second operational amplifier A in the reference circuit1And a medium eighth NLDMOS tube MHN8 and a fourth NLDMOS tube MHN4 are established. After the reference voltage is established, the third NLDMOS tube MHN3 and the eighth NLDMOS tube MNN8 are closed, the twentieth NMOS tube MN20 is opened, the current generated by the twentieth NMOS tube MHN is mirrored through a current mirror formed by the second PLDMOS tube MHP2 and the third PLDMOS tube MHP3, the grid electrode of the fourth NLDMOS tube MHN4 is charged to be high, the local power supply voltage L1 is charged to be high, and the potential of the generated local power supply voltage L1 is not influenced by the fluctuation of the input power supply voltage VDD. The sixth resistor R6 samples current feedback voltage, when the potential of the input power supply voltage VDD rises, the potential of a local power supply voltage L1 rises, namely the potential of a gate of a twenty-first NMOS tube MN21 rises, after inverse amplification, the potentials of drains of the twenty-first NMOS tube MN21 and a sixth NLDMOS tube MHN6 fall, namely the potential of a gate of a fourth NLDMOS tube MHN4 falls, after forward amplification, the potential of the local power supply voltage L1 falls, namely the local power supply voltage L1 is not influenced by the potential change of the input power supply voltage VDD. The sixth capacitor C6 is used to widen the bandwidth by adding a zero to speed up the negative feedback setup. The seventeenth PMOS transistor MP17 adopts floating gate technology, and when the input voltage of the operational amplifier changes, the gate and source of the eleventh PMOS transistor MP17 change the same, so as to determine the gate potentials of the fifth NLDMOS transistor MHN5, the sixth NLDMOS transistor MHN6 and the seventh NLDMOS transistor MHN 7. Due to the second operational amplifier A provided in the present embodiment1The structure of (1) establishes a local power supply voltage L1 independent of the input power supply voltage VDD, and uses the local power supply voltage L1 as a reference circuit generating section and a first operational amplifier A0The local power supply separates the input power supply voltage VDD disturbance from analog modules such as a reference circuit, and the like, thereby achieving the purpose of improving the power supply rejection ratio.
Fig. 7 is a simulation of the power supply rejection capability of the bandgap reference circuit provided by the present invention, and it can be seen that the power supply rejection ratio PSRR of the bandgap reference circuit provided by the present invention can reach 69.67dB at a low frequency.
The invention adopts a double-loop control mode to generate the reference voltage, ensures the accuracy of the reference voltage and high power supply rejection ratio, and realizes the output of the reference voltage with the change rate of 20.38 ppm/DEG C.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (3)

1. A double-ring control band gap reference circuit with a high power supply rejection ratio is characterized by comprising a first NPN bipolar junction transistor, a second NPN bipolar junction transistor, a third NPN bipolar junction transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a plurality of fourth NMOS tubes, an eighth NMOS tube, a ninth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NLDMOS tube, a second NLDMOS tube, a third NLDMOS tube, a fourth NLDMOS tube, a first PLDMOS tube, a first operational amplifier and a second operational amplifier;
the grid electrode of the fifth PMOS tube is connected with a first bias voltage, the source electrode of the fifth PMOS tube is connected with the drain electrodes of the third NLDMOS tube and the fourth NLDMOS tube and is connected with an input power voltage, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the first PLDMOS tube;
the grid electrode of the first PLDMOS is connected with a second bias voltage, and the drain electrode of the first PLDMOS is connected with the grid electrode and the drain electrode of the second NLDMOS tube and the grid electrode of the third NLDMOS tube;
the grid-drain short circuit of the sixth PMOS tube is connected with the drain electrodes of the eighth NMOS tube and the ninth NMOS tube, and the source electrode of the sixth PMOS tube is connected with the source electrode of the third NLDMOS tube and the local power supply voltage and is grounded through the second capacitor;
the grid electrode and the drain electrode of each fourth NMOS tube are connected with the source electrode of the previous fourth NMOS tube, the drain electrode of the first fourth NMOS tube is connected with the drain electrode of the first NLDMOS tube, the source electrode of the second NLDMOS tube, the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube, and is grounded through the first capacitor, and the source electrode of the last fourth NMOS tube is grounded;
the negative input end of the first operational amplifier is connected with the source electrode of the eighth NMOS transistor, the collector electrode of the second NPN bipolar junction transistor and one end of the second resistor, the positive input end of the first operational amplifier is connected with the source electrode of the ninth NMOS transistor, the collector electrode of the third NPN bipolar junction transistor and one end of the third resistor, and the output end of the first operational amplifier is connected with the base electrode of the second NPN bipolar junction transistor, the base electrode of the third NPN bipolar junction transistor and the positive input end of the second operational amplifier and outputs reference voltage;
the other ends of the second resistor and the third resistor are connected with the local power supply voltage;
one end of the fourth resistor is connected with the emitter of the second NPN bipolar junction transistor, and the other end of the fourth resistor is connected with the emitter of the third NPN bipolar junction transistor and is grounded through the fifth resistor;
the grid electrode of the fourth NLDMOS tube is connected with the output end of the second operational amplifier, and the source electrode of the fourth NLDMOS tube generates the local power supply voltage and is connected with one end of the sixth resistor;
one end of the seventh resistor is connected with the other end of the sixth resistor and the negative input end of the second operational amplifier, and the other end of the seventh resistor is grounded;
the base electrode of the first NPN bipolar junction transistor is connected with the reference voltage, the emitter electrode of the first NPN bipolar junction transistor is grounded after passing through the first resistor, and the collector electrode of the first NPN bipolar junction transistor is connected with the grid electrode and the drain electrode of the third PMOS tube and the base electrode of the fourth PMOS tube;
the grid-drain short circuit of the first PMOS tube is connected with the source electrode of the third PMOS tube and the grid electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with the local power supply voltage;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube and the grid electrode of the first NLDMOS tube;
the grid electrode of the third NMOS tube is connected with the grid electrode and the drain electrode of the second NMOS tube and the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the first NLDMOS tube, and the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube and grounded;
the substrates of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with the local power supply voltage; substrates of a fifth PMOS tube and a first PLDMOS tube are connected with the input power supply voltage; the substrates of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the eighth NMOS tube and the ninth NMOS tube are grounded; the substrate and the source electrode of the first NLDMOS tube, the second NLDMOS tube, the third NLDMOS tube, the fourth LDMOS tube and the sixth PMOS tube are in short circuit.
2. The high power supply rejection ratio double-ring control bandgap reference circuit according to claim 1, wherein the first operational amplifier comprises a fourth NPN bipolar junction transistor, a fifth NPN bipolar junction transistor, a third capacitor, a fourth capacitor, an eighth resistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor;
a base electrode of the fourth NPN bipolar junction transistor is used as a negative input end of the first operational amplifier, an emitter electrode of the fourth NPN bipolar junction transistor is connected with an emitter electrode of the fifth NPN bipolar junction transistor and a drain electrode of the eighteenth NMOS transistor, and a collector electrode of the fourth NPN bipolar junction transistor is connected with a grid electrode and a drain electrode of the eleventh PMOS transistor and a grid electrode of the ninth PMOS transistor;
a base electrode of the fifth NPN bipolar junction transistor is used as a positive input end of the first operational amplifier, and a collector electrode of the fifth NPN bipolar junction transistor is connected with a grid electrode and a drain electrode of the twelfth PMOS tube and a grid electrode of the thirteenth PMOS tube;
the grid electrode of the eighteenth NMOS tube is connected with the grid electrode of the tenth NMOS tube and the third bias voltage, and the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the nineteenth NMOS tube;
the grid electrode of the nineteenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube and the fourth bias voltage, and the source electrode of the nineteenth NMOS tube is connected with the source electrodes of the eleventh NMOS tube, the thirteenth NMOS tube and the fifteenth NMOS tube and is grounded;
the source electrode of the tenth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the fourteenth PMOS tube and the grid electrode and the drain electrode of the eighth PMOS tube;
the grid drain of the seventh PMOS tube is in short circuit connection with the source electrode of the eighth PMOS tube, and the source electrode of the seventh PMOS tube is connected with the source electrodes of the ninth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fifteenth PMOS tube and is connected with the local power supply voltage;
the source electrode of the tenth PMOS tube is connected with the drain electrode of the ninth PMOS tube, and the drain electrode of the tenth PMOS tube is connected with the grid electrode and the drain electrode of the twelfth NMOS tube and the grid electrode of the fourteenth NMOS tube;
the grid electrode of the fifteenth NMOS tube is connected with the grid electrode and the drain electrode of the thirteenth NMOS tube and the source electrode of the twelfth NMOS tube, and the drain electrode of the fifteenth NMOS tube is connected with the source electrode of the fourteenth NMOS tube;
a source electrode of the fourteenth PMOS tube is connected with a drain electrode of the thirteenth PMOS tube, a drain electrode of the fourteenth PMOS tube is used as an output end of the first operational amplifier, is connected with a drain electrode of the fourteenth NMOS tube and a grid electrode of the seventeenth NMOS tube, and is connected with a source electrode of the sixteenth NMOS tube through an eighth resistor;
the grid electrode of the sixteenth NMOS tube is connected with the source electrode of the second NLDMOS tube, and the drain electrode of the sixteenth NMOS tube is connected with the grid electrode and the drain electrode of the fifteenth PMOS tube and is grounded through the third capacitor;
the drain electrode of the seventeenth NMOS tube is connected with the local power supply voltage, and the source electrode of the seventeenth NMOS tube is grounded through the fourth capacitor.
3. The high power supply rejection ratio double-ring control bandgap reference circuit according to claim 1 or 2, wherein the second operational amplifier comprises a fifth capacitor, a sixth capacitor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a second PLDMOS transistor, a third PLDMOS transistor, a fourth PLDMOS transistor, a fifth NLDMOS transistor, a sixth NLDMOS transistor, a seventh NLDMOS transistor and an eighth NLDMOS transistor;
a grid electrode of a twentieth NMOS tube is used as a positive input end of the second operational amplifier, a source electrode of the twentieth NMOS tube is connected with a source electrode of a twenty-first NMOS tube, a drain electrode of the twenty-second NMOS tube and a grid electrode of a seventeenth PMOS tube, and a drain electrode of the twentieth NMOS tube is connected with a source electrode of a fifth PLDMOS tube;
the grid electrode of the twenty-first NMOS tube is used as the negative input end of the second operational amplifier and is connected with one end of a sixth capacitor, and the drain electrode of the twenty-first NMOS tube is connected with the source electrode of a sixth NLDMOS tube;
the other end of the sixth capacitor is connected with a source electrode of a fourth NLDMOS tube;
the grid electrode of the twenty-second NMOS tube is connected with a fourth bias voltage, and the source electrode of the twenty-second NMOS tube is connected with the drain electrode of the seventeenth PMOS tube and is grounded;
the grid-drain short circuit of the second PLDMOS tube is connected with the drain electrode of the fifth PLDMOS tube and the grid electrode of the third PLDMOS tube, and the source electrode of the second PLDMOS tube is connected with the source electrode of the third PLDMOS tube, the source electrode of the sixteenth PMOS tube and the drain electrode of the eighth NLDMOS tube and is connected with an input power supply voltage;
the grid electrode of the sixteenth PMOS tube is connected with the first bias voltage, and the drain electrode of the sixteenth PMOS tube is connected with the source electrode of the fourth PLDMOS tube;
the grid electrode of the fourth PLDMOS tube is connected with a second bias voltage, and the drain electrode of the fourth PLDMOS tube is connected with the grid electrode and the drain electrode of the seventh NLDMOS tube, the grid electrode of the fifth PLDMOS tube and the grid electrode of the sixth NLDMOS tube;
the source electrode of the seventh NLDMOS tube is connected with the source electrode of the seventeenth PMOS tube;
the grid electrode of the eighth NLDMOS tube is connected with the grid electrode of the third NLDMOS tube, the source electrode of the eighth NLDMOS tube is connected with the drain electrode of the third PLDMOS tube, the drain electrode of the sixth NLDMOS tube and one end of the fifth capacitor and serves as the output end of the second operational amplifier, and the other end of the fifth capacitor is grounded.
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