CN112000168A - Current source - Google Patents

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Publication number
CN112000168A
CN112000168A CN202010736978.XA CN202010736978A CN112000168A CN 112000168 A CN112000168 A CN 112000168A CN 202010736978 A CN202010736978 A CN 202010736978A CN 112000168 A CN112000168 A CN 112000168A
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China
Prior art keywords
transistor
pin
current
resistor
circuit
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CN202010736978.XA
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Chinese (zh)
Inventor
刘利书
冯宇翔
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Priority to CN202010736978.XA priority Critical patent/CN112000168A/en
Publication of CN112000168A publication Critical patent/CN112000168A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Abstract

The application discloses a current source includes: the band-gap reference circuit comprises a band-gap reference circuit, and a first-order compensation circuit, a second-order compensation circuit and an output circuit which are respectively connected with the band-gap reference circuit; the band-gap reference circuit is used for generating a first current; the first-order compensation circuit is used for generating a second current with a positive temperature coefficient and compensating the first current by utilizing the second current to obtain a third current; the output circuit is used for generating a fourth current equal to the third current; the second-order compensation circuit is used for generating a fifth current with a negative temperature coefficient; the output circuit is further used for merging the fourth current and the fifth current to obtain a stable current and outputting the stable current. The current source provided by the application has the advantages of higher output current precision and better stability.

Description

Current source
Technical Field
The application relates to the technical field of circuits, in particular to a current source.
Background
In the field of semiconductor devices and chips, it is generally necessary to design an external or internal current source with high precision and high temperature stability. The basic parameters for judging the quality of the power supply comprise: 1) stability of voltage: does not change with the applied voltage or load; 2) stability at temperature: does not change with the change of the external temperature; 3) the stability of the process. Among them, the challenge of temperature stability is greatest.
Currently, there are three variations of output current with temperature: the first is a positive temperature coefficient (PTAT) current source, the conventional design being based on a triode base-emitter Δ VBECurrent source as shown in fig. 1. The second is a negative temperature Coefficient (CTAT) current source, commonly referred to as VBEA current source. The third is a stable current source that does not vary with temperature. Conventional designs superimpose a PTAT current source and a CTAT current source.
In the current scheme, a non-linear term which changes with temperature exists in the CTAT current source, so that the linear compensation degrees of the CTAT current source and the PTAT current source in different temperature intervals are different, and complete compensation in a wide temperature range cannot be guaranteed, and therefore, the accuracy and the temperature stability of output current are not high.
Disclosure of Invention
It is an object of the present application to provide a current source. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a current source including a bandgap reference circuit, a first order compensation circuit, a second order compensation circuit, and an output circuit;
the first-order compensation circuit and the second-order compensation circuit are respectively connected with the band-gap reference circuit;
the output circuit is respectively connected with the band gap reference circuit and the second-order compensation circuit;
the band-gap reference circuit is used for generating a first current;
the first-order compensation circuit is used for generating a second current with a positive temperature coefficient and compensating the first current by using the second current to obtain a third current;
the output circuit is used for generating a fourth current equal to the third current;
the second-order compensation circuit is used for generating a fifth current with a negative temperature coefficient;
the output circuit is further used for merging the fourth current and the fifth current to obtain a stable current and outputting the stable current.
Further, the band-gap reference circuit comprises an operational amplifier, a current mirror, a first triode, a second triode, a first resistor, a second resistor and a third resistor, wherein the current mirror comprises a first transistor and a second transistor; a first pin of the first transistor and a first pin of the second transistor are respectively connected with a power supply voltage; the inverting input end of the operational amplifier, the emitter of the first triode and one end of the second resistor are respectively connected with the third pin of the first transistor; a second pin of the first transistor and a second pin of the second transistor are respectively connected with the output end of the operational amplifier; one end of the first resistor and one end of the third resistor are respectively connected with the positive phase input end of the operational amplifier; the other end of the first resistor is connected with an emitting electrode of the second triode; and the collector and the base of the second triode, the other end of the third resistor, the other end of the second resistor and the collector and the base of the first triode are respectively grounded.
Further, the first-order compensation circuit comprises a third transistor, a fourth resistor, a fifth resistor, a fourth transistor and a fifth transistor; one end of the fifth resistor is connected with the power supply voltage, and the other end of the fifth resistor is connected with a first pin of the third transistor; a third pin of the third transistor is connected with one end of the fourth resistor, a second pin of the third transistor is connected with an output end of the operational amplifier, and a third pin of the third transistor is connected with one end of the fourth resistor; the other end of the fourth resistor is grounded; a second pin of the fourth transistor and a second pin of the fifth transistor are both connected with a third pin of the third transistor; a third pin of the fourth transistor and a third pin of the fifth transistor are respectively connected with a third pin of the second transistor and a third pin of the first transistor; the first pin of the second transistor and the first pin of the third transistor are both grounded.
Further, the second-order compensation circuit comprises a sixth transistor, a seventh transistor, a sixth resistor and a seventh resistor; a first pin of the sixth transistor is connected with the power supply voltage; one end of the sixth resistor is connected with the power supply voltage, and the other end of the sixth resistor is respectively connected with the second pin of the sixth transistor and the first pin of the seventh transistor; a second pin of the seventh transistor is connected with the output end of the operational amplifier, and a third pin of the seventh transistor is connected with one end of the seventh resistor; the other end of the seventh resistor is grounded.
Further, the output circuit includes an eighth transistor, a first pin of the eighth transistor is connected to the power supply voltage, a second pin of the eighth transistor is connected to the output terminal of the operational amplifier, and a third pin of the eighth transistor is connected to a third pin of the sixth transistor.
Further, any transistor in the band gap reference circuit is a PMOS transistor or a PNP-type triode, a first pin of any transistor in the band gap reference circuit is a drain electrode of the PMOS transistor or a collector electrode of the PNP-type triode, a second pin of any transistor in the band gap reference circuit is a gate electrode of the PMOS transistor or a base electrode of the PNP-type triode, and a third pin of any transistor in the band gap reference circuit is a source electrode of the PMOS transistor or an emitter electrode of the PNP-type triode.
Further, a third transistor in the first-order compensation circuit is a PMOS transistor or a PNP triode, the fourth transistor and the fifth transistor are NMOS transistors or NPN triodes, a third pin of the third transistor is a drain of the PMOS transistor or a collector of the PNP triode, a second pin of the third transistor is a gate of the PMOS transistor or a base of the PNP triode, a second pin of the third transistor is a source of the PMOS transistor or an emitter of the PNP triode, a third pin of the fourth transistor and the fifth transistor is a drain of the NMOS transistor or a collector of the NPN triode, first pins of the fourth transistor and the fifth transistor are sources of the NMOS transistors or emitters of the NPN triode, and second pins of the fourth transistor and the fifth transistor are gates of the NMOS transistors or bases of the NPN triodes.
Furthermore, any transistor in the second-order compensation circuit is a PMOS transistor or a PNP-type triode, a third pin of any transistor in the second-order compensation circuit is a drain electrode of the PMOS transistor or a collector electrode of the PNP-type triode, a second pin of any transistor in the second-order compensation circuit is a gate electrode of the PMOS transistor or a base electrode of the PNP-type triode, and a first pin of any transistor in the second-order compensation circuit is a source electrode of the PMOS transistor or an emitter electrode of the PNP-type triode.
Further, any transistor in the band gap reference circuit is a PMOS transistor or a PNP-type triode, a first pin of any transistor in the band gap reference circuit is a drain electrode of the PMOS transistor or a collector electrode of the PNP-type triode, a second pin of any transistor in the band gap reference circuit is a gate electrode of the PMOS transistor or a base electrode of the PNP-type triode, and a third pin of any transistor in the band gap reference circuit is a source electrode of the PMOS transistor or an emitter electrode of the PNP-type triode.
Further, the first triode and the second triode are PNP tubes.
Further, a first triode and a second triode in the band gap reference circuit are replaced by NPN tubes, collectors and bases of the NPN tubes are in short circuit and connected with a high potential, and emitters of the NPN tubes are grounded and connected with a low potential.
Further, the temperature coefficient of the stabilization current is adjustable.
According to another aspect of the embodiments of the present application, there is provided an electrical apparatus including the current source described above.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the current source provided by the embodiment of the application utilizes the first current generated by the current compensation band-gap reference circuit with the positive temperature coefficient generated by the first-order compensation circuit to obtain the third current, the second-order compensation circuit generates the fourth current with the negative temperature coefficient, the output circuit generates the fourth current equal to the third current, and the fourth current and the fifth current are converged to obtain the stable current and output the stable current, so that the accuracy of the output current is higher, and the stability is better.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a prior art positive temperature coefficient current source;
FIG. 2 is a circuit diagram of a current source according to one embodiment of the present application;
fig. 3 is a circuit diagram of a current source according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As shown in fig. 2, a first embodiment of the present application provides a current source including a bandgap reference circuit 1, a first-order compensation circuit 2, a second-order compensation circuit 3, and an output circuit 4; the band-gap reference circuit 1 is respectively connected with a first-order compensation circuit 2, a second-order compensation circuit 3 and an output circuit 4;
the band-gap reference circuit 1 is used for generating a first current;
the first-order compensation circuit 2 is used for generating a second current with a positive temperature coefficient and compensating the first current by using the second current to obtain a third current;
the output circuit 4 is used for generating a fourth current equal to the third current;
the second-order compensation circuit 3 is used for generating a fifth current with a negative temperature coefficient;
the output circuit 4 is further configured to combine the fourth current and the fifth current to obtain a stable current and output the stable current.
The temperature coefficient of the stable current is adjustable, the flexibility is stronger, and the application range is wider.
The bandgap reference circuit 1 includes an operational amplifier OP, a second PMOS transistor MP2, a third PMOS transistor MP3, a first triode Q1, a second triode Q2, a first resistor R1, a second resistor R2, and a third resistor R3. The first transistor Q1 and the second transistor Q2 may be PNP transistors.
The first-order compensation circuit 2 comprises a first PMOS transistor MP1, a fourth resistor R4, a fifth resistor R5, a first NMOS transistor MN1 and a second NMOS transistor MN 2.
The second-order compensation circuit 3 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a sixth resistor R6, and a seventh resistor R7.
The output circuit 4 includes a fourth PMOS transistor MP 4.
In the first-order compensation circuit 2, the drain of the first PMOS transistor MP1 is grounded through the fourth resistor R4, and the source of the first PMOS transistor MP1 is connected to the power voltage V through the fifth resistor R5. One end of the fifth resistor R5 is connected to the power voltage V, and the other end is connected to the source of the first PMOS transistor MP 1. One end of the fourth resistor R4 is grounded, and the other end is connected to the drain of the first PMOS transistor MP 1.
The source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, and the source of the fourth PMOS transistor MP4 are respectively connected to a power voltage V. The inverting input terminal of the operational amplifier OP is connected to the drain of the second PMOS transistor MP2, and the non-inverting input terminal is connected to the drain of the third PMOS transistor MP 3. The second PMOS tube and the third PMOS tube form a current mirror.
The drain of the second NMOS transistor MN2, the emitter of the first triode Q1, and one end of the second resistor R2 are respectively connected to the drain of the second PMOS transistor MP 2. The drain of the first NMOS transistor MN1, one end of the third resistor R3, and one end of the first resistor R1 are respectively connected to the drain of the third PMOS transistor MP3, and the emitter of the second transistor Q2 is connected to the other end of the first resistor R1. The base and the collector of the first triode Q1 are respectively grounded, and the base and the collector of the second triode Q2 are respectively grounded. The source of the fifth PMOS transistor MP5 is connected to the supply voltage V. One end of the sixth resistor R6 is connected to the power voltage V, and the other end of the sixth resistor R6 is connected to the gate of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6, respectively. The drain of the sixth PMOS transistor MP6 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded. The gate of the sixth PMOS transistor MP6 is connected to the output terminal of the operational amplifier OP. The source and drain of the first NMOS transistor MN1 and the source and drain of the second NMOS transistor MN2 both output a positive temperature coefficient current In, i.e., a second current. The source and drain of the fifth PMOS transistor MP5 output a negative temperature coefficient current Ip, i.e., a fifth current.
The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 are respectively connected to the output terminal of the operational amplifier OP; the drain electrode of the second PMOS tube MP2 is connected with the inverting input end of the operational amplifier OP; the drain of the third PMOS transistor MP3 is connected to the non-inverting input of the operational amplifier OP. The source of the first PMOS transistor MP1 is connected to the power supply voltage V through a fifth resistor R5, and the drain is grounded through a fourth resistor R4. The gate of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP 6. The source of the sixth PMOS transistor MP6 is connected to the supply voltage V through a sixth resistor R6. The collector and base of the first transistor Q1 are both connected to ground GND, and the collector and base of the second transistor Q2 are both connected to ground GND. The emitter of the first triode Q1 is connected with the drain of the second PMOS tube. An emitter of the second triode Q2 is connected with one end of the first resistor R1, and the other end of the first resistor R1 is connected with a drain of the third PMOS transistor. The grid electrode of the first NMOS tube MN1 and the grid electrode of the second NMOS tube MN2 are respectively connected with the drain electrode of the first PMOS tube MP1, the source electrode of the first NMOS tube MN1 and the source electrode of the second NMOS tube MN2 are respectively grounded, and the drain electrode of the first NMOS tube MN1 is connected with the drain electrode of the third PMOS tube MP 3; the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the second PMOS transistor. The source electrode of the second PMOS transistor MP2, the source electrode of the third PMOS transistor MP3, the source electrode of the fourth PMOS transistor MP4, and the source electrode of the fifth PMOS transistor MP5 are respectively connected to a power supply voltage V. The first transistor Q1 and the second transistor Q2 are both PNP transistors.
The band-gap reference circuit 1 generates a first current; the first-order compensation circuit 2 generates a second current with a positive temperature coefficient, and compensates the first current by using the second current to obtain a third current; the output circuit 4 generates a fourth current equal to the third current; the second-order compensation circuit 3 generates a fifth current with a negative temperature coefficient; the output circuit 4 merges the fourth current and the fifth current to obtain a steady current and outputs the steady current.
The operational amplifier OP is used to stabilize the gate voltages of MP1, MP2, MP3, MP4, and MP 6.
Due to the virtual interruption of OP, the potentials of A and B are equal, VA＝VBFor Q1 pipe, VA＝VBE1；VA＝VB＝VBE1(ii) a The current through R1 is IR1＝(VB-VBE2)/R1＝(VBE1-VBE2)/R1＝ΔVBE/R1；ΔVBEIs a positive temperature coefficient, therefore IR1Is PTAT;
the current through R3 is IR3＝VB/R3＝VBE1/R3；VBE1Is a negative temperature coefficient, therefore IR3Is CTAT, but still has error on the linearity of temperature change;
I2＝IR1+IR3+In＝I3＝I1；Infor compensating IR3The non-linear term in (1) reduces the error. I isR1Is the current through the first resistor R1, IR3For the current through the third resistor R3, the first current is equal to IR1+IR3. I1, I2 and I3 are represented by the formula InThe current after the primary compensation is the current with better temperature stability, namely the third current. I3 is the fourth current. Ip is a fifth current.
The operational amplifier OP is used for providing stable grid voltage for the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the sixth PMOS tube MP 6;
operational amplifier OP virtual cutoff VA＝VBAnd finally generating positive temperature coefficient current and negative temperature coefficient current.
In is a positive temperature coefficient current and Ip is a negative temperature coefficient current, which are just opposite changes.
Factors controlling In and Ip: the ratio of R5 to R4 (R5/R4 is 9-14), and MP1 and MP2 are completely the same or are reduced in proportion.
The final output current Io is I3+ Ip, and Ip is compensated again, so that the error is further reduced, and the final output current Io is a stable current source. In certain embodiments, In ═ Ip.
The voltage division of the fourth resistor R4 and the fifth resistor R5 is adjusted to enable the first NMOS transistor MN1 and the second NMOS transistor MN2 to work In a subthreshold region, so that positive temperature coefficient current In is generated, and parameters are adjusted to enable the fifth PMOS transistor MP5 to also generate the same negative temperature coefficient current Ip; therefore, after the first-order compensation, the temperature of the current I1 is better, and finally, the second-order compensation is performed by the positive temperature coefficient current source of the fifth PMOS transistor MP5, so that the temperature stability of the output current Io is obviously improved.
The weak positive temperature coefficient current I3 and the negative temperature coefficient current Ip are summed to generate an output current Io, and the temperature coefficient of the output current Io is adjustable.
In some embodiments, any one of the PMOS transistors may be replaced by a PNP type triode, any one of the NMOS transistors may be replaced by an NPN type triode, in the connection relationship, a collector of the PNP type triode corresponds to a drain of the replacement PMOS transistor, a base of the PNP type triode corresponds to a gate of the replacement PMOS transistor, an emitter of the PNP type triode corresponds to a source of the replacement PMOS transistor, a collector of the NPN type triode corresponds to a drain of the replacement NMOS transistor, an emitter of the NPN type triode corresponds to a source of the replacement NMOS transistor, and a base of the NPN type triode corresponds to a gate of the replacement NMOS transistor. In some embodiments, one or more PMOS transistors may be replaced by a PNP transistor, and one or more NMOS transistors may be replaced by an NPN transistor, as required.
In some embodiments, the PNP transistor in the bandgap reference circuit may be replaced by an NPN transistor, the collector and the base of the NPN transistor are shorted to connect to a high potential, and the emitter of the NPN transistor is grounded to connect to a low potential. As shown in fig. 3, the first transistor Q1 and the second transistor Q2 are both NPN transistors, collectors and bases of Q1 and Q2 are both short-circuited and both connected to a high potential, and emitters E1 and E2 of the emitters E1 and Q2 of Q1 are both grounded and both connected to a low potential. The collector and base of Q1 are both connected to the inverting input of operational amplifier OP. The collector and base of Q2 are connected to a first resistor R1.
In another embodiment of the present application, an electrical appliance, such as a washing machine, is provided that includes the current source described above.
The current source provided by the embodiment of the application utilizes the first current generated by the current compensation band-gap reference circuit with the positive temperature coefficient generated by the first-order compensation circuit to obtain the third current, the second-order compensation circuit generates the fourth current with the negative temperature coefficient, the output circuit generates the fourth current equal to the third current, and the fourth current and the fifth current are converged to obtain the stable current and output the stable current, so that the accuracy of the output current is higher, and the stability is better.
It should be noted that:
in the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The above-mentioned embodiments only express the embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims (13)

1. A current source is characterized by comprising a band gap reference circuit, a first-order compensation circuit, a second-order compensation circuit and an output circuit;
the first-order compensation circuit and the second-order compensation circuit are respectively connected with the band-gap reference circuit;
the output circuit is respectively connected with the band gap reference circuit and the second-order compensation circuit;
the band-gap reference circuit is used for generating a first current;
the first-order compensation circuit is used for generating a second current with a positive temperature coefficient and compensating the first current by using the second current to obtain a third current;
the output circuit is used for generating a fourth current equal to the third current;
the second-order compensation circuit is used for generating a fifth current with a negative temperature coefficient;
the output circuit is further used for merging the fourth current and the fifth current to obtain a stable current and outputting the stable current.
2. The current source of claim 1, wherein the bandgap reference circuit comprises an operational amplifier, a current mirror, a first transistor, a second transistor, a first resistor, a second resistor, and a third resistor, the current mirror comprising a first transistor and a second transistor; a first pin of the first transistor and a first pin of the second transistor are respectively connected with a power supply voltage; the inverting input end of the operational amplifier, the emitter of the first triode and one end of the second resistor are respectively connected with the third pin of the first transistor; a second pin of the first transistor and a second pin of the second transistor are respectively connected with the output end of the operational amplifier; one end of the first resistor and one end of the third resistor are respectively connected with the positive phase input end of the operational amplifier; the other end of the first resistor is connected with an emitting electrode of the second triode; and the collector and the base of the second triode, the other end of the third resistor, the other end of the second resistor and the collector and the base of the first triode are respectively grounded.
3. The current source of claim 2, wherein the first-order compensation circuit comprises a third transistor, a fourth resistor, a fifth resistor, a fourth transistor, and a fifth transistor; one end of the fifth resistor is connected with the power supply voltage, and the other end of the fifth resistor is connected with a first pin of the third transistor; a third pin of the third transistor is connected with one end of the fourth resistor, a second pin of the third transistor is connected with an output end of the operational amplifier, and a third pin of the third transistor is connected with one end of the fourth resistor; the other end of the fourth resistor is grounded; a second pin of the fourth transistor and a second pin of the fifth transistor are both connected with a third pin of the third transistor; a third pin of the fourth transistor and a third pin of the fifth transistor are respectively connected with a third pin of the second transistor and a third pin of the first transistor; the first pin of the second transistor and the first pin of the third transistor are both grounded.
4. The current source of claim 3, wherein the second order compensation circuit comprises a sixth transistor, a seventh transistor, a sixth resistor, and a seventh resistor; a first pin of the sixth transistor is connected with the power supply voltage; one end of the sixth resistor is connected with the power supply voltage, and the other end of the sixth resistor is respectively connected with the second pin of the sixth transistor and the first pin of the seventh transistor; a second pin of the seventh transistor is connected with the output end of the operational amplifier, and a third pin of the seventh transistor is connected with one end of the seventh resistor; the other end of the seventh resistor is grounded.
5. The current source of claim 4, wherein the output circuit comprises an eighth transistor, a first pin of the eighth transistor is connected to the power supply voltage, a second pin of the eighth transistor is connected to the output of the operational amplifier, and a third pin of the eighth transistor is connected to the third pin of the sixth transistor.
6. The current source according to claim 2, wherein any transistor in the bandgap reference circuit is a PMOS transistor or a PNP triode, the first pin of any transistor in the bandgap reference circuit is a drain of the PMOS transistor or a collector of the PNP triode, the second pin of any transistor in the bandgap reference circuit is a gate of the PMOS transistor or a base of the PNP triode, and the third pin of any transistor in the bandgap reference circuit is a source of the PMOS transistor or an emitter of the PNP triode.
7. The current source of claim 3, wherein the third transistor of the first-order compensation circuit is a PMOS transistor or a PNP transistor, the fourth transistor and the fifth transistor are NMOS transistors or NPN type triodes, the third pin of the third transistor is the drain electrode of a PMOS transistor or the collector electrode of a PNP type triode, the second pin of the third transistor is the grid electrode of a PMOS tube or the base electrode of a PNP type triode, the second pin of the third transistor is the source electrode of a PMOS tube or the emitting electrode of a PNP type triode, the third pins of the fourth transistor and the fifth transistor are the drain of an NMOS tube or the collector of an NPN type triode, the first pins of the fourth transistor and the fifth transistor are the source electrodes of NMOS tubes or the emitting electrodes of NPN type triodes, and second pins of the fourth transistor and the fifth transistor are grids of an NMOS (N-channel metal oxide semiconductor) tube or bases of NPN (negative-positive-negative) type triodes.
8. The current source of claim 4, wherein any transistor in the second-order compensation circuit is a PMOS transistor or a PNP type triode, the third pin of any transistor in the second-order compensation circuit is a drain of the PMOS transistor or a collector of the PNP type triode, the second pin of any transistor in the second-order compensation circuit is a gate of the PMOS transistor or a base of the PNP type triode, and the first pin of any transistor in the second-order compensation circuit is a source of the PMOS transistor or an emitter of the PNP type triode.
9. The current source according to claim 5, wherein any transistor in the bandgap reference circuit is a PMOS transistor or a PNP type triode, a first pin of any transistor in the bandgap reference circuit is a drain of the PMOS transistor or a collector of the PNP type triode, a second pin of any transistor in the bandgap reference circuit is a gate of the PMOS transistor or a base of the PNP type triode, and a third pin of any transistor in the bandgap reference circuit is a source of the PMOS transistor or an emitter of the PNP type triode.
10. The current source of claim 5, wherein the first transistor and the second transistor are PNP transistors.
11. The current source according to claim 10, wherein the first transistor and the second transistor in the bandgap reference circuit are replaced by NPN transistors, collectors and bases of the NPN transistors are shorted to each other and connected to a high potential, and emitters of the NPN transistors are grounded and connected to a low potential.
12. The current source of claim 1, wherein a temperature coefficient of the stabilization current is adjustable.
13. An electrical device, characterized in that it comprises a current source according to any one of claims 1-12.
CN202010736978.XA 2020-07-28 2020-07-28 Current source Pending CN112000168A (en)

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Application publication date: 20201127