CN102981545A - Band gap reference voltage circuit with high-order curvature compensation - Google Patents
Band gap reference voltage circuit with high-order curvature compensation Download PDFInfo
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- CN102981545A CN102981545A CN2012105088880A CN201210508888A CN102981545A CN 102981545 A CN102981545 A CN 102981545A CN 2012105088880 A CN2012105088880 A CN 2012105088880A CN 201210508888 A CN201210508888 A CN 201210508888A CN 102981545 A CN102981545 A CN 102981545A
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Abstract
The invention discloses a band gap reference voltage source with high-order curvature compensation. The voltage source comprises a curvature compensation circuit, a reference voltage generating circuit, a startup circuit and an error amplifier (A1), wherein the curvature compensation circuit comprises a zeroth PMOS (P-channel Metal Oxide Semiconductor) tube (PM0), a first PMOS tube (PM1), a zeroth NMOS (N-channel Metal Oxide Semiconductor) tube (NM0), a first NMOS tube (NM1), a second NMOS tube (NM2), a zeroth triode (Q0) and a first triode (Q1); and the reference voltage generating circuit comprises a second triode (Q2) for generating positive temperature coefficient voltage, a third triode (Q3), a zeroth resistor (R0) for generating positive temperature coefficient current, a first resistor (R1) for generating a negative temperature coefficient, a second resistor (R2) and the like. According to the band gap reference voltage source, reference voltage with a lower temperature coefficient can be achieved in a very large temperature range.
Description
Technical field
The present invention relates to a kind of band-gap reference voltage circuit of source compensated by using high-order curvature, offset current is subthreshold current, this electric current has the high-order positive temperature coefficient (PTC), be used for and have a current summation of negative temperature coefficient, this negative temperature parameter current has the high-order negative temperature coefficient, the addition of the two can the cancellation electric current the high-order temperature coefficient, thereby obtain stable output voltage at output terminal.It is low that this circuit has a temperature coefficient, the advantage that power consumption is little.
Background technology
Reference voltage source is the very important ingredient of contemporary Analogous Integrated Electronic Circuits, and it provides reference voltage for serial voltage regulation circuit, A/D and D/A converter, also is voltage stabilizing power supply or the driving source of most of sensors.In addition, reference voltage source also can be used as scale merit and the Precision Current Component of standard cell, instrument gauge outfit.Its implementation has multiple, for example use electric resistance partial pressure, utilize the general-purpose diode two ends voltage, utilize the Zener diode two ends voltage, utilize temperature compensation Zener diode and bandgap voltage reference.Wherein bandgap voltage reference is most widely used, because its output voltage has good noise robustness, more because its output voltage is compared with the output voltage of other circuit, its temperature coefficient is less, so Bandgap Reference Voltage Generation Circuit is widely used.Lower temperature coefficient, lower power consumption, noise robustness is the target that the deviser pursues always better.
Present band-gap reference voltage circuit roughly can be divided into two kinds, and a kind of is to realize with resistance, metal-oxide-semiconductor and triode, and another kind is just to realize with metal-oxide-semiconductor and triode.The band-gap reference of MOS switch, electric capacity, metal-oxide-semiconductor and triode had also appearred using over the past two years.Wherein use the reference voltage circuit of resistance to occur in paper often, not only because it carries out second order or high-order temperature compensated easily, also very little because its temperature coefficient can be done, the change of voltage is very little in very large temperature range.The reference voltage circuit of this use resistance also has several structures according to varying in size of output voltage.The voltage of output can be greater than the band gap voltage 1.2V of silicon, also can less than supply voltage, perhaps the band gap voltage than 1.2V is also little greater than this voltage.
Use its principle of band-gap reference voltage circuit of resistance as follows: to utilize two triodes to be operated under the unequal current density, the difference of the base-emitter voltage of these two triodes just is directly proportional with absolute temperature so, when being the temperature rising, ideally, this difference increases with temperature linearity.And the base-emitter voltage of single triode has negative temperature coefficient, and when namely temperature rose, the base-emitter voltage of triode descended, but this variation non-linear hour.The voltage that bandgap voltage reference will have positive temperature coefficient (PTC) multiply by a coefficient, and the voltage that will have negative temperature coefficient also multiply by a suitable coefficient, then the two is added up, to realize the reference voltage of a zero-temperature coefficient.But the relation owing to positive temperature coefficient (PTC) voltage and temperature is linear, and the variation of the voltage of negative temperature coefficient and temperature is nonlinear, so this voltage is added up and only realized the compensation of single order temperature, the temperature coefficient of the reference voltage of acquisition is not fine.Based on this reason, circuit need to carry out high-order temperature compensated.In addition, along with integrated circuit is more and more higher to the requirement of power consumption, so that supply voltage is more and more lower, so the band-gap reference voltage circuit of low-power consumption has also obtained general attention and research under the low supply voltage.
Summary of the invention
Technical matters: the object of the present invention is to provide a reference voltage that in very large temperature range, has lower temperature coefficient.This circuit produces the high-order compensation that a small subthreshold current is realized temperature by a metal-oxide-semiconductor that works in sub-threshold region.Because the metal-oxide-semiconductor of this current generating circuit all is operated in weak inversion regime, so can not increase the power consumption of circuit.
Technical scheme: for solving the problems of the technologies described above, the invention discloses a kind of bandgap voltage reference of source compensated by using high-order curvature, it is characterized in that: this voltage source comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier;
The curvature compensation circuit comprises the 0th PMOS pipe, PMOS pipe, the 0th NMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 0th triode, the first triode;
Reference voltage generating circuit comprises the second triode, the 3rd for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance of positive temperature coefficient (PTC) electric current with for generation of the first resistance, second resistance of negative temperature coefficient, the 4th resistance for generation of output reference voltage, the 3rd PMOS pipe that is used for image current, the 4th PMOS pipe, the 5th PMOS pipe;
Start-up circuit comprises the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 3rd resistance and the 4th triode;
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe, PMOS pipe, the 2nd PMOS pipe links to each other, and the drain electrode of the 0th PMOS pipe links to each other with the drain electrode of the 0th NMOS pipe;
The drain electrode of the one PMOS pipe links to each other with drain electrode, the grid of a NMOS pipe respectively, and the grid of the 0th NMOS pipe, a NMOS pipe links to each other, and the grid of a NMOS pipe is connected to the grid of the 2nd NMOS pipe; The source electrode of the 0th NMOS pipe links to each other with the drain electrode of the 2nd NMOS pipe;
The base stage of the 0th triode links to each other with collector, and the base stage of the 0th triode is connected to the source electrode of a NMOS pipe, and the base stage of the first triode links to each other with collector and is connected to the source electrode of the 2nd NMOS pipe;
The grid of the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe links to each other, and the grid of the 3rd NMOS pipe is connected to the drain electrode of the 3rd NMOS pipe, and the simultaneously drain electrode of the 2nd PMOS pipe links to each other with the drain electrode of the 3rd NMOS pipe;
The grid of the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe links to each other, and the 5th gate pmos utmost point is received the output terminal of error amplifier;
The drain electrode of the 4th PMOS pipe is connected respectively to the drain terminal of zero resistance, the first resistance one end and the 4th NMOS pipe, and the other end of zero resistance links to each other with base stage, the collector of the second triode respectively;
The drain electrode of the 5th PMOS pipe is connected respectively to the drain electrode of the 5th NMOS pipe, base stage, collector, the base stage of the 4th triode, an end of the second resistance and the drain electrode of the 6th PMOS pipe of the 3rd triode Q3;
The drain electrode of the 7th PMOS pipe is connected respectively to the grid of the 6th PMOS pipe, an end of the 3rd resistance;
The 7th gate pmos utmost point is connected to the grid of the 8th PMOS pipe, the grid of the 8th PMOS pipe and the collector that drains and link to each other and be connected to the 4th triode;
The other end of the first resistance, the second resistance, the 3rd resistance, the 4th resistance all is connected to ground.
Beneficial effect: the characteristics of this band-gap reference circuit are for utilizing the metal-oxide-semiconductor that works in sub-threshold region, and the relevant circuit of structure, produce a subthreshold current that becomes higher-order function with temperature, be used for compensating the electric current of the negative temperature coefficient that transistor base and emitter voltage produce at resistance, thereby obtain optimum temperature coefficient.Simultaneously, because subthreshold current is very little, the overall power of circuit is not compared with compensating before after the compensation, can not increase, and therefore can not increase extra power consumption.
Description of drawings
Fig. 1 is the main body circuit diagram of source compensated by using high-order curvature band-gap reference circuit of the present invention.
Fig. 2 is the simulation result of the relation of source compensated by using high-order curvature band-gap reference circuit output voltage of the present invention and temperature.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Curvature compensation of the present invention adopts with temperature and becomes the subthreshold current of higher-order function relation to realize that this electric current increases along with the rising of temperature.By the resistance in the little reference circuit is replaced to metal-oxide-semiconductor, and make this metal-oxide-semiconductor be operated in weak inversion regime, the circuit that then originally produced the PTAT electric current can produce a subthreshold current.This subthreshold current is the higher-order function of temperature, increases with the rising of temperature.The core reference circuit partly produces a PTAT electric current and has the electric current of high-order negative temperature coefficient, and these three current summations can obtain an approximate temperature independent electric current, thereby obtain an output voltage with lower temperature coefficient.
Integrated circuit comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, four parts of error amplifier circuit.The curvature compensation circuit comprises PMOS pipe PM0, PM1, NMOS pipe NM0, NM1, NM2, triode Q0, the Q1 of the access of diode connected mode.Reference voltage generating circuit comprises triode Q2, the Q3 for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of resistance R 1, the R2 of negative temperature coefficient, for generation of the resistance R 4 of output reference voltage, be used for the PMOS pipe PM3-PM5 of image current.Start-up circuit comprises PMOS pipe PM6-PM8, resistance R 3 and triode Q4.Error amplifier circuit comprises PMOS pipe PM9-PM12, and input is to triode Q5, Q6, and NMOS manages NM6-NM9.
Figure 1 shows that the whole schematic diagram of curvature compensation circuit of the present invention, but to detailed description and explanation reference technique scheme and the embodiment part of this circuit.
Figure 2 shows that the simulation result of curvature compensation circuit output voltage of the present invention and temperature relation, as can be seen from the figure, the temperature coefficient of this reference voltage can reach 1.964ppm/ ° of C in-40 ℃ to 125 ℃ scopes.
Plant the bandgap voltage reference of source compensated by using high-order curvature, it carries out high-order temperature compensated on traditional reference voltage source basis that does not have curvature compensation.It is this characteristic of higher-order function of temperature that the metal-oxide-semiconductor subthreshold current has been adopted in compensation, compensates transistor base and launches the part that voltage across poles VBE rises and descends with temperature by this subthreshold current small voltage that increases with the temperature rising of resistance generation at reference voltage output end.NMOS pipe to two mirror image subthreshold currents in the curvature compensation circuit has designed trimming circuit, exist in the situation of fluctuation in manufacturing process like this, can control the size that is mirrored to benchmark main body circuit compensation electric current by the breadth length ratio of regulating NMOS, thus fine compensation output voltage variation with temperature.Simultaneously, in traditional Bandgap Reference Voltage Generation Circuit, the resistance that produces positive temperature coefficient (PTC) has also been designed trimming circuit.These two circuit can guarantee that output voltage has lower temperature coefficient, and namely in very large temperature range, the variation of output voltage is very little, is approximately constant voltage.Because the electric current that subthreshold current produces in the circuit is very little, therefore, the circuit extra power consumption of the compensated part of increase is very little.
The bandgap voltage reference of source compensated by using high-order curvature provided by the invention, this voltage source comprise curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier A1;
The curvature compensation circuit comprises that the 0th PMOS pipe PM0, a PMOS manage PM1, and the 0th NMOS pipe NM0, a NMOS pipe NM1, the 2nd NMOS manage NM2, the 0th triode Q0, the first triode Q1;
Reference voltage generating circuit comprises the second triode Q2, the 3rd Q3 for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of the first resistance R 1, second resistance R 2 of negative temperature coefficient, the 4th resistance R 4 for generation of output reference voltage, be used for the 3rd PMOS pipe PM3 of image current, the 4th PMOS pipe PM4, the 5th PMOS manage PM5;
Start-up circuit comprises that the 6th PMOS pipe PM6, the 7th PMOS pipe PM7, the 8th PMOS manage PM8, the 3rd resistance R 3 and the 4th triode Q4;
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe PM0, a PMOS pipe PM1, the 2nd PMOS pipe PM2 links to each other, and the drain electrode of the 0th PMOS pipe PM0 links to each other with the drain electrode of the 0th NMOS pipe NM0;
The drain electrode of the one PMOS pipe PM1 links to each other with drain electrode, the grid of NMOS pipe NM1 respectively, and the grid of the 0th NMOS pipe NM0, NMOS pipe NM1 links to each other, and the grid of NMOS pipe NM1 is connected to the grid of the 2nd NMOS pipe NM2; The source electrode of the 0th NMOS pipe NM0 links to each other with the drain electrode of the 2nd NMOS pipe NM2;
The base stage of the 0th triode Q0 links to each other with collector, and the base stage of the 0th triode Q0 is connected to the source electrode of NMOS pipe NM1, and the base stage of the first triode Q1 links to each other with collector and is connected to the source electrode that the 2nd NMOS manages NM2;
The grid of the 3rd NMOS pipe NM3, the 4th NMOS pipe NM4, the 5th NMOS pipe NM5 links to each other, and the grid of the 3rd NMOS pipe is connected to the drain electrode of the 3rd NMOS pipe NM3, and the simultaneously drain electrode of the 2nd PMOS pipe PM2 links to each other with the drain electrode of the 3rd NMOS pipe NM3;
The grid of the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, the 5th PMOS pipe PM5 links to each other, and the 5th gate pmos utmost point is received the output terminal of error amplifier A1;
The drain electrode of the 4th PMOS pipe PM4 is connected respectively to the drain terminal of zero resistance R0, the first resistance R 1 one ends and the 4th NMOS pipe NM4, and the other end of zero resistance R0 links to each other with base stage, the collector of the second triode Q2 respectively;
The drain electrode of the 5th PMOS pipe PM5 is connected respectively to the drain electrode of the 5th NMOS pipe NM5, base stage, collector, the base stage of the 4th triode Q4, an end of the second resistance R 2 and the drain electrode of the 6th PMOS pipe PM6 of the 3rd triode Q3;
The drain electrode of the 7th PMOS pipe PM7 is connected respectively to the grid of the 6th PMOS pipe PM6, an end of the 3rd resistance R 3;
The 7th gate pmos utmost point is connected to the grid of the 8th PMOS pipe PM8, the grid and the collector that drains and link to each other and be connected to the 4th triode Q4 of the 8th PMOS pipe PM8;
The other end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 all is connected to ground.
In the curvature compensation circuit, if being managed NM2, NMOS replaces to a resistance, this circuit is exactly a PTAT current generating circuit so, can export a PTAT electric current at the drain terminal of PMOS pipe PM2.NMOS pipe NM2 in this circuit is operated in weak inversion regime now, and the drain terminal of managing PM2 at PMOS obtains a subthreshold current, and this electric current is the high-order term function of temperature, increases along with the rising of temperature, and this rheometer is I
CThe voltage difference of triode Q2 and Q3 produces a PTAT electric current I by resistance R 0
0Because the effect of error amplifier so that the voltage at resistance R 1 and R2 two ends is equal, is triode Q3 base-emitter magnitude of voltage.This voltage produces the electric current I of a negative temperature coefficient at resistance R 1 and R2
1These three current summations namely are the electric currents that flows through PMOS pipe PM4, PM5.PMOS pipe PM3 is mirrored to output terminal by the mirror image effect with these three electric current sums, obtains output voltage in resistance R 4.The resistance of the resistance R 3 in the start-up circuit is chosen moderate, and resistance is too little can't to make later on the 6th PMOS pipe PM6 cut-off at circuit start, and the starting current of the too large then circuit of resistance is too little, possibly can't normally start.The bias voltage of error amplifier inside is linked to each other to provide with drain electrode by the grid of PMOS pipe PM8, i.e. Vbias in the diagram.The output that is input to of error amplifier has consisted of a stable closed-loop system.Consider the deviation that technique is made in the design, NMOS pipe NM4, the NM5 of mirror image subthreshold current designed trimming circuit.Simultaneously, the resistance R 0 that produces the PTAT electric current has also been designed trimming circuit.The ultimate principle of trimming circuit is for being operatively connected to resistance value in the circuit or the number of NMOS pipe with switch.Switch is realized with single NMOS pipe, so the resistance of place in circuit diminished when switching signal was input as high level, the resistance of access resistance becomes large during for low level.The current mirror effect of NMOS pipe and the increase of the resistance of resistance reduce similar, and the subthreshold current that is mirrored to output terminal when namely control signal is high level increases, and the subthreshold current that is mirrored to output terminal during for low level reduces.Switch controlling signal passed through first the two-stage phase inverter before receiving NMOS pipe switch, increase the driving force of signal.
By a metal-oxide-semiconductor that works in sub-threshold region, produce small, a temperature variant subthreshold current.This subthreshold current is the higher-order function of temperature, increases with the rising of temperature.The core reference circuit partly produces a PTAT electric current and has the electric current of high-order negative temperature coefficient, and these three current summations can obtain an approximate temperature independent electric current, thereby obtain an output voltage with lower temperature coefficient.If supply voltage is greater than the band gap voltage 1.2V of silicon, the reference voltage of output can be greater than the band gap voltage of silicon less than supply voltage.
Integrated circuit comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, four parts of error amplifier circuit.The curvature compensation circuit comprises PMOS pipe PM0, PM1, NMOS pipe NM0, NM1, NM2, NPN type triode Q0, the Q1 of the access of diode connected mode.Reference voltage generating circuit comprises triode Q2, the Q3 for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of resistance R 1, the R2 of negative temperature coefficient, for generation of the resistance R 4 of output reference voltage, be used for the PMOS pipe PM3-PM5 of image current.Start-up circuit comprises PMOS pipe PM6-PM8, resistance R 3 and triode Q4.Error amplifier circuit is used for guaranteeing that the voltage of positive-negative input end mouth equates, even the drain voltage of PMOS pipe PM4, PM5 equates.
The circuit of curvature compensation circuit and generation PTAT electric current is similar.In the curvature compensation circuit, if being managed NM2, NMOS replaces to a resistance, this circuit is exactly a PTAT current generating circuit so, can export a PTAT electric current at the drain terminal of PMOS pipe PM2.NMOS pipe NM2 in this circuit is operated in weak inversion regime now, and the drain terminal of managing PM2 at PMOS obtains a subthreshold current, and this electric current is the high-order term function of temperature, increases along with the rising of temperature, and this rheometer is I
CThe voltage difference of triode Q2 and Q3 produces a PTAT electric current I by resistance R 0
0Because the effect of error amplifier so that the voltage at resistance R 1 and R2 two ends is equal, is triode Q3 base-emitter magnitude of voltage.This voltage produces the electric current I of a negative temperature coefficient at resistance R 1 and R2
1These three current summations namely are the electric currents that flows through PMOS pipe PM4, PM5.PMOS pipe PM3 is mirrored to output terminal by the mirror image effect with these three electric current sums, obtains output voltage in resistance R 4.The resistance of the resistance R 3 in the start-up circuit is chosen moderate, and resistance is too little can't to make later on PMOS pipe PM6 cut-off at circuit start, and the starting current of the too large then circuit of resistance is too little, possibly can't normally start.The bias voltage of error amplifier inside is linked to each other to provide with drain electrode by the grid of PMOS pipe PM8, i.e. Vbias in the diagram.The output that is input to of error amplifier has consisted of a stable closed-loop system.
Consider the fluctuation of manufacturing process, designed respectively trimming circuit for the resistance R 0 of generation PTAT electric current and NMOS pipe NM4, the NM5 of mirror image subthreshold current.The trimming circuit ultimate principle is for being operatively connected to resistance value in the circuit or the number of NMOS pipe with switch.Switch is realized with single NMOS pipe, so the resistance of place in circuit diminished when switching signal was input as high level, the resistance of access resistance becomes large during for low level.The current mirror effect of NMOS pipe and the increase of the resistance of resistance reduce similar, and the subthreshold current that is mirrored to output terminal when namely control signal is high level increases, and the subthreshold current that is mirrored to output terminal during for low level reduces.Switch controlling signal passed through first the two-stage phase inverter before receiving NMOS pipe switch, increase the driving force of signal.
The above only is preferred embodiments of the present invention; protection scope of the present invention is not limited with above-mentioned embodiment; as long as the equivalence that those of ordinary skills do according to disclosed content is modified or changed, all should include in the protection domain of putting down in writing in claims.
Claims (1)
1. the bandgap voltage reference of a source compensated by using high-order curvature, it is characterized in that: this voltage source comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier (A1);
The curvature compensation circuit comprises that the 0th PMOS pipe (PM0), a PMOS manage (PM1), and the 0th NMOS pipe (NM0), NMOS pipe (NM1), the 2nd NMOS manage (NM2), the 0th triode (Q0), the first triode (Q1);
Reference voltage generating circuit comprises the second triode (Q2), the 3rd triode (Q3) for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance (R0) of positive temperature coefficient (PTC) electric current with for generation of the first resistance (R1), second resistance (R2) of negative temperature coefficient, the 4th resistance (R4) for generation of output reference voltage, be used for the 3rd PMOS pipe (PM3) of image current, the 4th PMOS pipe (PM4), the 5th PMOS manage (PM5);
Start-up circuit comprises that the 6th PMOS pipe (PM6), the 7th PMOS pipe (PM7), the 8th PMOS manage (PM8), the 3rd resistance (R3) and the 4th triode (Q4);
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe (PM0), PMOS pipe (PM1), the 2nd PMOS pipe (PM2) links to each other, and the drain electrode of the 0th PMOS pipe (PM0) links to each other with the drain electrode that the 0th NMOS manages (NM0);
The drain electrode of the one PMOS pipe (PM1) links to each other with drain electrode, the grid of NMOS pipe (NM1) respectively, the grid of the 0th NMOS pipe (NM0), NMOS pipe (NM1) links to each other, and the grid of NMOS pipe (NM1) is connected to the grid of the 2nd NMOS pipe (NM2); The source electrode of the 0th NMOS pipe (NM0) links to each other with the drain electrode that the 2nd NMOS manages (NM2);
The base stage of the 0th triode (Q0) links to each other with collector, and the base stage of the 0th triode (Q0) is connected to the source electrode of NMOS pipe (NM1), and the base stage of the first triode (Q1) links to each other with collector and is connected to the source electrode that the 2nd NMOS manages (NM2);
The grid of the 3rd NMOS pipe (NM3), the 4th NMOS pipe (NM4), the 5th NMOS pipe (NM5) links to each other, the grid of the 3rd NMOS pipe (NM3) is connected to the drain electrode of the 3rd NMOS pipe (NM3), and the simultaneously drain electrode of the 2nd PMOS pipe (PM2) links to each other with the drain electrode that the 3rd NMOS manages (NM3);
The grid of the 3rd PMOS pipe (PM3), the 4th PMOS pipe (PM4), the 5th PMOS pipe (PM5) links to each other, and the grid of the 5th PMOS pipe (PM5) is received the output terminal of error amplifier (A1);
The drain electrode of the 4th PMOS pipe (PM4) is connected respectively to the drain terminal of zero resistance (R0), the first resistance (R1) end and the 4th NMOS pipe (NM4), and the other end of zero resistance (R0) links to each other with base stage, the collector of the second triode (Q2) respectively;
The drain electrode of the 5th PMOS pipe (PM5) is connected respectively to the drain electrode of the 5th NMOS pipe (NM5), base stage, collector, the base stage of the 4th triode (Q4), an end of the second resistance (R2) and the drain electrode of the 6th PMOS pipe (PM6) of the 3rd triode (Q3);
The drain electrode of the 7th PMOS pipe (PM7) is connected respectively to the grid of the 6th PMOS pipe (PM6), an end of the 3rd resistance (R3);
The 7th PMOS pipe (PM7) grid is connected to the grid of the 8th PMOS pipe (PM8), the grid of the 8th PMOS pipe (PM8) and the collector that drains and link to each other and be connected to the 4th triode (Q4);
The other end of the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) all is connected to ground.
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| CN103294099A (en) * | 2013-05-17 | 2013-09-11 | 电子科技大学 | Second-order curvature temperature-compensation circuit for band-gap reference |
| CN108646845A (en) * | 2018-05-31 | 2018-10-12 | 东莞赛微微电子有限公司 | Reference voltage circuit |
| CN108762366A (en) * | 2018-06-02 | 2018-11-06 | 丹阳恒芯电子有限公司 | A kind of band-gap reference circuit |
| CN109343641A (en) * | 2018-11-23 | 2019-02-15 | 天津三源兴泰微电子技术有限公司 | A kind of high-precision current reference circuit |
| CN111596717A (en) * | 2020-06-03 | 2020-08-28 | 南京微盟电子有限公司 | Second-order compensation reference voltage source |
| CN112000168A (en) * | 2020-07-28 | 2020-11-27 | 广东美的白色家电技术创新中心有限公司 | Current source |
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| CN114995571A (en) * | 2022-06-16 | 2022-09-02 | 上海泰矽微电子有限公司 | Band-gap reference circuit with high-order curvature compensation |
| CN115016583A (en) * | 2022-06-16 | 2022-09-06 | 上海泰矽微电子有限公司 | Low-voltage band-gap reference circuit |
| CN115237195A (en) * | 2022-08-31 | 2022-10-25 | 中国电子科技集团公司第二十四研究所 | Voltage reference source |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434532A (en) * | 1993-06-16 | 1995-07-18 | Texas Instruments Incorporated | Low headroom manufacturable bandgap voltage reference |
| US20080048634A1 (en) * | 2004-10-08 | 2008-02-28 | Ivan Kotchkine | Reference Circuit |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN201435019Y (en) * | 2009-07-07 | 2010-03-31 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102323842A (en) * | 2011-05-13 | 2012-01-18 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
-
2012
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434532A (en) * | 1993-06-16 | 1995-07-18 | Texas Instruments Incorporated | Low headroom manufacturable bandgap voltage reference |
| US20080048634A1 (en) * | 2004-10-08 | 2008-02-28 | Ivan Kotchkine | Reference Circuit |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN201435019Y (en) * | 2009-07-07 | 2010-03-31 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102323842A (en) * | 2011-05-13 | 2012-01-18 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
Cited By (18)
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| CN103294099B (en) * | 2013-05-17 | 2015-04-15 | 电子科技大学 | Second-order curvature temperature-compensation circuit for band-gap reference |
| CN103294099A (en) * | 2013-05-17 | 2013-09-11 | 电子科技大学 | Second-order curvature temperature-compensation circuit for band-gap reference |
| CN108646845A (en) * | 2018-05-31 | 2018-10-12 | 东莞赛微微电子有限公司 | Reference voltage circuit |
| CN108762366A (en) * | 2018-06-02 | 2018-11-06 | 丹阳恒芯电子有限公司 | A kind of band-gap reference circuit |
| CN109343641A (en) * | 2018-11-23 | 2019-02-15 | 天津三源兴泰微电子技术有限公司 | A kind of high-precision current reference circuit |
| CN109343641B (en) * | 2018-11-23 | 2023-09-22 | 天津三源兴泰微电子技术有限公司 | High-precision current reference circuit |
| US10958227B2 (en) | 2019-05-07 | 2021-03-23 | Analog Devices, Inc. | Amplifier nonlinear offset drift correction |
| CN111596717B (en) * | 2020-06-03 | 2021-11-02 | 南京微盟电子有限公司 | Second-order compensation reference voltage source |
| CN111596717A (en) * | 2020-06-03 | 2020-08-28 | 南京微盟电子有限公司 | Second-order compensation reference voltage source |
| CN112000168A (en) * | 2020-07-28 | 2020-11-27 | 广东美的白色家电技术创新中心有限公司 | Current source |
| CN114489221A (en) * | 2022-01-11 | 2022-05-13 | 山东师范大学 | Band gap reference voltage source circuit and band gap reference voltage source |
| CN114489221B (en) * | 2022-01-11 | 2024-01-26 | 山东师范大学 | Band-gap reference voltage source circuit and band-gap reference voltage source |
| CN114995571A (en) * | 2022-06-16 | 2022-09-02 | 上海泰矽微电子有限公司 | Band-gap reference circuit with high-order curvature compensation |
| CN115016583A (en) * | 2022-06-16 | 2022-09-06 | 上海泰矽微电子有限公司 | Low-voltage band-gap reference circuit |
| CN114995571B (en) * | 2022-06-16 | 2024-03-08 | 上海泰矽微电子有限公司 | Band-gap reference circuit with high-order curvature compensation |
| CN115016583B (en) * | 2022-06-16 | 2024-03-08 | 上海泰矽微电子有限公司 | Low-voltage band-gap reference circuit |
| CN115237195A (en) * | 2022-08-31 | 2022-10-25 | 中国电子科技集团公司第二十四研究所 | Voltage reference source |
| CN115237195B (en) * | 2022-08-31 | 2023-08-22 | 中国电子科技集团公司第二十四研究所 | Voltage reference source |
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