CN102981545B - Band gap reference voltage circuit with high-order curvature compensation - Google Patents
Band gap reference voltage circuit with high-order curvature compensation Download PDFInfo
- Publication number
- CN102981545B CN102981545B CN201210508888.0A CN201210508888A CN102981545B CN 102981545 B CN102981545 B CN 102981545B CN 201210508888 A CN201210508888 A CN 201210508888A CN 102981545 B CN102981545 B CN 102981545B
- Authority
- CN
- China
- Prior art keywords
- pipe
- pmos pipe
- triode
- resistance
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The invention discloses a band gap reference voltage source with high-order curvature compensation. The voltage source comprises a curvature compensation circuit, a reference voltage generating circuit, a startup circuit and an error amplifier (A1), wherein the curvature compensation circuit comprises a zeroth PMOS (P-channel Metal Oxide Semiconductor) tube (PM0), a first PMOS tube (PM1), a zeroth NMOS (N-channel Metal Oxide Semiconductor) tube (NM0), a first NMOS tube (NM1), a second NMOS tube (NM2), a zeroth triode (Q0) and a first triode (Q1); and the reference voltage generating circuit comprises a second triode (Q2) for generating positive temperature coefficient voltage, a third triode (Q3), a zeroth resistor (R0) for generating positive temperature coefficient current, a first resistor (R1) for generating a negative temperature coefficient, a second resistor (R2) and the like. According to the band gap reference voltage source, reference voltage with a lower temperature coefficient can be achieved in a very large temperature range.
Description
Technical field
The present invention relates to a kind of band-gap reference voltage circuit of source compensated by using high-order curvature, offset current is subthreshold current, this electric current has high-order positive temperature coefficient (PTC), be used for and there is the current summation of negative temperature coefficient, this negative temperature parameter current has high-order negative temperature coefficient, the addition of the two can cancellation electric current high-order temperature coefficient, thereby obtain stable output voltage at output terminal.It is low that this circuit has temperature coefficient, the advantage that power consumption is little.
Background technology
Reference voltage source is the very important ingredient of contemporary Analogous Integrated Electronic Circuits, and it provides reference voltage for serial voltage regulation circuit, A/D and D/A converter, is also voltage stabilizing power supply or the driving source of most of sensors.In addition, reference voltage source also can be used as scale merit and the Precision Current Component of standard cell, instrument gauge outfit.Its implementation has multiple, for example use electric resistance partial pressure, utilize general-purpose diode two ends voltage, utilize Zener diode two ends voltage, utilize temperature compensation Zener diode and bandgap voltage reference.Wherein bandgap voltage reference is most widely used, because its output voltage has good noise robustness, more because compared with the output voltage of its output voltage and other circuit, its temperature coefficient is less, so Bandgap Reference Voltage Generation Circuit is widely used.Lower temperature coefficient, lower power consumption, noise robustness is the target that deviser pursues always better.
Present band-gap reference voltage circuit roughly can be divided into two kinds, and one is to realize with resistance, metal-oxide-semiconductor and triode, and another kind is just to realize with metal-oxide-semiconductor and triode.Also there is over the past two years using the band-gap reference of MOS switch, electric capacity, metal-oxide-semiconductor and triode.Wherein use the reference voltage circuit of resistance in paper, to occur often, not only, because it easily carries out second order or high-order temperature compensated, that also can do because of its temperature coefficient is very little, and in very large temperature range, the variation of voltage is very little.The reference voltage circuit of this use resistance also has several structures according to varying in size of output voltage.The voltage of output can be greater than the band gap voltage 1.2V of silicon, and also can be greater than this voltage and be less than supply voltage, or also less than the band gap voltage of 1.2V.
Use its principle of band-gap reference voltage circuit of resistance as follows: to utilize two triodes to be operated under unequal current density, the difference of the base-emitter voltage of these two triodes is just directly proportional to absolute temperature so, while being temperature rise, ideally, this difference increases with temperature linearity.And the base-emitter voltage of single triode has negative temperature coefficient, i.e., when temperature rise, the base-emitter voltage of triode declines, but this variation non-linear hour.The voltage with positive temperature coefficient (PTC) is multiplied by a coefficient by bandgap voltage reference, and the voltage with negative temperature coefficient is also multiplied by a suitable coefficient, then the two added up, to realize the reference voltage of a zero-temperature coefficient.But because the relation of positive temperature coefficient (PTC) voltage and temperature is linear, and the voltage of negative temperature coefficient and the variation of temperature are nonlinear, so this voltage is added up and only realized the compensation of single order temperature, the temperature coefficient of the reference voltage of acquisition is not fine.Based on this reason, circuit need to carry out high-order temperature compensated.In addition, along with integrated circuit is more and more higher to the requirement of power consumption, make supply voltage more and more lower, so the band-gap reference voltage circuit of low-power consumption has also obtained general attention and research under low supply voltage.
Summary of the invention
Technical matters: the object of the present invention is to provide a reference voltage in very large temperature range with lower temperature coefficient.This circuit is produced a small subthreshold current and is realized the high-order compensation of temperature by a metal-oxide-semiconductor that works in sub-threshold region.Because the metal-oxide-semiconductor of this current generating circuit is all operated in weak inversion regime, so can not increase the power consumption of circuit.
Technical scheme: for solving the problems of the technologies described above, the invention discloses a kind of bandgap voltage reference of source compensated by using high-order curvature, it is characterized in that: this voltage source comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier;
Curvature compensation circuit comprises the 0th PMOS pipe, a PMOS pipe, the 0th NMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 0th triode, the first triode;
Reference voltage generating circuit comprises for generation of the second triode of positive temperature coefficient (PTC) voltage, the 3rd, for generation of the zero resistance of positive temperature coefficient (PTC) electric current with for generation of the first resistance, second resistance of negative temperature coefficient, for generation of the 4th resistance of output reference voltage, for the 3rd PMOS pipe of image current, the 4th PMOS pipe, the 5th PMOS pipe;
Start-up circuit comprises the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 3rd resistance and the 4th triode;
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe, a PMOS pipe, the 2nd PMOS pipe is connected, and the drain electrode of the 0th PMOS pipe is connected with the drain electrode of the 0th NMOS pipe;
Drain electrode, the grid of the drain electrode of the one PMOS pipe the respectively with one NMOS pipe are connected, and the grid of the 0th NMOS pipe, a NMOS pipe is connected, and the grid of a NMOS pipe is connected to the grid of the 2nd NMOS pipe; The source electrode of the 0th NMOS pipe is connected with the drain electrode of the 2nd NMOS pipe;
The base stage of the 0th triode is connected with collector, and the base stage of the 0th triode is connected to the source electrode of a NMOS pipe, and the base stage of the first triode is connected with collector and is connected to the source electrode of the 2nd NMOS pipe;
The grid of the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe is connected, and the grid of the 3rd NMOS pipe is connected to the drain electrode of the 3rd NMOS pipe, and the drain electrode of the 2nd PMOS pipe is simultaneously connected with the drain electrode of the 3rd NMOS pipe;
The grid of the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe is connected, and the 5th gate pmos utmost point is received the output terminal of error amplifier;
The drain electrode of the 4th PMOS pipe is connected respectively to the drain terminal of zero resistance, first resistance one end and the 4th NMOS pipe, and base stage, the collector of the other end respectively with the second triode of zero resistance are connected;
The drain electrode of the 5th PMOS pipe is connected respectively to base stage, the collector of drain electrode, the 3rd triode Q3 of the 5th NMOS pipe, base stage, one end of the second resistance and the drain electrode of the 6th PMOS pipe of the 4th triode;
The drain electrode of the 7th PMOS pipe is connected respectively to the grid of the 6th PMOS pipe, one end of the 3rd resistance;
The 7th gate pmos utmost point is connected to the grid of the 8th PMOS pipe, the grid of the 8th PMOS pipe and the collector that drains and be connected and be connected to the 4th triode;
The other end of the first resistance, the second resistance, the 3rd resistance, the 4th resistance is all connected to ground.
Beneficial effect: the feature of this band-gap reference circuit is to utilize the metal-oxide-semiconductor that works in sub-threshold region, and build relevant circuit, produce a subthreshold current that becomes higher-order function with temperature, be used for compensating the electric current of the negative temperature coefficient that transistor base and emitter voltage produce on resistance, thereby obtain optimum temperature coefficient.Meanwhile, because subthreshold current is very little, compensate the overall power of rear circuit and before compensation, do not compare, can not increase, therefore can not increase extra power consumption.
Brief description of the drawings
Fig. 1 is the main body circuit diagram of source compensated by using high-order curvature band-gap reference circuit of the present invention.
Fig. 2 is the simulation result of the relation of source compensated by using high-order curvature band-gap reference circuit output voltage of the present invention and temperature.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Curvature compensation of the present invention adopts and becomes the subthreshold current of higher-order function relation to realize with temperature, and this electric current increases along with the rising of temperature.By the resistance in a little reference circuit is replaced to metal-oxide-semiconductor, and make this metal-oxide-semiconductor be operated in weak inversion regime, the circuit that originally produced PTAT electric current can produce a subthreshold current.This subthreshold current is the higher-order function of temperature, increases with the rising of temperature.Core reference circuit part produces a PTAT electric current and has the electric current of high-order negative temperature coefficient, and these three current summations can obtain an approximate temperature independent electric current, thereby obtain an output voltage with lower temperature coefficient.
Integrated circuit comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, four parts of error amplifier circuit.Curvature compensation circuit comprises PMOS pipe PM0, PM1, NMOS pipe NM0, NM1, NM2, triode Q0, the Q1 of the access of diode connected mode.Reference voltage generating circuit comprises triode Q2, the Q3 for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of resistance R 1, the R2 of negative temperature coefficient, for generation of the resistance R 4 of output reference voltage, for the PMOS pipe PM3-PM5 of image current.Start-up circuit comprises PMOS pipe PM6-PM8, resistance R 3 and triode Q4.Error amplifier circuit comprises PMOS pipe PM9-PM12, and input is to triode Q5, Q6, and NMOS manages NM6-NM9.
Figure 1 shows that curvature compensation circuit entirety schematic diagram of the present invention, can reference technique scheme and embodiment part to the detailed description of this circuit and explanation.
Figure 2 shows that the simulation result of curvature compensation circuit output voltage of the present invention and temperature relation, as can be seen from the figure, the temperature coefficient of this reference voltage can reach 1.964ppm/ ° of C within the scope of-40 DEG C to 125 DEG C.
The bandgap voltage reference of planting source compensated by using high-order curvature, it carries out high-order temperature compensated on traditional reference voltage source basis that there is no curvature compensation.To have adopted metal-oxide-semiconductor subthreshold current be this characteristic of higher-order function of temperature in compensation, produces one compensate transistor base and launch the part that voltage across poles VBE declines with temperature rise with the temperature small voltage increasing that raises by this subthreshold current on the resistance of reference voltage output end.NMOS pipe to two mirror image subthreshold currents in curvature compensation circuit has designed trimming circuit, like this in the situation that there is fluctuation in manufacturing process, can control the size that is mirrored to benchmark main body circuit compensation electric current by the breadth length ratio that regulates NMOS, thus fine compensation output voltage variation with temperature.Meanwhile, in traditional Bandgap Reference Voltage Generation Circuit, the resistance that produces positive temperature coefficient (PTC) has also been designed to trimming circuit.These two circuit can guarantee that output voltage has lower temperature coefficient, and, in very large temperature range, the variation of output voltage is very little, is approximately constant voltage.Because the electric current in subthreshold current generation circuit is very little, therefore, the circuit extra power consumption of the compensated part of increase is very little.
The bandgap voltage reference of source compensated by using high-order curvature provided by the invention, this voltage source comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier A1;
Curvature compensation circuit comprises the 0th PMOS pipe PM0, a PMOS pipe PM1, the 0th NMOS pipe NM0, a NMOS pipe NM1, the 2nd NMOS pipe NM2, the 0th triode Q0, the first triode Q1;
Reference voltage generating circuit comprises for generation of the second triode Q2 of positive temperature coefficient (PTC) voltage, the 3rd Q3, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of the first resistance R 1, second resistance R 2 of negative temperature coefficient, for generation of the 4th resistance R 4 of output reference voltage, for the 3rd PMOS pipe PM3 of image current, the 4th PMOS pipe PM4, the 5th PMOS pipe PM5;
Start-up circuit comprises the 6th PMOS pipe PM6, the 7th PMOS pipe PM7, the 8th PMOS pipe PM8, the 3rd resistance R 3 and the 4th triode Q4;
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe PM0, a PMOS pipe PM1, the 2nd PMOS pipe PM2 is connected, and the drain electrode of the 0th PMOS pipe PM0 is connected with the drain electrode of the 0th NMOS pipe NM0;
Drain electrode, the grid of drain electrode the respectively with one NMOS pipe NM1 of the one PMOS pipe PM1 are connected, and the grid of the 0th NMOS pipe NM0, a NMOS pipe NM1 is connected, and the grid of a NMOS pipe NM1 is connected to the grid of the 2nd NMOS pipe NM2; The source electrode of the 0th NMOS pipe NM0 is connected with the drain electrode of the 2nd NMOS pipe NM2;
The base stage of the 0th triode Q0 is connected with collector, and the base stage of the 0th triode Q0 is connected to the source electrode of a NMOS pipe NM1, and the base stage of the first triode Q1 is connected with collector and is connected to the 2nd NMOS and manages the source electrode of NM2;
The grid of the 3rd NMOS pipe NM3, the 4th NMOS pipe NM4, the 5th NMOS pipe NM5 is connected, and the grid of the 3rd NMOS pipe is connected to the drain electrode of the 3rd NMOS pipe NM3, and the drain electrode of the 2nd PMOS pipe PM2 is simultaneously connected with the drain electrode of the 3rd NMOS pipe NM3;
The grid of the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, the 5th PMOS pipe PM5 is connected, and the 5th gate pmos utmost point is received the output terminal of error amplifier A1;
The drain electrode of the 4th PMOS pipe PM4 is connected respectively to the drain terminal of zero resistance R0, first resistance R 1 one end and the 4th NMOS pipe NM4, and base stage, the collector of the other end respectively with the second triode Q2 of zero resistance R0 are connected;
The drain electrode of the 5th PMOS pipe PM5 is connected respectively to base stage, the collector of drain electrode, the 3rd triode Q3 of the 5th NMOS pipe NM5, base stage, one end of the second resistance R 2 and the drain electrode of the 6th PMOS pipe PM6 of the 4th triode Q4;
The drain electrode of the 7th PMOS pipe PM7 is connected respectively to the grid of the 6th PMOS pipe PM6, one end of the 3rd resistance R 3;
The 7th gate pmos utmost point is connected to the grid of the 8th PMOS pipe PM8, the grid and the collector that drains and be connected and be connected to the 4th triode Q4 of the 8th PMOS pipe PM8;
The other end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 is all connected to ground.
In curvature compensation circuit, if being managed to NM2, NMOS replaces to a resistance, this circuit is exactly a PTAT current generating circuit so, can export a PTAT electric current at the drain terminal of PMOS pipe PM2.NMOS pipe NM2 in this circuit is operated in weak inversion regime now, obtains a subthreshold current at the drain terminal of PMOS pipe PM2, and this electric current is the high-order term function of temperature, increases along with the rising of temperature, and this rheometer is done to I
c.The voltage difference of triode Q2 and Q3, by resistance R 0, produces a PTAT electric current I
0.Due to the effect of error amplifier, the voltage at resistance R 1 and R2 two ends is equated, be triode Q3 base-emitter magnitude of voltage.This voltage produces the electric current I of a negative temperature coefficient on resistance R 1 and R2
1.These three current summations are the electric currents that flows through PMOS pipe PM4, PM5.PMOS pipe PM3, by mirror image effect, is mirrored to output terminal by these three electric current sums, in resistance R 4, obtains output voltage.The resistance of the resistance R 3 in start-up circuit is chosen moderate, and resistance is too little cannot make the 6th PMOS pipe PM6 cut-off after circuit start, and the starting current of the too large circuit of resistance is too little, possibly cannot normally start.The bias voltage of error amplifier inside is connected to provide with drain electrode by the grid of PMOS pipe PM8, i.e. Vbias in diagram.The output that is input to of error amplifier has formed a stable closed-loop system.In design, consider the deviation that technique is manufactured, NMOS pipe NM4, the NM5 of mirror image subthreshold current have been designed to trimming circuit.Meanwhile, the resistance R 0 that produces PTAT electric current has also been designed to trimming circuit.The ultimate principle of trimming circuit is to be operatively connected to resistance value in circuit or the number of NMOS pipe with switch.Switch is realized with single NMOS pipe, so the resistance of place in circuit diminishes when switching signal is input as high level, the resistance that accesses resistance during for low level becomes large.The current mirror effect of NMOS pipe and the increase of the resistance of resistance reduce similar, and the subthreshold current that is mirrored to output terminal when control signal is high level increases, and the subthreshold current that is mirrored to output terminal during for low level reduces.Switch controlling signal first passed through two-stage phase inverter before receiving NMOS pipe switch, increased the driving force of signal.
By a metal-oxide-semiconductor that works in sub-threshold region, produce small, a temperature variant subthreshold current.This subthreshold current is the higher-order function of temperature, increases with the rising of temperature.Core reference circuit part produces a PTAT electric current and has the electric current of high-order negative temperature coefficient, and these three current summations can obtain an approximate temperature independent electric current, thereby obtain an output voltage with lower temperature coefficient.If supply voltage is greater than the band gap voltage 1.2V of silicon, the reference voltage of output can be greater than the band gap voltage of silicon and be less than supply voltage.
Integrated circuit comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, four parts of error amplifier circuit.Curvature compensation circuit comprises PMOS pipe PM0, PM1, NMOS pipe NM0, NM1, NM2, NPN type triode Q0, the Q1 of the access of diode connected mode.Reference voltage generating circuit comprises triode Q2, the Q3 for generation of positive temperature coefficient (PTC) voltage, for generation of the zero resistance R0 of positive temperature coefficient (PTC) electric current with for generation of resistance R 1, the R2 of negative temperature coefficient, for generation of the resistance R 4 of output reference voltage, for the PMOS pipe PM3-PM5 of image current.Start-up circuit comprises PMOS pipe PM6-PM8, resistance R 3 and triode Q4.Error amplifier circuit is used for ensureing that the voltage of positive-negative input end mouth equates, even if the drain voltage of PMOS pipe PM4, PM5 equates.
The circuit of curvature compensation circuit and generation PTAT electric current is similar.In curvature compensation circuit, if being managed to NM2, NMOS replaces to a resistance, this circuit is exactly a PTAT current generating circuit so, can export a PTAT electric current at the drain terminal of PMOS pipe PM2.NMOS pipe NM2 in this circuit is operated in weak inversion regime now, obtains a subthreshold current at the drain terminal of PMOS pipe PM2, and this electric current is the high-order term function of temperature, increases along with the rising of temperature, and this rheometer is done to I
c.The voltage difference of triode Q2 and Q3, by resistance R 0, produces a PTAT electric current I
0.Due to the effect of error amplifier, the voltage at resistance R 1 and R2 two ends is equated, be triode Q3 base-emitter magnitude of voltage.This voltage produces the electric current I of a negative temperature coefficient on resistance R 1 and R2
1.These three current summations are the electric currents that flows through PMOS pipe PM4, PM5.PMOS pipe PM3, by mirror image effect, is mirrored to output terminal by these three electric current sums, in resistance R 4, obtains output voltage.The resistance of the resistance R 3 in start-up circuit is chosen moderate, and resistance is too little cannot make PMOS pipe PM6 cut-off after circuit start, and the starting current of the too large circuit of resistance is too little, possibly cannot normally start.The bias voltage of error amplifier inside is connected to provide with drain electrode by the grid of PMOS pipe PM8, i.e. Vbias in diagram.The output that is input to of error amplifier has formed a stable closed-loop system.
Consider the fluctuation of manufacturing process, designed respectively trimming circuit for the resistance R 0 of generation PTAT electric current and NMOS pipe NM4, the NM5 of mirror image subthreshold current.Trimming circuit ultimate principle is to be operatively connected to resistance value in circuit or the number of NMOS pipe with switch.Switch is realized with single NMOS pipe, so the resistance of place in circuit diminishes when switching signal is input as high level, the resistance that accesses resistance during for low level becomes large.The current mirror effect of NMOS pipe and the increase of the resistance of resistance reduce similar, and the subthreshold current that is mirrored to output terminal when control signal is high level increases, and the subthreshold current that is mirrored to output terminal during for low level reduces.Switch controlling signal first passed through two-stage phase inverter before receiving NMOS pipe switch, increased the driving force of signal.
The foregoing is only preferred embodiments of the present invention; protection scope of the present invention is not limited with above-mentioned embodiment; in every case the equivalence that those of ordinary skill in the art do according to disclosed content is modified or is changed, and all should include in the protection domain of recording in claims.
Claims (1)
1. a bandgap voltage reference for source compensated by using high-order curvature, is characterized in that: this voltage source comprises curvature compensation circuit, reference voltage generating circuit, start-up circuit, error amplifier (A1);
Curvature compensation circuit comprises the 0th PMOS pipe (PM0), a PMOS pipe (PM1), the 0th NMOS pipe (NM0), a NMOS pipe (NM1), the 2nd NMOS pipe (NM2), the 0th triode (Q0), the first triode (Q1);
Reference voltage generating circuit comprises for generation of second triode (Q2) of positive temperature coefficient (PTC) voltage, the 3rd triode (Q3), for generation of the zero resistance (R0) of positive temperature coefficient (PTC) electric current with for generation of the first resistance (R1), second resistance (R2) of negative temperature coefficient, for generation of the 4th resistance (R4) of output reference voltage, for the 3rd PMOS pipe (PM3) of image current, the 4th PMOS pipe (PM4), the 5th PMOS pipe (PM5);
Start-up circuit comprises the 6th PMOS pipe (PM6), the 7th PMOS pipe (PM7), the 8th PMOS pipe (PM8), the 3rd resistance (R3) and the 4th triode (Q4);
Circuit connecting relation is as follows:
The grid of the 0th PMOS pipe (PM0), a PMOS pipe (PM1), the 2nd PMOS pipe (PM2) is connected and is connected to the drain electrode of the 0th NMOS pipe (NM0), and the drain electrode that the 0th PMOS manages (PM0) is connected with the drain electrode that the 0th NMOS manages (NM0);
Drain electrode, the grid of drain electrode the respectively with one NMOS pipe (NM1) of the one PMOS pipe (PM1) are connected, the grid of the 0th NMOS pipe (NM0), a NMOS pipe (NM1) is connected, and the grid of a NMOS pipe (NM1) is connected to the grid of the 2nd NMOS pipe (NM2); The source electrode of the 0th NMOS pipe (NM0) is connected with the drain electrode that the 2nd NMOS manages (NM2);
The base stage of the 0th triode (Q0) is connected with collector, the base stage of the 0th triode (Q0) is connected to the source electrode of a NMOS pipe (NM1), and the base stage of the first triode (Q1) is connected with collector and is connected to the 2nd NMOS and manages the source electrode of (NM2);
The grid of the 3rd NMOS pipe (NM3), the 4th NMOS pipe (NM4), the 5th NMOS pipe (NM5) is connected, source ground, the grid of the 3rd NMOS pipe (NM3) is connected to the drain electrode of the 3rd NMOS pipe (NM3), and the drain electrode of the 2nd PMOS pipe (PM2) is simultaneously connected with the drain electrode that the 3rd NMOS manages (NM3);
The grid of the 3rd PMOS pipe (PM3), the 4th PMOS pipe (PM4), the 5th PMOS pipe (PM5) is connected, and the grid of the 5th PMOS pipe (PM5) is received the output terminal of error amplifier (A1);
The drain electrode of the 4th PMOS pipe (PM4) is connected respectively to the drain terminal of positive input terminal, the first resistance (R1) one end and the 4th NMOS pipe (NM4) of zero resistance (R0), error amplifier (A1), and base stage, the collector of the other end respectively with the second triode (Q2) of zero resistance (R0) are connected;
The drain electrode of the 5th PMOS pipe (PM5) is connected respectively to base stage, the collector of negative input end, the 3rd triode (Q3) of drain electrode, the error amplifier (A1) of the 5th NMOS pipe (NM5), base stage, one end of the second resistance (R2) and the drain electrode of the 6th PMOS pipe (PM6) of the 4th triode (Q4);
The drain electrode of the 7th PMOS pipe (PM7) is connected respectively to the grid of the 6th PMOS pipe (PM6), one end of the 3rd resistance (R3);
The 7th PMOS pipe (PM7) grid is connected to the grid of the 8th PMOS pipe (PM8), the grid of the 8th PMOS pipe (PM8) and the collector that drains and be connected and be connected to the 4th triode (Q4); The grounded emitter of the first triode (Q1), the second triode (Q2), the 3rd triode (Q3), the 4th triode (Q4);
The source electrode of the 0th PMOS pipe (PM0), a PMOS pipe (PM1), the 2nd PMOS pipe (PM2), the 3rd PMOS pipe (PM3), the 4th PMOS pipe (PM4), the 5th PMOS pipe (PM5), the 6th PMOS pipe (PM6), the 7th PMOS pipe (PM7), the 8th PMOS pipe (PM8) connects respectively power supply;
The other end of the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) is all connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210508888.0A CN102981545B (en) | 2012-12-03 | 2012-12-03 | Band gap reference voltage circuit with high-order curvature compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210508888.0A CN102981545B (en) | 2012-12-03 | 2012-12-03 | Band gap reference voltage circuit with high-order curvature compensation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102981545A CN102981545A (en) | 2013-03-20 |
| CN102981545B true CN102981545B (en) | 2014-08-13 |
Family
ID=47855692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210508888.0A Expired - Fee Related CN102981545B (en) | 2012-12-03 | 2012-12-03 | Band gap reference voltage circuit with high-order curvature compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102981545B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103294099B (en) * | 2013-05-17 | 2015-04-15 | 电子科技大学 | Second-order curvature temperature-compensation circuit for band-gap reference |
| CN108646845A (en) * | 2018-05-31 | 2018-10-12 | 东莞赛微微电子有限公司 | Reference voltage circuit |
| CN108762366A (en) * | 2018-06-02 | 2018-11-06 | 丹阳恒芯电子有限公司 | A kind of band-gap reference circuit |
| CN109343641B (en) * | 2018-11-23 | 2023-09-22 | 天津三源兴泰微电子技术有限公司 | High-precision current reference circuit |
| US10958227B2 (en) | 2019-05-07 | 2021-03-23 | Analog Devices, Inc. | Amplifier nonlinear offset drift correction |
| CN111596717B (en) * | 2020-06-03 | 2021-11-02 | 南京微盟电子有限公司 | Second-order compensation reference voltage source |
| CN112000168A (en) * | 2020-07-28 | 2020-11-27 | 广东美的白色家电技术创新中心有限公司 | Current source |
| CN114489221B (en) * | 2022-01-11 | 2024-01-26 | 山东师范大学 | Band-gap reference voltage source circuit and band-gap reference voltage source |
| CN114995571B (en) * | 2022-06-16 | 2024-03-08 | 上海泰矽微电子有限公司 | Band-gap reference circuit with high-order curvature compensation |
| CN115016583B (en) * | 2022-06-16 | 2024-03-08 | 上海泰矽微电子有限公司 | Low-voltage band-gap reference circuit |
| CN115237195B (en) * | 2022-08-31 | 2023-08-22 | 中国电子科技集团公司第二十四研究所 | Voltage reference source |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434532A (en) * | 1993-06-16 | 1995-07-18 | Texas Instruments Incorporated | Low headroom manufacturable bandgap voltage reference |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN201435019Y (en) * | 2009-07-07 | 2010-03-31 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102323842A (en) * | 2011-05-13 | 2012-01-18 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008516328A (en) * | 2004-10-08 | 2008-05-15 | フリースケール セミコンダクター インコーポレイテッド | Reference circuit |
-
2012
- 2012-12-03 CN CN201210508888.0A patent/CN102981545B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434532A (en) * | 1993-06-16 | 1995-07-18 | Texas Instruments Incorporated | Low headroom manufacturable bandgap voltage reference |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN201435019Y (en) * | 2009-07-07 | 2010-03-31 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102323842A (en) * | 2011-05-13 | 2012-01-18 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102981545A (en) | 2013-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102981545B (en) | Band gap reference voltage circuit with high-order curvature compensation | |
| CN106959723B (en) | A kind of bandgap voltage reference of wide input range high PSRR | |
| CN102393786B (en) | High-order temperature compensation CMOS band-gap reference voltage source | |
| CN103488227B (en) | Band-gap reference voltage circuit | |
| CN102622032B (en) | Low temperature coefficient bandgap voltage reference circuit | |
| CN112859996B (en) | Low-voltage high-precision band-gap reference circuit | |
| CN107168442B (en) | Band gap reference voltage source circuit | |
| CN108762367B (en) | Mixed adjustment type temperature compensation band gap reference circuit | |
| CN104007777A (en) | Current source generator | |
| CN102253684A (en) | Bandgap reference circuit employing current subtraction technology | |
| CN102354251A (en) | Band-gap reference voltage circuit | |
| CN104977971A (en) | Free-operational amplifier low power-consumption band-gap reference circuit | |
| CN101149628B (en) | Reference voltage source circuit | |
| CN207352505U (en) | A kind of non-resistance formula high-precision low-power consumption a reference source | |
| CN104977963A (en) | Free-operational amplifier low power-consumption high power supply rejection ratio band-gap reference circuit | |
| CN106155171B (en) | The bandgap voltage reference circuit of linear temperature coefficient compensation | |
| CN101598953A (en) | A kind ofly export adjustable high power supply rejection ratio (PSRR) reference source circuit | |
| CN104216458A (en) | Temperature curvature complementary reference source | |
| CN102809979B (en) | Third-order compensation band-gap reference voltage source | |
| CN104914915A (en) | High-precision negative-voltage sectional compensation band gap reference voltage source circuit | |
| CN202171758U (en) | Band-gap reference voltage circuit | |
| CN208873065U (en) | A kind of band-gap reference circuit | |
| CN104820460B (en) | A kind of band gap reference voltage source circuit | |
| CN203643886U (en) | Band-gap reference source circuit and band-gap reference source | |
| CN106571810B (en) | Temperature coefficient compensation device and method for atomic frequency standard equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170215 Address after: 99 No. 214135 Jiangsu province Wuxi city Wuxi District Linghu Avenue Patentee after: Southeast University Wuxi branch Address before: 99 No. 214135 Jiangsu New District of Wuxi City Linghu Avenue Patentee before: Southeast University |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140813 Termination date: 20201203 |