CN114024516A - Constant offset voltage rail-to-rail operational amplifier - Google Patents

Constant offset voltage rail-to-rail operational amplifier Download PDF

Info

Publication number
CN114024516A
CN114024516A CN202111301686.4A CN202111301686A CN114024516A CN 114024516 A CN114024516 A CN 114024516A CN 202111301686 A CN202111301686 A CN 202111301686A CN 114024516 A CN114024516 A CN 114024516A
Authority
CN
China
Prior art keywords
electrode
tube
nmos
pmos
nmos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111301686.4A
Other languages
Chinese (zh)
Inventor
李海波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangyin Xinji Technology Co ltd
Original Assignee
Jiangyin Xinji Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangyin Xinji Technology Co ltd filed Critical Jiangyin Xinji Technology Co ltd
Priority to CN202111301686.4A priority Critical patent/CN114024516A/en
Publication of CN114024516A publication Critical patent/CN114024516A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a constant offset voltage rail-to-rail operational amplifier, which comprises: a first input stage operational amplifier unit electrically connected between the power supply voltage VDD and the reference potential and including multiple MOS transistors and a first resistor R1First resistance R1For generating a first offset voltage; the first bias enhancement control unit and the first control tube are used for generating a first control signal and a second control signal; a second input stage operational amplification unit electrically connected between the power supply voltage VDD and the reference potential and the first input stage operational amplification unit, comprising a plurality of MOS transistors and a second resistor R2A second resistance R2For generating a second offset voltage; the second bias enhancement control unit and the second control tube are used for generating a third control signal and a fourth control signal. The rail-to-rail operational amplifier can work in a full swing voltage range and has the advantages ofConstant offset voltage.

Description

Constant offset voltage rail-to-rail operational amplifier
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a constant offset voltage rail-to-rail operational amplifier.
Background
In the design process of an analog integrated circuit, operations of adding a fixed voltage or subtracting a fixed voltage to some signals are often required, and sometimes the swing of the signals to be processed is large, which is a challenge for circuit design, and the implementation of the circuit is often complicated.
The input and output voltage swings of the rail-to-rail operational amplifier are very close to or almost equal to the voltage value of a power supply, and a high signal-to-noise ratio can be kept to a certain degree, but in the manufacturing process of an integrated circuit, offset voltage is introduced due to the influence of factors such as process and device mismatch, the precision of digital-to-analog or analog-to-digital conversion is directly influenced, and the signal-to-noise ratio is reduced.
Therefore, in view of the above technical problems, it is desirable to provide a constant offset voltage rail-to-rail operational amplifier.
Disclosure of Invention
Accordingly, the present invention is directed to a constant offset voltage rail-to-rail operational amplifier.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a constant offset voltage rail-to-rail operational amplifier, the rail-to-rail operational amplifier comprising:
a first input stage operational amplifier unit electrically connected between the power supply voltage VDD and the reference potential and including multiple MOS transistors and a first resistor R1First resistance R1For generating a first offset voltage;
a first bias enhancement control unit and a first control tube for generating a first control signal and a second control signal, wherein the first control signal is used for controlling the first control tube to maintain a current flowing through the first resistor R1First current I ofR1The second control signal is used for stabilizing the first current I when the first current I cannot be stabilizedR1The first input stage operational amplification unit is turned off;
a second input stage operational amplification unit electrically connected between the power supply voltage VDD and the reference potential and the first input stage operational amplification unit, comprising a plurality of MOS transistors and a second resistor R2A second resistance R2For generating a second offset voltage;
a second bias enhancement control unit and a second control tube for generating a third control signal and a fourth control signal, wherein the third control signal is used for controlling the second control tube to maintain a current flowing through a second resistor R2Second current I ofR2The fourth control signal is used for stabilizing the second current IR2Time-off second input stageAn operational amplification unit.
In an embodiment, the first input stage operational amplification unit is an NMOS input stage operational amplification unit, and includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a first resistor R1And a first current source I1, wherein:
the source electrode of the third PMOS tube MP3 is connected with a power supply voltage VDD, the grid electrode is connected with the drain electrode, the source electrode of the fourth PMOS tube MP4 is connected with the power supply voltage VDD, and the grid electrode is connected with the drain electrode;
the grid of the first NMOS transistor MN1 is connected with the first signal input end, the drain is connected with the drain of the third PMOS transistor MP3, the grid of the second NMOS transistor MN2 is connected with the second signal input end, the drain is connected with the drain of the fourth PMOS transistor MP4, and the source is connected with the first resistor R1Are connected with each other;
the first terminal of the first current source I1, the source of the first NMOS transistor MN1 and the first resistor R1The second end of the first resistor is connected with a reference potential;
the source electrode of the first PMOS tube MP1 is connected with a power supply voltage VDD, the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of a twelfth NMOS tube MN12, the grid electrode of the twelfth NMOS tube MN12 is connected with the drain electrode of a twelfth NMOS tube MN12, and the source electrode of the twelfth NMOS tube MN12 is connected with a reference potential;
the source electrode of the sixth PMOS tube MP6 is connected with a power supply voltage VDD, the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth NMOS tube MN5, the grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN5, and the source electrode of the fifth NMOS tube MN5 is connected with a reference potential;
the drain electrode of a fourteenth NMOS tube MN14 is connected with the second input-stage operational amplification unit, the source electrode is connected with the drain electrode of a thirteenth NMOS tube MN13, the grid electrode of the thirteenth NMOS tube MN13 is connected with the grid electrode of a twelfth NMOS tube NM12, and the source electrode is connected with a reference potential;
the drain electrode of the third NMOS tube MN3 is connected with the signal output end, the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourteenth NMOS tube MN14, the source electrode of the third NMOS tube MN4 is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the fourth NMOS tube MN4 is connected with the grid electrode of the fifth NMOS tube MN5, and the source electrode of the fourth NMOS tube MN4 is connected with the reference potential;
the second input stage operational amplification unit is a PMOS input stage operational amplification unit and comprises a seventh PMOS tube MP7, an eighth PMOS tube MP8, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a sixteenth NMOS tube MN16, a seventeenth NMOS tube MN17, an eighteenth NMOS tube MN18, a nineteenth NMOS tube MN19, a twenty-first NMOS tube MN21, a twenty-second NMOS tube MN22 and a second resistor R2And a fourth current source I4, wherein:
the source electrode of the seventeenth NMOS transistor MN17 is connected with the reference potential, the grid electrode is connected with the drain electrode, the source electrode of the eighteenth NMOS transistor MN18 is connected with the reference potential, and the grid electrode is connected with the drain electrode;
the gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, the drain is connected to the drain of the seventeenth NMOS transistor MN17, the gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, the drain is connected to the drain of the eighteenth NMOS transistor MN18, and the source is connected to the second resistor R2Are connected with each other;
a first terminal of the second current source I2 is connected to the reference potential, and a second terminal thereof is connected to the source of the seventh PMOS transistor MP7 and the second resistor R2Are connected with each other;
a source electrode of the tenth PMOS transistor MP10 is connected to a power supply voltage VDD, a gate electrode is connected to a drain electrode, a drain electrode is connected to a drain electrode of the twenty-first NMOS transistor MN21, a drain electrode of the twenty-first NMOS transistor MN21 is connected to a drain electrode of the fourteenth NMOS transistor MN14, a source electrode is connected to a drain electrode of the sixteenth NMOS transistor MN16, a gate electrode of the sixteenth NMOS transistor MN16 is connected to a gate electrode of the seventeenth NMOS transistor MN17, and a source electrode is connected to a reference potential;
the source electrode of the eleventh PMOS tube MP11 is connected with a power supply voltage VDD, the grid electrode of the eleventh PMOS tube MP11 is connected with the grid electrode of the tenth PMOS tube MP10, the drain electrode of the eleventh PMOS tube MP 3578 is connected with the drain electrode of the twenty-second NMOS tube MN22, the source electrode of the twenty-second NMOS tube MN22 is connected with the drain electrode of the nineteenth NMOS tube MN19, the grid electrode of the nineteenth NMOS tube MN19 is connected with the grid electrode of the eighteenth NMOS tube MN18, the source electrode of the nineteenth NMOS tube MN19 is connected with a reference potential, and the drain electrode of the eleventh PMOS tube MP11 and the drain electrode of the twenty-second NMOS tube MN22 are connected with a signal output end.
In one embodiment, the first resistor R1And a second resistor R2Are equal in resistance, i.e. R1＝R2The first offset voltage is VOS1＝R1*IR1The second offset voltage is VOS2＝R2*IR2(ii) a The current of the first current source I1 is I1＝I0The current of the fourth current source I4 is I4＝I0。
In one embodiment, the first control transistor is an eighth NMOS transistor MN8, a gate of the eighth NMOS transistor MN8 is connected to the first bias boosting control unit, a source is connected to the reference potential, and a drain is connected to the first end of the first current source I1; the second control tube is a sixteenth PMOS tube MP16, the grid electrode of the sixteenth PMOS tube MP16 is connected with the second bias enhancement control unit, the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the second resistor R2Are connected to each other.
In an embodiment, the first bias boosting control unit includes a first sampling unit and a first control unit, the first sampling unit includes a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a second current source I2, the first control unit includes a ninth NMOS transistor MN9, a third current source I3, and a first schmitt trigger, wherein:
the source electrode of the second PMOS tube MP2 is connected with a power supply voltage VDD, the grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the eleventh NMOS tube MN11, the grid electrode of the eleventh NMOS tube MN11 is connected with the drain electrode, and the source electrode of the eleventh NMOS tube MN11 is connected with a reference potential;
a first end of a second current source I2 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a tenth NMOS tube MN10, a grid electrode of a tenth NMOS tube MN10 is connected with a grid electrode of an eleventh NMOS tube MN11, and the drain electrode is connected with a reference potential;
the source electrode of the fifth PMOS tube MP5 is connected with a power supply voltage VDD, the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the sixth NMOS tube MN6, the grid electrode of the sixth NMOS tube MN6 is connected with the drain electrode, and the source electrode of the sixth NMOS tube MN6 is connected with a reference potential;
the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the sixth NMOS transistor MN6, the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN8, the grid electrode of the ninth NMOS transistor MN9 and the drain electrode of the tenth NMOS transistor MN10, and the source electrode of the seventh NMOS transistor MN7 is connected with the reference potential;
a first end of a third current source I3 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a ninth NMOS transistor MN9, a grid electrode of the ninth NMOS transistor MN9 is connected with a grid electrode of an eighth NMOS transistor MN8, and a source electrode is connected with a reference potential;
the input end of the first Schmitt trigger is connected with the drain electrode of a ninth NMOS transistor MN9, and the output end of the first Schmitt trigger is connected with the grid electrode of a fourteenth NMOS transistor MN14 and the grid electrode of a third NMOS transistor MN 3;
the second bias enhancement control unit comprises a second sampling unit and a second control unit, the second sampling unit comprises a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20 and a fifth current source I5, the second control unit comprises a fifteenth PMOS transistor MP15, a sixth current source I6 and a second schmitt trigger, wherein:
the source electrode of the ninth PMOS transistor MP9 is connected with the power supply voltage VDD, the grid electrode is connected with the drain electrode, the drain electrode is connected with the drain electrode of a fifteenth NMOS transistor MN15, the grid electrode of the fifteenth NMOS transistor MN15 is connected with the grid electrode of a seventeenth NMOS transistor MN17, and the source electrode is connected with the reference potential;
the source of the twelfth PMOS transistor MP12 is connected with the power supply voltage VDD, the gate is connected with the gate of the ninth PMOS transistor MP9, the drain is connected with the first end of the fifth current source I5, the source of the thirteenth PMOS transistor MP13 is connected with the power supply voltage VDD, the drain is connected with the first end of the fifth current source I5, and the second end of the fifth current source I5 is connected with the reference potential;
a source electrode of the fourteenth PMOS tube MP14 is connected with a power supply voltage VDD, a grid electrode of the fourteenth PMOS tube MP 3578 is connected with a grid electrode of the thirteenth PMOS tube MP13, a drain electrode of the fourteenth PMOS tube MP14 is connected with a grid electrode of the fourteenth PMOS tube MP14 and a drain electrode of the twentieth NMOS tube MN20, a grid electrode of the twentieth NMOS tube MN20 is connected with a grid electrode of the eighteenth NMOS tube MN18, and a source electrode of the twentieth NMOS tube MN20 is connected with a reference potential;
the source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate thereof is connected to the gate of the sixteenth PMOS transistor MP16, the drain thereof is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential;
the input end of the second schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first end of the sixth current source I6, and the output end is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN 22.
In one embodiment, the current of the second current source I2 is I2＝I0The current of the third current source I3 is I3＝I0/2, the current of the fifth current source I5 is I5＝I0The current of the sixth current source I6 is I6＝I0/2。
In an embodiment, the first sampling unit is configured to collect the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2, and the current I of the second current source I22Comparing to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN 8;
the second sampling unit is used for collecting the current flowing through the seventh PMOS tube MP7 and the eighth PMOS tube MP8 and the current I of the fifth current source I55And comparing to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP 16.
In one embodiment, the first control unit is configured to turn off the first input stage operational amplifier unit when the current of the eighth NMOS transistor MN8 is greater than the first current threshold;
the second control unit is used for turning off the first input stage operational amplification unit when the current of the sixteenth PMOS transistor MP16 is smaller than the second current threshold.
In one embodiment, in the rail-to-rail operational amplifier, the signal output terminal is connected to the second signal input terminal, and the first signal input terminal receives a linearly increasing or decreasing voltage signal.
In one embodiment, the rail-to-rail operational amplifier:
at the time t1-t2 and the time t4-t5, the NMOS input stage operational amplification unit and the PMOS input stage operational amplification unit are both in a working state;
at the time t2-t4, the NMOS input stage operational amplification unit is in a working state, and the PMOS input stage operational amplification unit is in a non-working state;
at time t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is equal to INN-INP and is kept constant, INP and INN are the voltage signal at the first signal input terminal and the voltage signal at the second signal input terminal, respectively;
wherein:
at time t1, the voltage signal at the first signal input end is equal to VGSN, where VGSN is Vthn + Vdson, Vthn is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN2, and Vdson is the overdrive voltage;
at time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, VGSP is Vthp + Vdson, Vthp is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and Vdson is the overdrive voltage;
at time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power voltage VDD;
at time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP;
at time t5, the voltage signal at the first signal input terminal is equal to VGSN.
The invention has the following beneficial effects:
the rail-to-rail operational amplifier can work in a full swing voltage range and has constant offset voltage in the working process.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a constant offset voltage rail-to-rail operational amplifier of the present invention;
FIG. 2 is a circuit diagram of a constant offset voltage rail-to-rail operational amplifier according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating operation of a constant offset voltage rail-to-rail operational amplifier according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention discloses a constant offset voltage rail-to-rail operational amplifier, which includes:
a first input stage operational amplifier unit electrically connected between the power supply voltage VDD and the reference potential and including multiple MOS transistors and a first resistor R1First resistance R1For generating a first offset voltage;
a first bias enhancement control unit and a first control tube for generating a first control signal and a second control signal, wherein the first control signal is used for controlling the first control tube to maintain a current flowing through the first resistor R1First current I ofR1The second control signal is used for stabilizing the first current I when the first current I cannot be stabilizedR1The first input stage operational amplification unit is turned off;
a second input stage operational amplification unit electrically connected between the power supply voltage VDD and the reference potential and the first input stage operational amplification unit, comprising a plurality of MOS transistors and a second resistor R2A second resistance R2For generating a second offset voltage;
a second bias enhancement control unit and a second control tube for generating a third control signal and a fourth control signal, wherein the third control signal is used for controlling the second control tube to maintain a current flowing through a second resistor R2Second current I ofR2The fourth control signal is used for stabilizing the second current IR2The second input stage operational amplification unit is turned off.
Preferably, the reference potential in the present invention is explained by taking the ground potential as an example.
The first input stage operational amplification unit is an NMOS input stage operational amplification unit and comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6 and a first resistor R1And a first current source I1, wherein:
the source electrode of the third PMOS tube MP3 is connected with a power supply voltage VDD, the grid electrode is connected with the drain electrode, the source electrode of the fourth PMOS tube MP4 is connected with the power supply voltage VDD, and the grid electrode is connected with the drain electrode;
the grid of the first NMOS transistor MN1 is connected with the first signal input end, the drain is connected with the drain of the third PMOS transistor MP3, the grid of the second NMOS transistor MN2 is connected with the second signal input end, the drain is connected with the drain of the fourth PMOS transistor MP4, and the source is connected with the first resistor R1Are connected with each other;
the first terminal of the first current source I1, the source of the first NMOS transistor MN1 and the first resistor R1The second end of the first resistor is connected with a reference potential;
the source electrode of the first PMOS tube MP1 is connected with a power supply voltage VDD, the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of a twelfth NMOS tube MN12, the grid electrode of the twelfth NMOS tube MN12 is connected with the drain electrode of a twelfth NMOS tube MN12, and the source electrode of the twelfth NMOS tube MN12 is connected with a reference potential;
the source electrode of the sixth PMOS tube MP6 is connected with a power supply voltage VDD, the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth NMOS tube MN5, the grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN5, and the source electrode of the fifth NMOS tube MN5 is connected with a reference potential;
the drain electrode of a fourteenth NMOS tube MN14 is connected with the second input-stage operational amplification unit, the source electrode is connected with the drain electrode of a thirteenth NMOS tube MN13, the grid electrode of the thirteenth NMOS tube MN13 is connected with the grid electrode of a twelfth NMOS tube NM12, and the source electrode is connected with a reference potential;
the drain electrode of the third NMOS tube MN3 is connected with the signal output end, the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourteenth NMOS tube MN14, the source electrode of the third NMOS tube MN4 is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the fourth NMOS tube MN4 is connected with the grid electrode of the fifth NMOS tube MN5, and the source electrode of the fourth NMOS tube MN4 is connected with the reference potential;
in the NMOS input stage operational amplification unit, the current of the first current source I1 is I1＝I0When the input signal voltage is higher than one VGS, the operational amplifier starts to work. A first resistor R1For generating a first offset voltage VOS1And flows through the first resistor R1Current I ofR1Correlation, VOS1＝R1*IR1。
The second input stage operational amplification unit is a PMOS input stage operational amplification unit and comprises a seventh PMOS tube MP7, an eighth PMOS tube MP8, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a sixteenth NMOS tube MN16, a seventeenth NMOS tube MN17, an eighteenth NMOS tube MN18, a nineteenth NMOS tube MN19, a twenty-first NMOS tube MN21, a twenty-second NMOS tube MN22 and a second resistor R2And a fourth current source I4, wherein:
the source electrode of the seventeenth NMOS transistor MN17 is connected with the reference potential, the grid electrode is connected with the drain electrode, the source electrode of the eighteenth NMOS transistor MN18 is connected with the reference potential, and the grid electrode is connected with the drain electrode;
the gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, the drain is connected to the drain of the seventeenth NMOS transistor MN17, the gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, the drain is connected to the drain of the eighteenth NMOS transistor MN18, and the source is connected to the second resistor R2Are connected with each other;
a first terminal of the second current source I2 is connected to the reference potential, and a second terminal thereof is connected to the source of the seventh PMOS transistor MP7 and the second resistor R2Are connected with each other;
a source electrode of the tenth PMOS transistor MP10 is connected to a power supply voltage VDD, a gate electrode is connected to a drain electrode, a drain electrode is connected to a drain electrode of the twenty-first NMOS transistor MN21, a drain electrode of the twenty-first NMOS transistor MN21 is connected to a drain electrode of the fourteenth NMOS transistor MN14, a source electrode is connected to a drain electrode of the sixteenth NMOS transistor MN16, a gate electrode of the sixteenth NMOS transistor MN16 is connected to a gate electrode of the seventeenth NMOS transistor MN17, and a source electrode is connected to a reference potential;
the source electrode of the eleventh PMOS tube MP11 is connected with a power supply voltage VDD, the grid electrode of the eleventh PMOS tube MP11 is connected with the grid electrode of the tenth PMOS tube MP10, the drain electrode of the eleventh PMOS tube MP 3578 is connected with the drain electrode of the twenty-second NMOS tube MN22, the source electrode of the twenty-second NMOS tube MN22 is connected with the drain electrode of the nineteenth NMOS tube MN19, the grid electrode of the nineteenth NMOS tube MN19 is connected with the grid electrode of the eighteenth NMOS tube MN18, the source electrode of the nineteenth NMOS tube MN19 is connected with a reference potential, and the drain electrode of the eleventh PMOS tube MP11 and the drain electrode of the twenty-second NMOS tube MN22 are connected with a signal output end.
In the PMOS input stage operational amplification unit, the current of the fourth current source I4 is I4＝I0When the difference between the input signal voltage and the power supply voltage VDD is lower than one VGS, the operational amplifier starts to work. A second resistor R2For generating a second offset voltage VOS2And flows through the second resistor R2Current I ofR2Correlation, VOS2＝R2*IR2And a first resistance R1And a second resistor R2Are equal in resistance, i.e. R1＝R2。
Specifically, the first control transistor in the present invention is an eighth NMOS transistor MN8, a gate of the eighth NMOS transistor MN8 is connected to the first bias boosting control unit, a source is connected to the reference potential, and a drain is connected to the first end of the first current source I1; the second control tube is a sixteenth PMOS tube MP16, the gate of the sixteenth PMOS tube MP16 is connected with the second bias enhancement control unit, the source is connected with the power supply voltage VDD, and the drain is connected with the second resistor R2Are connected to each other.
The first bias enhancement control unit samples the currents flowing through the MN1 and the MN2, compares the sampled currents with a reference current, generates a first control signal to control the MN8 so that the sum of the currents of the MN1 and the MN2 is equal to the reference current, and maintains R1The current is stable, and the purpose of keeping constant offset voltage is achieved. The unit also generates a second control signal EN _ NEA when the input signal voltage is too low to stabilize R1When the current is positive, the control signal EN _ NEA closes the NMOS input stage operational amplification unit;
the second bias boosting control unit samples the current flowing through the MP7 and the MP8, compares the sampled current with the reference current, generates a third control signal to control the MP16 so that the sum of the currents of the MP7 and the MP8 is equal to the reference current, thereby maintaining R2The current of the power supply is stable and constantThe purpose of fixing offset voltage. The unit also generates a fourth control signal EN _ PEA when the input signal voltage is too large to stabilize R2The control signal EN _ PEA turns off the PMOS input stage operational amplifier unit.
Referring to fig. 2, in an embodiment of the invention, the first input stage operational amplification unit and the second input stage operational amplification unit have the same circuit structure, and are not repeated herein.
In this embodiment, the first bias boosting control unit includes a first sampling unit and a first control unit, the first sampling unit includes a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a second current source I2, the first control unit includes a ninth NMOS transistor MN9, a third current source I3, and a first schmitt trigger, where:
the source electrode of the second PMOS tube MP2 is connected with a power supply voltage VDD, the grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the eleventh NMOS tube MN11, the grid electrode of the eleventh NMOS tube MN11 is connected with the drain electrode, and the source electrode of the eleventh NMOS tube MN11 is connected with a reference potential;
a first end of a second current source I2 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a tenth NMOS tube MN10, a grid electrode of a tenth NMOS tube MN10 is connected with a grid electrode of an eleventh NMOS tube MN11, and the drain electrode is connected with a reference potential;
the source electrode of the fifth PMOS tube MP5 is connected with a power supply voltage VDD, the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the sixth NMOS tube MN6, the grid electrode of the sixth NMOS tube MN6 is connected with the drain electrode, and the source electrode of the sixth NMOS tube MN6 is connected with a reference potential;
the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the sixth NMOS transistor MN6, the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN8, the grid electrode of the ninth NMOS transistor MN9 and the drain electrode of the tenth NMOS transistor MN10, and the source electrode of the seventh NMOS transistor MN7 is connected with the reference potential;
a first end of a third current source I3 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a ninth NMOS transistor MN9, a grid electrode of the ninth NMOS transistor MN9 is connected with a grid electrode of an eighth NMOS transistor MN8, and a source electrode is connected with a reference potential;
the input end of the first schmitt trigger is connected with the drain electrode of the ninth NMOS transistor MN9, and the output end of the first schmitt trigger is connected with the gate electrode of the fourteenth NMOS transistor MN14 and the gate electrode of the third NMOS transistor MN 3.
The second bias enhancement control unit comprises a second sampling unit and a second control unit, the second sampling unit comprises a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20 and a fifth current source I5, the second control unit comprises a fifteenth PMOS transistor MP15, a sixth current source I6 and a second schmitt trigger, wherein:
the source electrode of the ninth PMOS transistor MP9 is connected with the power supply voltage VDD, the grid electrode is connected with the drain electrode, the drain electrode is connected with the drain electrode of a fifteenth NMOS transistor MN15, the grid electrode of the fifteenth NMOS transistor MN15 is connected with the grid electrode of a seventeenth NMOS transistor MN17, and the source electrode is connected with the reference potential;
the source of the twelfth PMOS transistor MP12 is connected with the power supply voltage VDD, the gate is connected with the gate of the ninth PMOS transistor MP9, the drain is connected with the first end of the fifth current source I5, the source of the thirteenth PMOS transistor MP13 is connected with the power supply voltage VDD, the drain is connected with the first end of the fifth current source I5, and the second end of the fifth current source I5 is connected with the reference potential;
a source electrode of the fourteenth PMOS tube MP14 is connected with a power supply voltage VDD, a grid electrode of the fourteenth PMOS tube MP 3578 is connected with a grid electrode of the thirteenth PMOS tube MP13, a drain electrode of the fourteenth PMOS tube MP14 is connected with a grid electrode of the fourteenth PMOS tube MP14 and a drain electrode of the twentieth NMOS tube MN20, a grid electrode of the twentieth NMOS tube MN20 is connected with a grid electrode of the eighteenth NMOS tube MN18, and a source electrode of the twentieth NMOS tube MN20 is connected with a reference potential;
the source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate thereof is connected to the gate of the sixteenth PMOS transistor MP16, the drain thereof is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential;
the input end of the second schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first end of the sixth current source I6, and the output end is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN 22.
Wherein, the current of the second current source I2 is I2＝I0The current of the third current source I3 is I3＝I0/2, the current of the fifth current source I5 is I5＝I0The current of the sixth current source I6 is I6＝I0/2。
The first sampling unit is used for collecting the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2 and the current I of the second current source I22Comparing to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN 8;
the first control unit is used for turning off the first input stage operational amplification unit when the current of the eighth NMOS transistor MN8 is greater than the first current threshold. The ninth NMOS transistor MN9 mirrors the current of the eighth NMOS transistor MN8, when the current of MN8 is greater than a certain value, it indicates that the input signal is very low, and if the signal is further decreased, the NMOS input stage operational amplifier unit will not work normally, so at this time, the control circuit will generate the control signal EN _ NEA, turn off the NMOS input stage operational amplifier unit, and at this time, the PMOS input stage operational amplifier unit generates the output voltage.
The second sampling unit is used for collecting the current flowing through the seventh PMOS tube MP7 and the eighth PMOS tube MP8 and the current I of the fifth current source I55Comparing to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP 16;
the second control unit is used for turning off the first input stage operational amplification unit when the current of the sixteenth PMOS transistor MP16 is smaller than the second current threshold. The fifteenth PMOS transistor MP15 mirrors the current of the sixteenth PMOS transistor MP16, when the current of MP16 is smaller than a certain value, it means that the input signal is very high, if the signal is further increased, the PMOS input stage operational amplification unit will not work normally, so at this time, the control circuit will generate the control signal EN _ PEA, turn off the PMOS input stage operational amplification unit, and at this time, the NMOS input stage operational amplification unit with constant offset voltage will generate the output voltage.
When the signal output terminal OUT of the rail-to-rail operational amplifier is connected to the second signal input terminal INN, the first signal input terminal INP receives a linearly increasing or decreasing voltage signal.
Referring to fig. 3, taking an example that the INP voltage is linearly increased (0 to VDD-VGSP) and then linearly decreased (VDD-VGSP to 0), the operation of the corresponding amplifier is as follows:
at the time t1-t2 and the time t4-t5, the NMOS input stage operational amplification unit and the PMOS input stage operational amplification unit are both in a working state;
at the time t2-t4, the NMOS input stage operational amplification unit is in a working state, and the PMOS input stage operational amplification unit is in a non-working state;
at time t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is equal to INN-INP and is kept constant, where INP and INN are the voltage signal at the first signal input terminal and the voltage signal at the second signal input terminal, respectively.
Wherein:
at time t1, the voltage signal at the first signal input terminal is equal to VGSN, where VGSN is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN 2;
at time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, where VGSP is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP 8;
at time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power voltage VDD;
at time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP;
at time t5, the voltage signal at the first signal input terminal is equal to VGSN.
When INP voltage is less than VGSN, MN8 has no current flowing because its drain voltage is low, and as INP gradually increases, MN8 has drain voltage increasing and current increasing, and IMN1And IMN2Then the current of the current sensor is increased and stabilized at the set current I2At a value of I with further increase of INP voltage1Gradually increases the current of MN8, gradually decreases the current of MN8, when INP is equal to VGSN, EN _ NEA becomes high, the NMOS input stage operational amplification unit starts to work, and at this time, IMN1And IMN2The current of the capacitor reaches the set value, so that the offset voltage does not change at this time.
When the INP voltage is from zero to VDD-VGSP, the PMOS input stageThe operational amplification unit is always in a normal working state, and the offset voltage of the operational amplification unit is a set value. When INP rises to I4When it is unable to work normally, I4Gradually decreases the current of MP16, but then IMP7And IMP8Has a current of I4Current of (1) andMP16sum, and still maintain the set value I0When INN reaches VDD-VGSP, EN _ PEA becomes low, the PMOS input stage operational amplification unit stops working, and then the NMOS input stage operational amplification unit continues working and maintains the output voltage.
It can be seen from the above analysis that the rail-to-rail operational amplifier with constant offset voltage of the present invention can operate in the range from the reference potential (ground potential) to the full swing voltage of the power supply voltage VDD, and since the operating state of the rail-to-rail operational amplifier is established before the NMOS/PMOS input stage operational amplifier unit is enabled, the offset voltage VOS-INN-INP of the rail-to-rail operational amplifier unit is not affected and remains constant during the switching operation of the NMOS/PMOS input stage operational amplifier unit.
According to the technical scheme, the invention has the following advantages:
the rail-to-rail operational amplifier can work in a full swing voltage range and has constant offset voltage in the working process.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. A constant offset voltage rail-to-rail operational amplifier, the rail-to-rail operational amplifier comprising:
a first input stage operational amplifier unit electrically connected between the power supply voltage VDD and the reference potential and including multiple MOS transistors and a first resistor R1First resistance R1For generating a first offset voltage;
a first bias enhancement control unit and a first control tube for generating a first control signal and a second control signal, wherein the first control signal is used for controlling the first control tube to maintain a current flowing through the first resistor R1First current I ofR1The second control signal is used for stabilizing the first current I when the first current I cannot be stabilizedR1The first input stage operational amplification unit is turned off;
a second input stage operational amplification unit electrically connected between the power supply voltage VDD and the reference potential and the first input stage operational amplification unit, comprising a plurality of MOS transistors and a second resistor R2A second resistance R2For generating a second offset voltage;
a second bias enhancement control unit and a second control tube for generating a third control signal and a fourth control signal, wherein the third control signal is used for controlling the second control tube to maintain a current flowing through a second resistor R2Second current I ofR2The fourth control signal is used for stabilizing the second current IR2The second input stage operational amplification unit is turned off.
2. The constant offset voltage rail-to-rail operational amplifier as claimed in claim 1, wherein the first input stage operational amplifier unit is an NMOS input stage operational amplifier unit comprising a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN4MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, and a first resistor R1And a first current source I1, wherein:
the source electrode of the third PMOS tube MP3 is connected with a power supply voltage VDD, the grid electrode is connected with the drain electrode, the source electrode of the fourth PMOS tube MP4 is connected with the power supply voltage VDD, and the grid electrode is connected with the drain electrode;
the grid of the first NMOS transistor MN1 is connected with the first signal input end, the drain is connected with the drain of the third PMOS transistor MP3, the grid of the second NMOS transistor MN2 is connected with the second signal input end, the drain is connected with the drain of the fourth PMOS transistor MP4, and the source is connected with the first resistor R1Are connected with each other;
the first terminal of the first current source I1, the source of the first NMOS transistor MN1 and the first resistor R1The second end of the first resistor is connected with a reference potential;
the source electrode of the first PMOS tube MP1 is connected with a power supply voltage VDD, the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of a twelfth NMOS tube MN12, the grid electrode of the twelfth NMOS tube MN12 is connected with the drain electrode of a twelfth NMOS tube MN12, and the source electrode of the twelfth NMOS tube MN12 is connected with a reference potential;
the source electrode of the sixth PMOS tube MP6 is connected with a power supply voltage VDD, the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth NMOS tube MN5, the grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN5, and the source electrode of the fifth NMOS tube MN5 is connected with a reference potential;
the drain electrode of a fourteenth NMOS tube MN14 is connected with the second input-stage operational amplification unit, the source electrode is connected with the drain electrode of a thirteenth NMOS tube MN13, the grid electrode of the thirteenth NMOS tube MN13 is connected with the grid electrode of a twelfth NMOS tube NM12, and the source electrode is connected with a reference potential;
the drain electrode of the third NMOS tube MN3 is connected with the signal output end, the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourteenth NMOS tube MN14, the source electrode of the third NMOS tube MN4 is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the fourth NMOS tube MN4 is connected with the grid electrode of the fifth NMOS tube MN5, and the source electrode of the fourth NMOS tube MN4 is connected with the reference potential;
the second input stage operational amplification unit is a PMOS input stage operational amplification unit, and comprises a seventh PMOS tube MP7, an eighth PMOS tube MP8, a tenth PMOS tube MP10 and an eleventh PMOS tube MP11Sixteenth NMOS transistor MN16, seventeenth NMOS transistor MN17, eighteenth NMOS transistor MN18, nineteenth NMOS transistor MN19, twenty first NMOS transistor MN21, twenty second NMOS transistor MN22, and second resistor R2And a fourth current source I4, wherein:
the source electrode of the seventeenth NMOS transistor MN17 is connected with the reference potential, the grid electrode is connected with the drain electrode, the source electrode of the eighteenth NMOS transistor MN18 is connected with the reference potential, and the grid electrode is connected with the drain electrode;
the gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, the drain is connected to the drain of the seventeenth NMOS transistor MN17, the gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, the drain is connected to the drain of the eighteenth NMOS transistor MN18, and the source is connected to the second resistor R2Are connected with each other;
a first terminal of the second current source I2 is connected to the reference potential, and a second terminal thereof is connected to the source of the seventh PMOS transistor MP7 and the second resistor R2Are connected with each other;
a source electrode of the tenth PMOS transistor MP10 is connected to a power supply voltage VDD, a gate electrode is connected to a drain electrode, a drain electrode is connected to a drain electrode of the twenty-first NMOS transistor MN21, a drain electrode of the twenty-first NMOS transistor MN21 is connected to a drain electrode of the fourteenth NMOS transistor MN14, a source electrode is connected to a drain electrode of the sixteenth NMOS transistor MN16, a gate electrode of the sixteenth NMOS transistor MN16 is connected to a gate electrode of the seventeenth NMOS transistor MN17, and a source electrode is connected to a reference potential;
the source electrode of the eleventh PMOS tube MP11 is connected with a power supply voltage VDD, the grid electrode of the eleventh PMOS tube MP11 is connected with the grid electrode of the tenth PMOS tube MP10, the drain electrode of the eleventh PMOS tube MP 3578 is connected with the drain electrode of the twenty-second NMOS tube MN22, the source electrode of the twenty-second NMOS tube MN22 is connected with the drain electrode of the nineteenth NMOS tube MN19, the grid electrode of the nineteenth NMOS tube MN19 is connected with the grid electrode of the eighteenth NMOS tube MN18, the source electrode of the nineteenth NMOS tube MN19 is connected with a reference potential, and the drain electrode of the eleventh PMOS tube MP11 and the drain electrode of the twenty-second NMOS tube MN22 are connected with a signal output end.
3. The constant offset voltage rail-to-rail operational amplifier of claim 2, wherein the first resistor R1And a second resistor R2Are equal in resistance, i.e. R1＝R2The first offset voltage is VOS1＝R1*IR1The second offset voltage is VOS2＝R2*IR2(ii) a The current of the first current source I1 is I1＝I0The current of the fourth current source I4 is I4＝I0。
4. The constant offset voltage rail-to-rail operational amplifier as claimed in claim 2, wherein the first control transistor is an eighth NMOS transistor MN8, a gate of the eighth NMOS transistor MN8 is connected to the first bias boosting control unit, a source is connected to the reference potential, and a drain is connected to the first terminal of the first current source I1; the second control tube is a sixteenth PMOS tube MP16, the grid electrode of the sixteenth PMOS tube MP16 is connected with the second bias enhancement control unit, the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the second resistor R2Are connected to each other.
5. The constant offset voltage rail-to-rail operational amplifier of claim 4, wherein the first bias boosting control unit comprises a first sampling unit and a first control unit, the first sampling unit comprises a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11 and a second current source I2, the first control unit comprises a ninth NMOS transistor MN9, a third current source I3 and a first Schmitt trigger, wherein:
the source electrode of the second PMOS tube MP2 is connected with a power supply voltage VDD, the grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the third PMOS tube MP3, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the eleventh NMOS tube MN11, the grid electrode of the eleventh NMOS tube MN11 is connected with the drain electrode, and the source electrode of the eleventh NMOS tube MN11 is connected with a reference potential;
a first end of a second current source I2 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a tenth NMOS tube MN10, a grid electrode of a tenth NMOS tube MN10 is connected with a grid electrode of an eleventh NMOS tube MN11, and the drain electrode is connected with a reference potential;
the source electrode of the fifth PMOS tube MP5 is connected with a power supply voltage VDD, the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrode of the fourth PMOS tube MP4, the drain electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the sixth NMOS tube MN6, the grid electrode of the sixth NMOS tube MN6 is connected with the drain electrode, and the source electrode of the sixth NMOS tube MN6 is connected with a reference potential;
the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the sixth NMOS transistor MN6, the drain electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN8, the grid electrode of the ninth NMOS transistor MN9 and the drain electrode of the tenth NMOS transistor MN10, and the source electrode of the seventh NMOS transistor MN7 is connected with the reference potential;
a first end of a third current source I3 is connected with a power supply voltage VDD, a second end is connected with a drain electrode of a ninth NMOS transistor MN9, a grid electrode of the ninth NMOS transistor MN9 is connected with a grid electrode of an eighth NMOS transistor MN8, and a source electrode is connected with a reference potential;
the input end of the first Schmitt trigger is connected with the drain electrode of a ninth NMOS transistor MN9, and the output end of the first Schmitt trigger is connected with the grid electrode of a fourteenth NMOS transistor MN14 and the grid electrode of a third NMOS transistor MN 3;
the second bias enhancement control unit comprises a second sampling unit and a second control unit, the second sampling unit comprises a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20 and a fifth current source I5, the second control unit comprises a fifteenth PMOS transistor MP15, a sixth current source I6 and a second schmitt trigger, wherein:
the source electrode of the ninth PMOS transistor MP9 is connected with the power supply voltage VDD, the grid electrode is connected with the drain electrode, the drain electrode is connected with the drain electrode of a fifteenth NMOS transistor MN15, the grid electrode of the fifteenth NMOS transistor MN15 is connected with the grid electrode of a seventeenth NMOS transistor MN17, and the source electrode is connected with the reference potential;
the source of the twelfth PMOS transistor MP12 is connected with the power supply voltage VDD, the gate is connected with the gate of the ninth PMOS transistor MP9, the drain is connected with the first end of the fifth current source I5, the source of the thirteenth PMOS transistor MP13 is connected with the power supply voltage VDD, the drain is connected with the first end of the fifth current source I5, and the second end of the fifth current source I5 is connected with the reference potential;
a source electrode of the fourteenth PMOS tube MP14 is connected with a power supply voltage VDD, a grid electrode of the fourteenth PMOS tube MP 3578 is connected with a grid electrode of the thirteenth PMOS tube MP13, a drain electrode of the fourteenth PMOS tube MP14 is connected with a grid electrode of the fourteenth PMOS tube MP14 and a drain electrode of the twentieth NMOS tube MN20, a grid electrode of the twentieth NMOS tube MN20 is connected with a grid electrode of the eighteenth NMOS tube MN18, and a source electrode of the twentieth NMOS tube MN20 is connected with a reference potential;
the source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate thereof is connected to the gate of the sixteenth PMOS transistor MP16, the drain thereof is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential;
the input end of the second schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first end of the sixth current source I6, and the output end is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN 22.
6. The constant offset voltage rail-to-rail operational amplifier of claim 5, wherein the current of the second current source I2 is I2＝I0The current of the third current source I3 is I3＝I0/2, the current of the fifth current source I5 is I5＝I0The current of the sixth current source I6 is I6＝I0/2。
7. The constant offset voltage rail-to-rail operational amplifier as claimed in claim 5, wherein the first sampling unit is configured to collect the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2 and the current I of the second current source I22Comparing to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN 8;
the second sampling unit is used for collecting the current flowing through the seventh PMOS tube MP7 and the eighth PMOS tube MP8 and the current I of the fifth current source I55And comparing to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP 16.
8. The constant offset voltage rail-to-rail operational amplifier of claim 7, wherein the first control unit is configured to turn off the first input stage operational amplifier unit when the current of the eighth NMOS transistor MN8 is greater than the first current threshold;
the second control unit is used for turning off the first input stage operational amplification unit when the current of the sixteenth PMOS transistor MP16 is smaller than the second current threshold.
9. The constant offset voltage rail-to-rail operational amplifier of claim 8, wherein the rail-to-rail operational amplifier has a signal output terminal connected to the second signal input terminal and a first signal input terminal receiving a linearly increasing or decreasing voltage signal.
10. The constant offset voltage rail-to-rail operational amplifier of claim 9, wherein the rail-to-rail operational amplifier:
at the time t1-t2 and the time t4-t5, the NMOS input stage operational amplification unit and the PMOS input stage operational amplification unit are both in a working state;
at the time t2-t4, the NMOS input stage operational amplification unit is in a working state, and the PMOS input stage operational amplification unit is in a non-working state;
at time t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is equal to INN-INP and is kept constant, INP and INN are the voltage signal at the first signal input terminal and the voltage signal at the second signal input terminal, respectively;
at time t1, the voltage signal at the first signal input end is equal to VGSN, where VGSN is Vthn + Vdson, Vthn is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN2, and Vdson is the overdrive voltage;
at time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, VGSP is Vthp + Vdson, Vthp is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and Vdson is the overdrive voltage;
at time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power voltage VDD;
at time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP;
at time t5, the voltage signal at the first signal input terminal is equal to VGSN.
CN202111301686.4A 2021-11-04 2021-11-04 Constant offset voltage rail-to-rail operational amplifier Pending CN114024516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111301686.4A CN114024516A (en) 2021-11-04 2021-11-04 Constant offset voltage rail-to-rail operational amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111301686.4A CN114024516A (en) 2021-11-04 2021-11-04 Constant offset voltage rail-to-rail operational amplifier

Publications (1)

Publication Number Publication Date
CN114024516A true CN114024516A (en) 2022-02-08

Family

ID=80060882

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111301686.4A Pending CN114024516A (en) 2021-11-04 2021-11-04 Constant offset voltage rail-to-rail operational amplifier

Country Status (1)

Country Link
CN (1) CN114024516A (en)

Similar Documents

Publication Publication Date Title
CN108803761B (en) LDO circuit that contains high-order temperature compensation
KR100322539B1 (en) Sense amplifying apparatus of semiconductor integrated circuit
CN113703510B (en) Band gap reference circuit with low power consumption
CN109286372B (en) High-precision oscillator circuit
CN116827320B (en) Fast-response self-adaptive power supply conversion circuit
JP2007081907A (en) Output buffer circuit
CN110703010A (en) Test circuit
CN103956983B (en) A kind of error amplifier with clamping function
US8638126B2 (en) Rail-to-rail comparator
KR100221942B1 (en) Semiconductor integrated circuit
JP4749105B2 (en) Reference voltage generation circuit
CN114625196B (en) LDO circuit with wide input common mode range
CN114024516A (en) Constant offset voltage rail-to-rail operational amplifier
CN113644901B (en) High-speed comparator circuit
CN110460338B (en) Sampling hold circuit
CN114696802A (en) Comparator circuit and chip comprising same
CN111510090B (en) Operational amplifier with high voltage slew rate and wide output range
CN114725897A (en) Overcurrent protection circuit for switching power supply
CN108768352B (en) Comparator with a comparator circuit
CN210534616U (en) Reference circuit and integrated circuit
CN112242823B (en) Differential input circuit, control method thereof and differential amplifier
KR100873287B1 (en) Comparator with Hysteresis Characteristics
CN107888184B (en) Single-end-to-differential circuit and buffer circuit and sample hold circuit formed by same
CN112947660B (en) Pretreatment circuit and pretreatment method for power supply voltage
CN113050741B (en) Low-power consumption band-gap reference source circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination