CN202261165U - Annular voltage-controlled oscillator - Google Patents

Abstract

The utility model discloses an annular voltage-controlled oscillator, which comprises a reference voltage resource, a voltage stabilization circuit, a compensation circuit and an oscillation circuit, wherein the output of the reference voltage source is connected with the input end of the voltage stabilization circuit; the voltage stabilization circuit generates two paths of output voltages; the first output serves as working voltage of the oscillation circuit, and the second output is input into the compensation circuit and serves as input voltage of the compensation circuit; and the output of the compensation circuit serves as bias voltage of the oscillation circuit. The oscillation frequency of the oscillation circuit is controlled by generating the bias voltage which is changed along with the temperature and the process, so that the output frequency deflection of the oscillator is compensated automatically. When the frequency of the oscillation circuit is increased along with the raise of the temperature, the compensation circuit generates control voltage reduced along with the temperature so as to compensate the reduction of the compensation frequency; and when a process angle is changed from SS to FF, the frequency of the oscillation circuit is increased, and the compensation circuit generates control voltage reduced along with the process so as to compensate the reduction of the compensation frequency.

Description

A kind of annular voltage controlled oscillator

Technical field

The utility model belongs to the IC design technical field, is specifically related to a kind of annular voltage controlled oscillator with temperature and technology self compensation function.

Background technology

Oscillator is the main modular of many electronic systems, and the clock generating of range of application from microprocessor is synthetic to the carrier wave in the wireless communication system.The most general oscillator is a quartz oscillator, and the performance of crystal oscillator is very stable, and precision is very high, but it can not be integrated in chip system inside.Utilize the CMOS technology of standard to realize that oscillator replaces the outer crystal oscillator of sheet on the sheet, for the cost that reduces system, the integrated level that improves system is with helpful.

Along with the development of semiconductor process techniques, the integrated level of chip is also increasingly high, thereby has caused the rapid rising of power consumption, and power problems becomes the critical limitation factor that modern large scale integrated circuit is realized just day by day.The numerous characteristics of MOS transistor all changes with temperature in addition, and in chip manufacturing proces, and between different wafers and different batches, transistorized parameter alters a great deal.Therefore, realize that the challenge that oscillator mainly faces on the sheet mainly shows two aspects: the one, low-power consumption, the power consumption of oscillator module should be as far as possible little, to reduce the power consumption of entire chip; The 2nd, high accuracy, promptly frequency of oscillation keeps high stability for the variation of supply voltage, temperature and technology.

Go up oscillator for existing and mainly contain following several kinds.

(1) pursues the low-power consumption of circuit, and adopted the simple pierce circuit of structure.This oscillator receives temperature and technogenic influence bigger, and the system that frequency accuracy is had relatively high expectations is difficult to meet the demands.

(2) have the pierce circuit of digital circuit calibration function.In order to obtain high-precision frequency of oscillation; In oscillator, having added the digital circuit calibration module comes the frequency of oscillation deviation is calibrated; But this mode has increased the complexity of design and the power consumption of circuit greatly; Be not suitable for being used in in the strict system of the low-power consumption of chip, for example as the ultrahigh frequency electronic tag of Internet of Things node.

(3) based on the oscillator with temperature compensation effect of band-gap reference.This oscillator adopts the variation of the good bipolar transistor sense temperature of the temperature coefficient linearity, yet sort circuit structure power consumption is bigger, and bad with the standard CMOS process compatibility.In addition, this structure can not compensate technique change, and the frequency departure that causes because of technology is also quite big.

Owing to go up the problems referred to above that pierce circuit exists for existing, therefore can not be used in the system that low-power consumption, low cost, high accuracy and integrated level are all had higher requirements.

The utility model content

The purpose of the utility model is to receive temperature and the bigger problem of technogenic influence in order to solve existing pierce circuit, has proposed a kind of annular voltage controlled oscillator.

The technical scheme of the utility model is: a kind of annular voltage controlled oscillator comprises: reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit, and said reference voltage source output is connected with the input of said voltage stabilizing circuit; Said voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of said compensating circuit links to each other with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of said annular voltage controlled oscillator.

The beneficial effect of the utility model is: the annular voltage controlled oscillator of the utility model is realized the output frequency deviation of automatic compensated oscillator through producing the frequency of oscillation that a bias voltage with temperature and technique change comes control oscillation circuit.When temperature raise the frequency rising that causes oscillating circuit, compensating circuit produced a bias voltage that reduces with temperature, made the frequency of oscillating circuit descend, thereby reached the purpose of compensating frequency, the i.e. decline of compensating frequency; When process corner changes from SS to FF; The frequency of oscillating circuit also raises, and compensating circuit produces a bias voltage that reduces with above-mentioned technique change trend, makes the frequency of oscillating circuit descend; Thereby also can reach the purpose of compensating frequency, i.e. the decline of compensating frequency.Can guarantee that so, then output frequency is consistent under different temperatures and process conditions.

Description of drawings

Fig. 1 is the annular voltage controlled oscillator structured flowchart of the utility model.

Fig. 2 is the schematic diagram of the reference voltage source of the utility model embodiment.

Fig. 3 is the schematic diagram of the voltage stabilizing circuit of the utility model embodiment.

Fig. 4 is the schematic diagram of the compensating circuit of the utility model embodiment.

Fig. 5 is the schematic diagram of the oscillating circuit of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is elaborated.

The annular voltage controlled oscillator structured flowchart that the utility model proposes is as shown in Figure 1, specifically comprises reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit.Said reference voltage source output is connected with the input of said voltage stabilizing circuit; Said voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of said compensating circuit links to each other with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of said annular voltage controlled oscillator.

Wherein, the reference voltage source road produces one and has nothing to do with supply voltage and temperature, and with the reference voltage V of technique change _RefVoltage stabilizing circuit is with reference voltage V _RefAmplify in proportion, produce two output voltage, one road V _DdAs the operating voltage of oscillating circuit, another road V _pBe input to compensating circuit; Compensating circuit produces a bias voltage V _CtrlThe output frequency of control oscillation circuit, bias voltage and frequency of oscillation are positive correlations, when the temperature rising caused frequency of oscillation to raise, compensating circuit produced a bias voltage that reduces with temperature, thus the decline of compensating frequency; When process corner changed from SS to FF, frequency of oscillation also raise, and compensating circuit produces a bias voltage that reduces with above-mentioned technique change trend, thus the decline of compensating frequency.Can guarantee that so, then output frequency is consistent under different temperatures and process conditions.

Fig. 2 is a kind of mode that reference voltage source is implemented.Owing to contain bipolar device in traditional band gap reference; Output reference voltage high (about 1.25V), power consumption is big, therefore is not suitable for being used in the CMOS integrated circuit of low-voltage and low-power dissipation; Therefore the utility model adopts the CMOS reference source circuit; Comprise start-up circuit, reference current generating circuit, reference voltage generating circuit, the input of start-up circuit are the output V of CMOS a reference source _Ref, the output of start-up circuit is connected to the input of reference current generating circuit, the input of the output termination reference voltage generating circuit of reference current generating circuit, through current mirror with reference current I ₀Be mirrored to reference voltage generating circuit, reference voltage generating circuit output and supply voltage V _CcWith the irrelevant reference voltage V of temperature _RefAll PMOS pipe substrates all meet external power source V among Fig. 2 _Cc, the equal ground connection of all NMOS pipe substrates.

Start-up circuit comprises PMOS pipe MP1, MP2 and NMOS pipe MN1, MN2, and wherein, the drain electrode of the source electrode of PMOS pipe MP1 and NMOS pipe MN2 meets external power source V _CcThe grid of PMOS pipe MP1 links to each other with drain electrode and links to each other with the source electrode of PMOS pipe MP2; The grid of PMOS pipe MP2 links to each other as the input of start-up circuit with the grid of NMOS pipe MN1; The drain electrode of the drain electrode of PMOS pipe MP2 and NMOS pipe MN1 links to each other and is connected to the grid that NMOS manages MN2, and the source electrode of NMOS pipe MN2 is as the output of start-up circuit.Because have two stable states in the reference current source circuit, one is zero current condition, one is the operating state of hoping, the function of start-up circuit is to make circuit to break away from the operating state that nought state enters into hope.When being in zero current condition, output reference voltage V _RefBe low-voltage, behind the inverter through PMOS pipe MP2 and NMOS pipe MN1 formation, produce the grid that high voltage is input to NMOS pipe MN2, make NMOS pipe MN2 conducting, output HIGH voltage works on power circuit to reference current generating circuit.

Reference current generating circuit comprises PMOS pipe MP3, MP4, NMOS pipe MN3, MN4, MN5 and amplifier OPA1; Wherein, The grid of PMOS pipe MP3 and MP4 links to each other as the output of reference current generating circuit; Link together source electrode and the external power source V of PMOS pipe MP3 and MP4 with the output of amplifier OPA1 _CcLink to each other, the drain electrode of PMOS pipe MP3 links to each other as the input of reference current generating circuit with the drain electrode of NMOS pipe MN3, and is connected to the negative input end of amplifier OPA1; The drain electrode that the drain electrode of PMOS pipe MP4 and NMOS manage MN4 links to each other and is connected to the positive input terminal of amplifier OPA1; The grid of NMOS pipe MN3 and MN4 links to each other, and the grid of NMOS pipe MN3 links to each other source ground with drain electrode; The source electrode of NMOS pipe MN4 is connected to the drain electrode of NMOS pipe MN5, and the grid of NMOS pipe MN5 is connected to reference voltage V _Ref, source ground.

Amplifier OPA1 forces to make the drain voltage of PMOS pipe MP3 and MP4 to equate, thereby the electric current of two branch roads equates in the reference voltage generating circuit, is made as I ₀NMOS pipe MN3 and MN4 work in sub-threshold region, and NMOS pipe MN5 works in dark linear zone, is equivalent to a resistance, is made as R ₀So, obtain a reference current

$I_0=\frac{{\mathrm{nV}}_T}{R_0}\ln \left(\frac{W_{N3}{L}_{N4}}{L_{N3}{W}_{N4}}\right)$

Wherein n is the sub-threshold slope factor, V _TBe thermal voltage, K is a Boltzmann constant, and T is an absolute temperature, and q is the quantity of electric charge of an electronics, and W/L representes the breadth length ratio of metal-oxide-semiconductor.Thus it is clear that, I ₀Be to be independent of supply voltage, be directly proportional with absolute temperature.

Reference voltage generating circuit comprises PMOS pipe MP5, MP6, MP7, NMOS pipe MN6, MN7, MN8, MN9, MN10 and capacitor C 1, and wherein, the source electrode of PMOS pipe MP5, MP6, MP7 all is connected to external power source V _Cc, grid all links together as the input of reference voltage generating circuit, and drain electrode then links to each other respectively with the drain electrode of NMOS pipe MN6, MN8, MN10 respectively, wherein the drain electrode output reference voltage V of PMOS pipe MP7 _RefAnd be connected to ground through capacitor C 1, and NMOS pipe MN6, MN8, MN10 grid and drain electrode separately link together, and the source electrode of NMOS pipe MN6 links to each other with the source electrode that NMOS manages MN9 with the drain electrode of NMOS pipe MN7; The source electrode of NMOS pipe MN8 links to each other with the drain electrode of NMOS pipe MN9 and the source electrode of NMOS pipe MN10; The grid of NMOS pipe MN7 links to each other with the grid of NMOS pipe MN6, source ground, and the grid of NMOS pipe MN9 links to each other with the grid of NMOS pipe MN8.

PMOS pipe MP5, MP6, MP7 are identical, thereby mirror image goes out 3 identical electric currents, and NMOS pipe MN6, MN7, MN8, MN9, MN10 all work in sub-threshold region, and its gate source voltage is respectively V _GS6, V _GS7, V _GS8, V _GS9, V _GS10s, then output reference voltage does

$V_{\mathrm{ref}}=V_{\mathrm{GSN}10}-V_{\mathrm{GSN}8}+V_{\mathrm{GSN}9}-V_{\mathrm{GSN}6}+V_{\mathrm{GSN}7}$

$=n{V}_T\ln \left(\frac{W_{N8}{L}_{N10}{W}_{N6}{L}_{N9}}{L_{N8}{W}_{N10}{L}_{N6}{W}_{N9}}\right)+V_{\mathrm{GSN}7}$

$=V_{\mathrm{TH}0}+T[\frac{\mathrm{kn}}{q}\ln \left(\frac{W_{P5}{L}_{P4}{L}_{N7}{I}_0}{L_{P5}{W}_{P4}{W}_{N7}{I}_{D0}}\right)+\frac{\mathrm{kn}}{q}\ln \left(\frac{W_{N8}{L}_{N10}{W}_{N6}{L}_{N9}}{L_{N8}{W}_{N10}{L}_{N6}{W}_{N9}}\right)-\mathrm{\κ}]$

V _TH0Be that absolute temperature is the threshold voltage of 0 o'clock metal-oxide-semiconductor, I _D0Be the subthreshold value characteristic current, κ is the temperature coefficient of metal-oxide-semiconductor threshold voltage, can make the part in the above-mentioned bracket equal 0 through the breadth length ratio of confirming metal-oxide-semiconductor MP4, MP5, MN6, MN7, MN8, MN9, MN10, thereby obtain V _Ref=V _TH0V _TH0Irrelevant with supply voltage and temperature, and receive effect of process variations, when process corner changes from SS to FF, V _TH0Reduce, obtained with supply voltage and temperature irrelevant and thus with the reference voltage V of technique change _Ref

Fig. 3 is a kind of execution mode of voltage stabilizing circuit.Voltage stabilizing circuit comprises PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, amplifier OPA2, OPA3 and capacitor C 2, C3, and wherein the negative input end of amplifier OPA2 and OPA3 links together as the input V of voltage stabilizing circuit _RefThe positive input terminal of amplifier OPA2 and OPA3 links to each other with the grid of PMOS pipe MP9 and MP14 respectively; The output of amplifier OPA2 and OPA3 links to each other with the grid of PMOS pipe MP8 and MP12 respectively; The substrate of PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15 all is connected to source electrode separately, and the grid separately of PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 links to each other with drain electrode and constitutes the MOS diode, and the source electrode of PMOS pipe MP8 and MP12 all is connected to external power source V _CcThe corresponding source electrode that connects PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 of the drain electrode of PMOS pipe MP8, MP9, MP10, MP12, MP13, MP14; The drain electrode that the grounded drain of PMOS pipe MP11 and MP15, PMOS are managed MP8 and MP12 is respectively as the first output V of voltage stabilizing circuit _DdWith the second output V _p, and be connected to ground through capacitor C 2 with C3 respectively.

Can see that by Fig. 3 voltage stabilizing circuit is made up of two essentially identical branch roads of circuit structure, to produce output voltage V _DdBranch road be the operation principle of example explanation circuit: metal-oxide-semiconductor MP9, MP10, the MP11 formation bleeder circuit of connecting each other, with output voltage V _DdBe divided into some parts, the negative input end of amplifier OPA2 is connected to the grid of one of them metal-oxide-semiconductor, forces it to equal amplifier positive input terminal voltage V _Ref,, offset temperature and effect of process variations, thereby reached reference voltage V because used metal-oxide-semiconductor is identical _RefThe effect of amplifying in proportion.Those of ordinary skill in the art is to be appreciated that; Fig. 3 is an example of this voltage stabilizing circuit structure; In practical application, the position that the quantity of the metal-oxide-semiconductor of series connection and amplifier negative input end connect should determine according to the size of the voltage stabilizing output voltage of required generation.

Fig. 4 is a kind of execution mode of compensating circuit, comprises that resistance R 1, resistance R 2, NMOS manage MN11, and wherein, an end of resistance R 1 is the input V of compensating circuit _p, the other end is the output V of compensating circuit _Ctrl, the grid of NMOS pipe MN11 and the output V that drains and link to each other and be connected to compensating circuit through resistance R 2 _Ctrl, substrate and the source ground of NMOS pipe MN11.The output voltage V of compensating circuit _CtrlAs the bias voltage of oscillating circuit, be the main factor of decision frequency of oscillation, V _CtrlCenter voltage guarantee that oscillating circuit produces required frequency of oscillation, on the other hand, near electrocardio is pressed therein, V _CtrlNeeding has variation among a small circle with temperature and technology, thereby the output frequency of compensation oscillating circuit is with the variation of temperature and technology.The characteristic of metal-oxide-semiconductor is temperature influence both, receives technogenic influence again, and the resistance of resistance mainly receives effect of process variations.NMOS pipe MN11 and resistance R 1, R2 constitute bleeder circuit in the compensating circuit, and the NMOS pipe mainly plays temperature-compensating, and resistance R 1, R2 have confirmed V through dividing potential drop _CtrlCenter voltage (under normal temperature and typical process angle, the output voltage of compensating circuit is V _CtrlCenter voltage).As previously mentioned, reference voltage source produces one and has nothing to do with supply voltage and temperature, and with the reference voltage V of technique change _Ref, the V that after voltage stabilizing circuit amplifies in proportion, obtains _pAlso irrelevant and with technique change with supply voltage and temperature, V _pAct on compensating circuit to realize technological compensa tion.When temperature raise, the threshold voltage of metal-oxide-semiconductor reduced, and resistance is very little with variation of temperature, can ignore, and is like this then obtain the output voltage V with the temperature reduction _CtrlWhen process corner changed from SS to FF, the threshold voltage of metal-oxide-semiconductor reduced, and its equivalent resistance reduces, and the resistance of resistance also reduces, and then the dividing potential drop in the compensating circuit is close like constant, thereby with input V _pOperational characteristic be delivered to output V _Ctrl, obtain the bias voltage V that reduces with above-mentioned technique change trend _Ctrl

Fig. 5 is a kind of execution mode of oscillating circuit, comprises bias current generating circuit, vibration core circuit and pulse shaper.Bias voltage V _CtrlInput as bias current generating circuit; The characteristic that the temperature and the operational characteristic of voltage is converted into bias current; Through current mirror bias current is mirrored to the vibration core circuit; The time of delay of control generator delay cell, thus the frequency of oscillator determined, the waveform V that pulse shaper produces the vibration core circuit _OscShaping, the cycle rectangle square wave V of output rule _Out

Bias current generating circuit is the common-source amplifier of a band source negative feedback resistance; Input voltage is converted into output current; Negative feedback resistor has improved the linearity of amplifier; Make the temperature and the operational characteristic of output current milder, when temperature raises or process corner when from SS to FF, changing, bias current all reduces.Bias current generating circuit comprises PMOS pipe MP16, NMOS pipe M12 and resistance R 3.The grid of NMOS pipe MN12 and the output V of compensating circuit _CtrlLink to each other, the substrate ground connection of NMOS pipe MN12, source electrode is through resistance R 3 ground connection, and drain electrode links to each other with the drain electrode of PMOS pipe MP16, and source electrode and the substrate of PMOS pipe MP16 all are connected to operating voltage V _Dd, the grid of PMOS pipe MP16 is as the output of bias current generating circuit.

The vibration core circuit is made up of the end to end delay cell of N level; Delay cell can be single-ended; Also can be difference form, for single-ended delay cell, its progression N can only be the odd number more than or equal to 3; Delay cell for difference form; Progression N can be the arbitrary integer more than or equal to 2, and the progression of delay cell should be looked the size of the frequency of oscillation that will produce and determine, the current source that is come by the bias current generating circuit mirror image is as the size of the load control lag time of delay cell.

As a simple and effective example; Demonstrated the vibration core circuit of 3 grades of single-ended format among Fig. 5; Comprise PMOS transistor MP17, MP18, MP19, inverter INV1, INV2, INV3, substrate and the source electrode of PMOS transistor MP17, MP18, MP19 all are connected to operating voltage V _DdGrid all links together as the input of vibration core circuit; And link to each other with output that biasing circuit produces circuit; Corresponding respectively the operating voltage of the drain electrode of PMOS transistor MP17, MP18, MP19 as inverter INV1, INV2, INV3, inverter INV1, INV2, the INV3 formation ring-type that joins end to end, inverter INV3 output waveform V _OscUnder the constant situation of bias current, when temperature raise, the frequency of oscillation of ring oscillator raise; When process corner changes from SS to FF; Frequency of oscillation also raises, and the bias current that is produced reduces with the trend of said temperature and technique change, and bias current and output frequency are the linear positive relations; Therefore the temperature and the operational characteristic of bias current can be done compensation to frequency of oscillation, obtain stable output frequency.

The effect of pulse shaper is the cycle square wave that waveform is shaped as rule, and simple proposal is to adopt the one-level inverter.As shown in Figure 5, the input of inverter INV4 links to each other with the output of inverter INV3, i.e. inverter INV4 input waveform V _Osc, the recurrent pulse square wave V of output rule after the shaping _Out, be the output of oscillating circuit, that is to say the output of annular voltage controlled oscillator.

The utility model utilizes the temperature and the operational characteristic of cmos device; Designed a kind of annular voltage controlled oscillator that can compensate frequency departure automatically; Under different temperature and process conditions, frequency of oscillation keeps advantages of higher stability, and circuit power consumption is low; Compatibility standard CMOS technology is in the electronic system that is suitable for power consumption, cost and frequency accuracy are all had higher requirements.The pierce circuit of the utility model only comprises NMOS, PMOS, resistance, four kinds of devices of electric capacity, have simple in structure, on the CMOS processing line, realize convenient, effectively, compatible good advantage.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help the principle of reader understanding's the utility model, should to be understood that the protection range of the utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these teachings of the utility model, and these distortion and combination are still in the protection range of the utility model.

Claims (5)

1. an annular voltage controlled oscillator is characterized in that, comprising: reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit, and said reference voltage source output is connected with the input of said voltage stabilizing circuit; Said voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of said compensating circuit links to each other with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of said annular voltage controlled oscillator.

2. annular voltage controlled oscillator according to claim 1 is characterized in that described reference voltage source comprises start-up circuit; Reference current generating circuit and reference voltage generating circuit, the input of start-up circuit are the output of reference voltage source, and the output of start-up circuit is connected to the input of reference current generating circuit; The input of the output termination reference voltage generating circuit of reference current generating circuit; Reference voltage generating circuit output is the output of reference voltage source, wherein

Described start-up circuit comprises PMOS pipe MP1, MP2 and NMOS pipe MN1, MN2; Wherein, The drain electrode of the source electrode of PMOS pipe MP1 and NMOS pipe MN2 connects external power source, and the grid of PMOS pipe MP1 links to each other with drain electrode and links to each other with the source electrode of PMOS pipe MP2, and the grid of PMOS pipe MP2 links to each other as the input of start-up circuit with the grid of NMOS pipe MN1; The drain electrode of the drain electrode of PMOS pipe MP2 and NMOS pipe MN1 links to each other and is connected to the grid that NMOS manages MN2, and the source electrode of NMOS pipe MN2 is as the output of start-up circuit;

Described reference current generating circuit comprises PMOS pipe MP3, MP4, NMOS pipe MN3, MN4, MN5 and amplifier OPA1, and wherein, the grid of PMOS pipe MP3 and MP4 links to each other as the output of reference current generating circuit; Link together with the output of amplifier OPA1, the source electrode of PMOS pipe MP3 and MP4 links to each other with external power source, and the drain electrode of PMOS pipe MP3 links to each other as the input of reference current generating circuit with the drain electrode of NMOS pipe MN3; And be connected to the negative input end of amplifier OPA1; The drain electrode of the drain electrode of PMOS pipe MP4 and NMOS pipe MN4 links to each other and is connected to the positive input terminal of amplifier OPA1, and the grid of NMOS pipe MN3 and MN4 links to each other, and the grid that NMOS manages MN3 links to each other with draining; Source ground; The source electrode of NMOS pipe MN4 is connected to the drain electrode of NMOS pipe MN5, and the grid of NMOS pipe MN5 is connected to the output of reference voltage source, source ground;

Described reference voltage generating circuit comprises PMOS pipe MP5, MP6, MP7, NMOS pipe MN6, MN7, MN8, MN9, MN10 and capacitor C 1; Wherein, The source electrode of PMOS pipe MP5, MP6, MP7 all is connected to external power source, and grid all links together as the input of reference voltage generating circuit, and the then corresponding drain electrode with NMOS pipe MN6, MN8, MN10 of drain electrode links to each other respectively; Wherein PMOS manages the drain electrode output reference voltage of MP7; And be connected to ground through capacitor C 1, and NMOS pipe MN6, MN8, MN10 grid and drain electrode separately link together, and the source electrode of NMOS pipe MN6 links to each other with the source electrode that NMOS manages MN9 with the drain electrode of NMOS pipe MN7; The source electrode of NMOS pipe MN8 links to each other with the drain electrode of NMOS pipe MN9 and the source electrode of NMOS pipe MN10; The grid of NMOS pipe MN7 links to each other with the grid of NMOS pipe MN6, source ground, and the grid of NMOS pipe MN9 links to each other with the grid of NMOS pipe MN8.

3. annular voltage controlled oscillator according to claim 1 and 2; It is characterized in that; Described voltage stabilizing circuit comprises PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, amplifier OPA2, OPA3 and capacitor C 2, C3; Wherein the negative input end of amplifier OPA2 and OPA3 links together as the input of voltage stabilizing circuit; The corresponding respectively grid with PMOS pipe MP9 and MP14 of the positive input terminal of amplifier OPA2 and OPA3 links to each other; The corresponding respectively grid with PMOS pipe MP8 and MP12 of the output of amplifier OPA2 and OPA3 links to each other; The substrate of PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15 all is connected to source electrode separately, and the grid separately of PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 links to each other with drain electrode and constitutes the MOS diode, and the source electrode of PMOS pipe MP8 and MP12 all is connected to external power source; The corresponding source electrode that connects PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 of the drain electrode of PMOS pipe MP8, MP9, MP10, MP12, MP13, MP14; The grounded drain of PMOS pipe MP11 and MP15, the drain electrode of PMOS pipe MP8 and MP12 be respectively as first output and second output of voltage stabilizing circuit, and be connected to ground through capacitor C 2 and C3 respectively.

4. annular voltage controlled oscillator according to claim 3; It is characterized in that described compensating circuit comprises that resistance R 1, resistance R 2, NMOS manage M11, wherein; One end of resistance R 1 input of circuit by way of compensation links to each other with second output of voltage stabilizing circuit; The other end is the output of circuit by way of compensation, and the grid of NMOS pipe MN11 links to each other with drain electrode and is connected to the output of compensating circuit through resistance R 2, and NMOS manages substrate and the source ground of MN11.

5. annular voltage controlled oscillator according to claim 4 is characterized in that, described oscillating circuit comprises bias current generating circuit, vibration core circuit and pulse shaper, wherein,

Described bias current generating circuit comprises PMOS pipe MP16, NMOS pipe M12 and resistance R 3; The grid of NMOS pipe MN12 links to each other with the output of compensating circuit; The substrate ground connection of NMOS pipe MN12, source electrode are through resistance R 3 ground connection, and drain electrode links to each other with the drain electrode of PMOS pipe MP16; The source electrode of PMOS pipe MP16 and first output that substrate all is connected to voltage stabilizing circuit, the grid of PMOS pipe MP16 is as the output of bias current generating circuit;

Described vibration core circuit comprises PMOS transistor MP17, MP18, MP19, inverter INV1, INV2, INV3; The substrate of PMOS transistor MP17, MP18, MP19 and source electrode all are connected to first output of voltage stabilizing circuit; Grid all links together as the input of vibration core circuit; And link to each other with output that biasing circuit produces circuit; Corresponding respectively the operating voltage of the drain electrode of PMOS transistor MP17, MP18, MP19 as inverter INV1, INV2, INV3, inverter INV1, INV2, the INV3 formation ring-type that joins end to end, inverter INV3 exports waveform;

Described pulse shaper comprises inverter INV4, and the input of inverter INV4 links to each other with the output of inverter INV3, and the output of inverter INV4 is the output of said oscillating circuit.

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