TWI430576B - System for improved phase noise in a bicmos clock driver - Google Patents

Description

Used to improve the phase noise of a clock driver in a bi-carrier complementary metal-oxide semiconductor (BiCMOS) system

The present invention relates to a method and system for a clock driver, and a plurality of systems using the method and system. More particularly, the present invention relates to a method and system for a BiCMOS clock driver, and a plurality of systems using the method and system.

Today's signal processing systems often digitize and process high-speed signals with a wide dynamic range. Digitization includes quantifying a signal into discrete levels, such as an n-bit analog to digital converter (ADC) quantized to a 2 ⁿ level; and sampling a signal at discrete time intervals. The frequency of some high-speed input signals is higher than the sampling rate of the ADC used, which causes so-called "low sampling", which requires accurate repeat reference time. Otherwise, the time uncertainty of the sampling operation may result in a larger error than when the quantization procedure was performed. This well-known problem is described in the "Prior Art" section of U.S. Patent No. 7,345,528, entitled "Method and Apparatus for Improved Clock Pre-Amplifier with Low Jitter" (hereinafter referred to as "the '528 patent").

The ideal clock signal for this system is a repetitive waveform with a perfect fixed period. Each single cycle should have exactly the same period as the other cycles. The actual clock signal can be characterized as jitter (in the time domain) or phase noise (in the frequency domain) with respect to fluctuations during each cycle. Under certain assumptions, the latter can be converted into the former. It is generally expected that the jitter or phase noise can be as small as possible.

Various attempts have been made to achieve low phase noise. For example, a low-noise bipolar junction transistor (BJT) circuit can be fabricated, for example, in an emitter-coupled logic form (ECL, Emitter-Coupled Logic) to achieve a sufficiently low phase miscellaneous News. The BJT circuit preserves signal speed and low amplitude noise integrity.

Although there is high noise in the MOSFET device itself, the conventional CMOS logic circuit can also be used to achieve low phase noise because the logic swing is large (rail-to-rail) and the phase noise has signal-to-noise (Signal- to-Noise) feature. That is, larger noise can be overcome by using a higher rail-to-rail signal level.

CMOS can retain both speed and noise only when a track-to-rail signal swing is available. However, various sources of low-phase noise signals are almost incapable of transmitting true rail-to-rail CMOS logic levels, regardless of whether the signal source is a quartz crystal oscillator, a resonant oscillator, or a carrier that transmits signals through a medium. Therefore, problems arise when a low phase noise signal is to be translated from a low level (such as an ECL or a small sinusoidal waveform) into a CMOS logic level.

There are various conventional solutions to overcome the problems associated with translating a low phase noise signal from a low level to a CMOS logic level. Unfortunately, these conventional solutions typically result in one or more of poor phase noise, speed limitations, or excessive power loss. For example, U.S. Patent No. 5,019,726, entitled "BiCMOS ECL-TO-CMOS Conversion Circuit" (hereinafter referred to as "the '726 patent") discloses a conversion circuit having a differential ECL signal and three MOSFET gates at the input end. The constructed circuit load is driven. The capacitive loading of the MOSFET gates of the '726 patent does not limit the operating speed of the circuit, or requires a large amount of power supply to drive the gates. Depending on the implementation, the solution proposed by the '726 patent may increase the level of noise. In addition, the base node of the upper BJT will have a large voltage swing through each cycle. Therefore, timing uncertainty occurs when combined with the inevitable slew rate limit. When there is noise in the current used to charge the capacitor of the base node (determined by the upper PMOS or the lowest NMOS), the phase noise is proportionally degraded based on the noise level. The time required to generate a voltage swing from an idle state to an exchange point is inversely proportional to the slew rate.

U.S. Patent No. 5,631,580, entitled "BiCMOS ECL-to-CMOS Level Converter", hereinafter referred to as "the '580 patent", discloses another prior art solution in which there is a low level signal swing until a rail-to-rail CMOS The signal is generated. However, the performance of the disclosed circuit still does not produce the desired phase noise performance because the noise level caused by the PMOSFET (whose gate is connected to the drain) is still too high. This limits the available voltage swing and thus degrades the signal to noise ratio. Even without this limitation, when the complementary output BJT is turned off, its base is driven as far as its emitter to the power rail. This means that there is a signal swing that swings from an idle state to the switching point to hundreds of millivolts (up to 900 mV at -55 °C). Although the '580 patent has been improved over the '726 patent, the noise is still too large, and the performance of the phase noise is degraded due to current noise and the conversion rate limitation.

U.S. Patent No. 5,900,746 (Ultra Low Jitter Differential to Fullswing BiCMOS Comparator with equal rise/fall time and Complementary Outputs, hereinafter referred to as '746 patent), by using a virtual inverter The input of the first CMOS gate is maintained at a static level close to one of the switching thresholds, and the dynamic driving signal is a low level signal from the BJT differential pair. Therefore, the first node having a significant voltage change to be converted is the first rail-to-rail CMOS signal. However, the signal driving the gate of the first MOSFET is essentially a current drive signal. Therefore, the edge conversion rate is determined by the quiescent current level in the driver circuit and the capacitance seen from the MOSFET gate of the inverter. These capacitors include gate-to-source capacitance, gate-to-bulk capacitance, and gate-to-drain capacitance. Therefore, the gate-to-drain capacitance is amplified several times due to the well-known Miller effect, which increases the effective capacitance due to the opposite thin plate connected to the drain. That is, the inverter output has a large opposite voltage swing.

Driving the gate with this current source may produce acceptable speeds, but due to the noise present on the current source, the noise often does not perform well. An on-chip current source is typically generated with conventional reference bandgap types to provide a current that is substantially unaffected by supply voltage and temperature, or a current that is proportional to absolute temperature. Although the circuit disclosed in the '746 patent provides certain desirable characteristics in some cases, the dynamic range of the current source based on the reference bandgap is defined as the quiescent current separated by the current noise leveling region. Levels often cause limitations and do not achieve the most needed phase noise performance.

Another prior art circuit is disclosed in U.S. Patent No. 6,008,667, entitled "Emitter-Coupled Logic to CMOS Logic Converter and method of operation" (hereinafter referred to as "the '667" patent). In the circuit described in the '667 patent, the gates of the NMOS and PMOS transistors that generate the first rail-to-rail CMOS signal are independently driven by a small voltage swing, which is followed by each individual MOSFET. The Vgs are limited to swing at the center. This improves the speed of a particular level of quiescent current drain, which is obtained by measuring both the transfer delay and the slew rate of the gate drive signal. One of the sources of noise for the inverter MOSFET is the input reference voltage noise. Therefore, the faster the conversion rate (volts per second), the less the voltage noise is converted into phase noise.

However, the circuit disclosed in the '667 patent also has two drawbacks, which are also present in other prior art circuits. The first drawback is that the gate drive signal is still limited by the quiescent current of the stage. The MOSFET whose gate is connected to the drain at the gate of the inverter attempts to reduce the impedance, making the driver more similar to a voltage source. Therefore, such a MOSFET, as a passive component, does not increase the current available to drive the inverter gate terminal. The second disadvantage is that the gates of these MOSFETs are connected to the drain and limit the signal-to-noise ratio itself, as described above.

The circuit disclosed in U.S. Patent No. 7,345,528 (hereinafter referred to as "the '528 patent") uses a common node to drive the gate of the first inverter, which maintains an appropriate intermediate level at the power supply level ( See also the circuit disclosed in the '746 patent. In the '528 patent, the driver circuit includes complementary differential BJT pairs to improve the signal to noise ratio at a particular quiescent current level. The circuit disclosed in the '528 patent uses a signal to drive an inverter input having a high impedance, but improves the signal-to-noise ratio by varying the current slots and current sources driving the nodes, and the amplitude is improved by a factor of two. In addition, the '528 patent discloses a bipolar pinch circuit that limits the voltage swing at the input of the inverter, which improves phase noise performance as previously described.

Figure 1 (Prior Art) illustrates another prior art circuit for driving the gate terminals of a pair of P-MOSFETs (150 and 155) by a conventional ECL logic gate (including transistors 115 and 120). When the circuit is fabricated in an integrated circuit process and the Vbe level of an NPN transistor and the critical level Vgs of a PMOS transistor (150 and 155) are properly controlled, the circuit can be used in accordance with the art. The technology is fabricated with appropriate voltage swing settings at various operating temperatures to perform the correct function. The input to this circuit is the ECL logic signal, and its output is used to generate CMOS logic signals, as explained further below.

The digital logic circuit shown in Figure 1 has only two static, two static transitions (hopefully) can be performed in a fast dynamic manner. When the input state changes, one of the two PMOS devices (eg, 150) is turned off by the NPN emitter follower (eg, 130) connected to its gate. This usually occurs fairly quickly with small noise, because the NPN emitter follower (eg, 130) acts as a voltage source that increases the node's current gain and increases with its base extremes. The current required. However, in the other half of the circuit, the other PMOS devices (eg, 155) will turn on, but this will not happen so quickly because the emitter follower (eg, 135) will turn off (fall to zero emitter current) ), unless the static bias current (145) of the emitter follower is set at a very high level. As mentioned earlier, the capacitance seen from the gate of the MOSFET includes the gate-to-source capacitance, the gate-to-body capacitance, and the gate-to-drain capacitance, where the gate-to-drain capacitance is multiplied by the well-known Miller effect. Times.

At ECL logic gates capable of producing such multiples of capacitance and fast slew rate, a large amount of quiescent current is required to cause the NPN emitter follower (e.g., 135) to be actively biased during the falling edge of the signal. This large bias level will result in all undesirable results, including increased supply rail power consumption and increased heat generation on the wafer. This also increases the noise of the circuit because the NPN base current noise acts on the pull-up resistor R4 (110), which is much larger than the reciprocal of the mutual conductance (gm). That is, the voltage noise level of the base terminal is not determined by the general voltage noise term, but by the multiplication of the current noise and the value of the pull-up resistor.

At a typical quiescent current level, the noise is maintained at an acceptable level on the edge of the signal used to turn off the PMOS device. However, time-based noise is primarily determined by the noise used to turn on the current source on the edge of the signal of the PMOS device.

Another solution of the prior art of Figure 1 is to change transistors Q5 and Q6 to N-channel MOSFETs. These source followers are identical to the aforementioned emitter followers, both of which are functionally a class of voltage followers. The use of NMOS introduces problems associated with Vgs _(on) variability, especially due to the subject effect such that Vgs _(on) will vary with the subject voltage. However, the main noise term when using the emitter follower - the base current pulse noise - will disappear due to the fractional level of the gate current noise of the MOSFET. Therefore, in the case of using an NMOS type voltage follower, it is possible to increase the current from I2 and I3, but it does not generate a noise load as large as the NPN type voltage follower.

Figure 2 (Prior Art) illustrates prior art means 200 for generating conventional CMOS logic signals for use in the circuit shown in Figure 1. In circuit 200, anti-parallel CMOS inverters 230 and 240 are disposed on the drains of PMOS transistors 210 and 220 to form a latch that cooperates with circuit 100 of FIG. 1 between two logic states. Set and reset. This is suitable for implementation in CMOS processes including NPN BJT rather than PNP BJT. However, circuit 200 will result in a slight skew of the duty cycle at the two outputs. One of the PMOS devices 210 and 220 generally has a faster turn-off speed than its corresponding PMOS turn-on speed, as previously described with reference to FIG. This is desirable in terms of the competition in the circuit 200 shown in Fig. 2. However, since the rising edge of each output is actively pulled up by the PMOS device and the falling edge is behind about one inverter delay time, the skew occurs at the output. As a result, the duty cycle of the two outputs shown in Figure 2 will be skewed, so the high energy state in one cycle will be slightly longer than the low energy state compared to the ECL output.

Figure 3 (Prior Art) illustrates a fully differential and complementary implementation 300 of circuit 100 of Figure 1. A complementary circuit is well known to those skilled in the art, and wherein a second circuit is mirrored. The polarity of all BJTs is flipped from NPN to PNP, and vice versa; and the polarity of all MOSFETs is flipped from PMOS to NMOS and vice versa. In general, in the mirror relationship between the two supply rails with the neutral point as the standard, the signal and the bias voltage will be equal in size, but will have opposite polarities. Circuit 300 can be implemented only in a process that includes NPN, PNP BJT, and CMOS devices. Such processes are required for making complementary circuits and are commonly used in high speed, low noise circuits. In FIG. 3, input transistors 310 and 315 are coupled to two PNP voltage followers 360 and 375 which further drive the gate terminals of the two N-MOSFET transistors 385 and 390. In addition, the complementary side includes two input transistors 320 and 325 that are coupled to two NPN voltage followers 345 and 365 that drive the gate terminals of the two P-MOSFET transistors 377 and 380.

Four voltage followers (345, 365, 360, and 375) drive four MOSFETs (377, 380, 385, and 390) to produce a first CMOS rail-to-rail logic signal at the output. The latch circuit need not be similar to the circuit 200 shown in FIG. Since circuit 300 is merely a complementary version of Figure 1, it has the same characteristics and disadvantages in driving the MOSFET gate. That is, the emitter follower acts as a voltage source and the gate is quickly driven to the off state. There is a current limit when the gate is driven to the on state, so the speed will be driven slower to the on state and also subject to more noise, unless the quiescent current source is greatly increased. In this case, the noise level rises anyway due to base current noise, which causes noise on the base node through the resistor.

Although an alternative to FIG. 3 may be to change four BJT voltage follower devices (345, 365, 360, and 375) to their corresponding polarity MOSFETs, this may result in a DC level that is fairly easy to change because Vgs _(on) will vary with the subject voltage and additional noise (such as 1/f variability).

Therefore, the circuit shown in Figure 3 requires a modified version that does not increase the bias current level of the voltage follower regardless of the particular transistor set used to implement the voltage follower.

An aspect of the present invention provides an apparatus for a CMOS clock driver, comprising: a first input receiving circuit for receiving a small signal logic input; and a first voltage follower circuit coupled to the a first input receiving circuit for generating a first set of voltage follower outputs; and a first output circuit coupled to the first voltage follower circuit for receiving the first set of voltages The output of the follower is input, and an output signal is generated, wherein the first voltage follower circuit is coupled to a first switching circuit, and the first switching circuit is coupled to the first set of voltage follower outputs. And configured to reduce the phase noise level of the output signals.

Another aspect of the present invention provides an apparatus for a clock driver, comprising: an input receiving circuit for receiving a small signal logic input; and a voltage follower circuit coupled to the input receiving circuit to For generating a plurality of voltage follower outputs; and an output circuit coupled to the voltage follower circuit for receiving the plurality of voltage follower outputs as an input and generating an output signal, wherein the output signal is generated The voltage follower circuit is coupled to a switching circuit, and the switching circuit is coupled to the plurality of voltage follower outputs and configured to reduce phase noise levels of the output signals.

The present invention is generally directed to a clock driver circuit. More specifically, the present invention relates to a BiCMOS clock driver circuit that improves the phase noise performance of a clock driver.

The present invention discloses a circuit suitable for use as a clock driver having reduced phase noise compared to each of the prior art circuits described above. An improvement is achieved at the interface between the double-numbered sub- (ECL) portion and the CMOS portion by actively driving the first MOSFET gate up or down. In some embodiments, a direction is driven by a BJT emitter follower, and the other direction is driven by using a MOSFET switch to push the charge stored in the dummy MOSFET gate. It will be appreciated that other specific embodiments within the scope of the scope of the patent application are also possible.

FIG. 4 shows an exemplary embodiment of a fully differential and complementary circuit 400 that drives a set of MOSFET gate terminals by a conventional ECL logic gate. Circuit 400 includes an additional MOSFET at the output of each of the four emitter followers 427, 430, 440, and 443 as compared to circuit 300 shown in FIG. Block 470 includes newly added MOSFETs, namely transistors N5, N6, P3, and P4 (which are a set of transistors connected to emitter followers 427 and 430) and P5, P6, N3, and N4 (connected to the shot). Polar followers 440 and 443).

The newly added transistor is constructed as follows. The transistor N5 is an NMOS device having a source connected to a current source I2 and a drain connected to the emitter of the transistor 427 (Q5). The transistor N6 is an NMOS device having a source connected to the current source I3 and a drain connected to the emitter of the transistor 430 (Q6). The gate of transistor N5 is connected to the drain of transistor N6, and the gate of transistor N6 is connected to the drain of transistor N5. This is an important feature of the invention. As disclosed, with this configuration, transistors N5 and N6 are constructed as switches or so-called switch MOSFETs.

Another important feature of the present invention relates to the capacitance placed at the source of each of transistors N5 and N6. As shown in FIG. 4, a device designated P3 is a PMOS transistor having a drain and a source connected to the positive supply rail and a gate connected to the source of the transistor N5. Similarly, for transistor N6, a device designated P4 is a PMOS transistor having its drain and source connected to the positive supply rail and its gate connected to the source of transistor N6. The desired function of devices P3 and P4 acts as a capacitor for each of them, i.e., a charge reservoir. The connection shown in Figure 4 causes virtual devices P3 and P4 to operate as capacitors.

As for the complementary portion of the circuit shown in Fig. 4, the transistor P5 is a PMOS device having a source connected to a current source I4 and a drain connected to the emitter of the transistor 440 (Q7). The transistor P6 is a PMOS device having a source connected to a current source I5 and a drain connected to the emitter of the transistor 443 (Q8). Similarly, the gate of transistor P5 is connected to the drain of transistor P6, and the gate of transistor P6 is connected to the drain of transistor P5. In this exemplary embodiment, there are four switcher MOSFETs labeled N5, N6, P5, and P6, respectively. The transistors P5 and P6 are combined to act as a switch MOSFET, as will be further explained below. The same applies to the complementary portions of circuit 400. For each of transistors P5 and P6 in switching circuit 470, a capacitor is disposed at the source of each of the switch MOSFETs. As shown in FIG. 4, the device N3 is an NMOS transistor whose drain and source are connected to the negative supply rail and the gate is connected to the source of the transistor P5. The device N4 is an NMOS transistor having a drain and a source connected to the negative supply rail and a gate connected to the source of the transistor P6. Each of the transistors N3 and N4 functions as a capacitor, that is, a charge reservoir. Using the circuit configuration shown in Figure 4, N3 and N4 can achieve such a desired function.

As shown in Figure 4, circuit 400 can be adapted to operate as a logic translator; however, since the input is static and equal in voltage at the output transistor pair (transistor pair 445/455 (N1/P1) and transistor pair 450/ A shoot through is generated in 460 (N2/P2), so in some embodiments, a latch or hysteresis stage (not shown) can be configured prior to the input shown in Figure 4 to ensure These inputs are either at the ECL logic level or at the logic level.

When the input voltage of the bases of transistors 402 and 410 (Q1 and Q3) is higher than the static input voltage of the bases of transistors 405 and 412 (Q2 and Q4), the current from current source 415 (I1) is The flow is directed through transistor 410 (Q1) to resistor 420 (R3). Current from current source 407 (I0) is directed through transistor 405 (Q4) to resistor 437 (R2). Since no current flows through resistor 425 (R4), the gate voltage of PMOS P2 is pulled up by the NPN emitter follower 430 (Q6) toward the positive supply rail, and the gate voltage of the NMOS transistor N5 is also pulled up. The current from current source I2 thus flows through transistor N5, pulling the gate voltage of PMOS transistor 445 (P1) down until the NPN emitter follower 427 (Q5) is turned on. Since current flows through resistor 420 (R3), Q5 will not conduct until the gate-to-source voltage of transistor 445 (P1) is substantially greater than a threshold Vgs, and thus the performance of device P1 is fully enhanced.

When the circuit is still static, the gate voltage of the transistor N6 is lower than the voltage value of the positive supply rail, and the voltage value is I*R (the value of the resistor 420 (R3)) plus the transistor 427 (Q5). The Vbe value. Maintaining this state for an appropriate period of time, current source I3 pulls the gate voltage of P4 (a capacitive connection device) low enough that transistor N6 then reloads the current from current source I3. However, this is not an operational requirement for the circuit and will be further explained below.

In the corresponding circuit of the lower half of the circuit 400, when no current flows through the resistor 435 (R1), the gate voltage of the NMOS transistor 455 (N1) is negatively biased by the PNP emitter follower transistor 440 (Q7). When the power rail is pulled down, the gate voltage of the PMOS transistor P6 is also pulled down. The current from current source I5 is thus pushed through transistor P6, pulling up the gate voltage of NMOS transistor 460 (N2) until PNP emitter is turned on with 442 (Q8). Since current flows through resistor 437 (R2), Q8 will not conduct until the gate-to-source voltage of transistor 460 (N2) is substantially greater than a threshold Vgs, and thus the performance of device N2 is fully enhanced.

When the circuit is still in this static state, the gate voltage of the transistor P5 is higher than the voltage drop of the negative supply rail group, and the voltage drop is measured as I*R (the value of the resistor 437 (R2)) plus the transistor 443. The Vbe value of (Q8). Maintaining this state for a suitable period of time, current source I4 pulls up the gate voltage of transistor N3 (a capacitive connection device) high enough that transistor P5 re-bears the current from current source I4. Again, this is not an operational requirement for the circuit, as explained further below.

The improvements achieved by circuit 400 are best represented by the transition between logic states. Since circuit 400 is fully differential, the various descriptions described above with respect to a static logic are reversed for the opposite static logic. Likewise, the functions described below are directed to the transition from the above state to an opposite state. Describe the opposite situation and reflect the situation associated with transitioning to the above static.

At a transition, when the input voltage to the bases of transistors 410 (Q1) and 402 (Q3) drops below the input voltage of the bases of transistors 412 (Q2) and 405 (Q4), current source 407 The currents of (I0) and 415 (I1) are directed to another relative resistance on the collector of the respective differential pair. The circuit function that reacts to the base inputs of the four BJT emitter followers (transistors 427, 430, 440, and 443) is the same as that described with reference to circuit 300 shown in FIG.

Due to the current drop at the collector of transistor 410 (Q1), resistor 420 (R3) pulls the base voltage of transistor 427 (Q5) up to the positive supply rail. Since transistor 427 (Q5) is an emitter follower transistor, it directly pulls up the gate terminal of transistor 445 (P1) and quickly turns it off, as described with reference to Figure 3. However, transistor 427 (Q5) also pulls the gate voltage of transistor N6 in circuit 400. Since the transistor P4 (capacitor connection device) is charged to a voltage much larger than the threshold Vgs, the transistor N6 is turned on, and operates as a switch to connect the gates of the PMOS devices P4 and P2 to actively pull down The gate voltage of the output device 450 (P2). Since the input signal (via the transistors Q1-R3-Q5-N6) is actively driven, the time-based noise is independent of the noise of the current source I3.

In a corresponding portion of the circuit of the differential circuit 400, current from the current source 415 (I1) is pulled by the transistor 412 (Q2) and flows through the resistor 425 (R4), thus pulling down the emitter follower transistor 430 (Q6) Base voltage. As described above with reference to Fig. 3, it is not possible to ensure that the gate voltage of the transistor 450 (P2) is actively pulled low. However, in circuit 400, the gate voltage of transistor 450 (P2) is pulled low quickly due to the operation of the N6 switch described herein. Since the gate of the transistor 450 is at a low voltage, the transistor N5 is turned off because the capacitor is connected to the P3 device so that the source terminal of the transistor N5 is not immediately pulled down by the current source I2. When the gate of transistor P3 is pulled down sufficiently low, transistor N5 then begins to conduct current. The exact time at which this occurs will vary due to noise from current source I2 (time-related noise). However, this noise from current source I2 does not affect the output, so the phase noise performance of the signal path is not degraded by the noise of the current source.

Moreover, for the lower half of circuit 400, transistor 437 (R2) pulls the base voltage of transistor 443 (Q8) to a negative supply due to the current drop from the collector of transistor 405 (Q4). rail. The transistor 443 (Q8) is also an emitter follower, which in turn directly pulls down the gate voltage of the transistor 460 (N2). This allows the transistor 460 to be quickly turned off, as described herein with reference to Figure 3. However, in circuit 400, transistor 443 (Q8) also pulls down the gate voltage of P5. Because the capacitor connection device N3 is charged to a voltage much higher than the threshold Vgs compared to the gate voltage of P5, the transistor P5 is turned on, and operates as a switch to connect the gate terminals of the NMOS devices N3 and N1. stand up. In this manner, circuit 400 actively pulls up the gate voltage of output device N1. In addition, since the gate of N1 is actively driven by the input signal (via Q4-R2-Q8-P5), the time-based noise is independent of the noise of current source I4.

As for the operation of the other portions of the lower half of the circuit 400, the current of the current source 407 (I0) is redirected by the transistor 402 (Q3) and flows through the resistor 435 (R1), so the pull-up emitter follows the coupling transistor 440 (Q7). The base voltage of ). As explained for the circuit 300 shown in FIG. 3, this does not ensure that the gate voltage of the transistor 455 (N1) is actively pulled high. However, in circuit 400, the gate voltage of transistor 455 (N1) is rapidly pulled high due to the associated switch operation of transistor P5 described herein. Since the gate voltage of the transistor 455 is at a higher voltage, the transistor P6 is turned off because the capacitor connection device N4 causes the source terminal of the transistor P6 to not be immediately pulled up by the current source I5. In this manner, transistor P6 re-conducts current only when the gate of transistor N4 is pulled high enough. The exact point in time at which this occurs will vary due to noise from current source I5. However, such noise does not affect the output, so the phase noise performance of the signal path is not degraded by the noise of the current source.

As with the operation of circuit 400 disclosed herein, the conversion has a gate voltage of both output devices 455 (N1) and 445 (P1) that are actively pulled high, and a common connection between N1 and P1 that are actively pulled low. Bungee, which has the smallest added phase noise. In addition, the gate voltages of both output devices 460 (N2) and 450 (P2) are actively pulled low, and their shared connection drains are actively pulled high with minimal added phase noise.

In some embodiments of the invention, the capacitors used are implemented as capacitor-connected MOSFETs, as shown in Figure 4, the polarity of the MOSFET can be selected to match the type of device actively connected by the capacitor. For example, device P3 is a PMOS device that can be selected to match PMOS device P1. Similarly, device P4 is a PMOS type that matches PMOS device P2. This makes it easier to size the capacitance ratio between the two, while also tracking the variation due to temperature and wafer processing more effectively. However, other configurations are also possible. For example, the capacitors used can also be fabricated using different construction methods, such as a parallel plate capacitor or a diode-connected MOSFET with opposite polarity.

In some embodiments of the invention, a capacitively connected MOSFET whose capacitance value is greater than the capacitance of the output device can be selected for a variety of reasons. For example, the gate-to-dip capacitance value of an output device is multiplied by the Miller effect, and the capacitive connection device does not experience such a Miller effect. In another example, the gates of both the output MOSFET and the capacitor-connected MOSFET can each swing with the same voltage change during the entire signal period. Therefore, in the case where the capacitance values of the two are made equal, when the MOSFET switch between the two capacitors is turned off, the charge redistribution is caused to cause the two capacitance values to undergo a voltage change, and the voltage change is the swing. half. Since the threshold Vgs of the output device is generally similar but not exactly at a half-way point, it is desirable to be able to drive the output device gate terminal beyond the midway point within the range of charge redistribution. This can be achieved by a large capacitive connection device.

A large capacitive connection device may have some related problems. For example, recharging after an inactive transition typically takes a long time. The quiescent current required for the same charging time may increase. For example, if the capacitance value of a capacitor connection device is not more than 50% larger or larger than the capacitance value of the output device, the circuit shown in FIG. 3 maintains the same conversion speed and still maintains an improved phase noise. The current required, the extra current drawn is small.

Another related feature of circuit 400 is illustrated below. The voltage swing across the resistor, plus the Vbe value of the emitter follower, plus the Vgs value of the switch MOSFET, is close to a voltage value equal to or exceeding the total supply voltage. For example, when circuit 400 is operable to operate on a 5V supply, it is also suitable for operation with a 3.3V supply voltage. Under the industry standard 10% tolerance, the supplied voltage can be as low as 3V. With a 800mVp-p swing at the resistor and a Vbe with an emitter follower of 800mV, more than half of the supply voltage can be consumed.

The switch MOSFET can operate in a manner that the source is remote from the rail (the body is typically coupled to the rail). This will increase the threshold voltage Vgs unless the body can float to the source terminal in parallel. In some instances, this is not necessarily possible, and in some cases this may be a situation that does not want to happen. In the worst case of the temperature at which the BJT Vbe is 900mV and the MOSFET Vgs may be 1.2V, the total voltage from the rail straddles 2.9V, leaving only 100mV of headroom for the current source I2-I5. In the presence of a ground bounce or other dynamic wobble, this grace may completely disappear.

The above problem, if any, is not fatal for circuit 400 for the following reasons. A current source can be a benign drop when it meets a deficiency in the compliance headroom (e.g., a current source implemented with a MOSFET output device) that is generally acceptable in circuit 400. Although the capacitor-connected MOSFET can stop charging, at the moment the charging is stopped, the capacitor-connected MOSFET may already have most of the required voltage change, so most of the required charge has been stored. In this case, there is no need to cause the switch MOSFET to conduct current. This eliminates the bias of the emitter follower on its drain because the emitter follower discharges the Cgs of the output MOSFET during switching and can have a sufficient amount of bias current to pull the charge out.

After the conversion is complete, the emitter of the Q5-Q8 can simply remain idle without negative side effects. If there is leakage current at a node, the voltage may drift, causing abnormal behavior or limiting the minimum frequency of operation. If this is not acceptable in a particular application, a small current source can be added to solve the problem. The added current source can be set to one tenth of the value of the current source I2-I5 or less than the value of the current source I2-I5 to be able to independently provide a minimum bias level to each emitter follower. Because the emitter of Q5-Q8 is on the other side of the switch MOSFET compared to the I2-I5 connection, it typically has a large margin for such small additional current sources.

In the exemplary embodiment shown in FIG. 4, the capacitive connection MOSFET is connected to a supply voltage for use in an individual half circuit. It should be appreciated that this configuration is not necessary and the present invention can be implemented to connect such capacitors to any static or quasi-static node. As is well known in the art, CMOS circuitry causes large current spikes from the voltage supply rail during the transition, thus causing a substantial voltage "bounce" on the power supply. An example configuration of circuitry 400 is somewhat immune to this situation.

Incorporating the switch MOSFETs N5, N6, P5, and P6, the efficiency of the circuit 400 can be improved by the full speed of the turn-on speeds of the MOSFETs N1, N2, P1, and P2, making it more efficient than the circuit 300. In general, they are not responsible for turning off MOSFETs N1, N2, P1, and P2, while the emitters in circuit 400 follow the couplers Q5, Q6, Q7, and Q8 to turn them off quickly. The switch MOSFETs cause a surge in current from the corresponding capacitor-connected MOSFET at the appropriate time in a critical transition (ie, where a particular switch MOSFET is turning on its associated MOSFET N1, N2, P1, or P2 transition). The switch MOSFET is not critical during other conversions. Switcher MOSFETs N5 and P6 are critical during the switching of turn-on devices P1 and N2. Switcher MOSFETs N6 and P5 are critical during the switching of turn-on devices P2 and N1.

It is noted that the design criteria for the switch MOSFET transistors N5, N6, P5, and P6 can be significantly different than the other MOSFETs shown in circuit 400. Each switch MOSFET is driven as a switch during critical transitions and is turned off during other transitions, with active linear operation only during idle time. In these cases, the noise of this switch MOSFET at any location is not as important as the noise of the output MOSFET or BJT transistor. Thus, when the output devices (eg, P1, P2, N1, and N2) need to be designed to have the least possible noise, the switch MOSFET can be optimized based on other criteria such as switching speed or channel resistance.

In order to fully utilize the advantages of the present invention, the circuit 400 shown in FIG. 4 can be driven with an input that can be converted as quickly as possible. As mentioned earlier, when this feature is applicable for other reasons, a pre-stage with a latch or hysteresis may be sufficient to ensure that the conversion can occur quickly.

Compared to the conventional circuit 300 shown in FIG. 3, the circuit 400 shown in FIG. 4 is also advantageous in physical implementation. The output impedance of current source I2-I5 (350, 367, 352, and 370) in Figure 3, which is typically controlled by the output capacitor for high speed circuit design, directly affects the phase noise performance of circuit 300. This is because these current sources in Figure 3 reduce the skew rate of the output gate drive node. However, in accordance with the present invention, the four current sources I2-I5 as shown in Figure 4 have a capacitor connected thereto and which is part of the improvement described herein. With this circuit configuration, the output capacitance of the current source is less important, and the output capacitance of the current source I2-I5 in Figure 4 can actually help improve phase noise performance.

In the exemplary implementation shown in FIG. 4, the values of similar circuit components can generally be made the same or similar. For example, R3 = R4 = R1 = R2, I0 = I1, and I2 = I3 = I4 = I5. Further, for differential symmetry, I2 = I3, I4 = I5, R3 = R4, and R1 = R2. However, it should be appreciated that no other consistency or similarity is required in the exemplary embodiments. For example, in a program where the NPN speed is much faster than the PNP speed, the relationship between the skew current source I2-I5 and the resistance for the upper half circuits (420 and 425) with respect to the lower half circuits (435 and 437). It is advantageous. Another reason for performing this skew may be that there is an extremely unbalanced state of the NMOS to PMOS threshold Vgs, in which case the desired product I1 × R3 may be skewed relative to the product I0 × R1. This design change is all within the scope of the invention. The preferred skew of the channel length and width of the output MOSFET device can be established based on the difference in NMOS and PMOS noise performance. That is, the NMOS and PMOS devices N1, N2, and P1, P2 require different geometries (length, width) such that the noise levels of the two pairs of devices are comparable.

Figure 5 shows an embodiment of a fully differential and complementary circuit for driving a set of MOSFET gates by conventional ECL logic to generate standard LVDS logic signals in accordance with an embodiment of the present invention. This circuit produces a low voltage differential signaling (LVDS) output with phase noise improvement as shown in FIG.

LVDS is defined by the TIA/EIA-644-A standard and generally requires more circuitry than the circuit shown in Figure 5, such as actively controlling at least a 3.5 mA current source to ensure output offset voltage (defined in the standard). Meet the specifications 4.1.2. The circuitry used to perform this function and other items necessary for compliance may be of conventional construction while still achieving phase noise improvement in FIG.

The LVDS signal is generated by directing a 3.5 mA current source to operate the N-channel MOSFET through N9 and N12 or by manipulating the N-channel MOSFET through N10 and N11. When a 100 ohm differential terminal is incorporated at the LVDS receiver, a differential voltage of 350 mV can be generated in this manner. In order to turn on the NMOS devices N9 and N12, their gate nodes (which are connected to the drains of P1 and N7) must be pulled high. In order to turn on the NMOS devices N10 and N11, their gate nodes (which are connected to the drains of P2 and N8) must be pulled high.

The operation of Figure 5 is identical to the operation of the four MOSFETs labeled N1, N2, P1, and P2 on Figure 4. The circuit in Figure 4 can be used to drive the MOSFETs N5-N8 to generate LVDS signals. However, during the transition, there is a brief instant when only devices N11 and N12 are turned on and N9 and N10 are not turned on. When only N11 and N12 are turned on, the low 3.5mA current sink can dynamically pull down the output line, which may make it difficult to meet the LVDS standard specification 4.1.5 - Dynamic Output Signal Balance.

The N7 and N8 NMOS devices are added to the drains of N1 and N2, respectively, to change the dynamic behavior when the LVDS signal is generated. Specifically, the pole of P1 rises from the low level to the high level, so the pole of P2 drops from the high level to the low level. Once the voltage follower Q5 and the switch MOSFET N5 pull the gate of P1 low. Then, the bungee of P1 will rise. However, unlike Figure 4, once the voltage follower Q8 and the switch MOSFET P6 pull up the gate of N2, the drain of P2 is pulled low. In addition, the drain voltage of P1 must be raised enough to turn on the cross-coupling device N8. At this point, the N2's bungee can pull down the P2's bungee.

The dynamic output signal balance is improved by providing a steering NMOS device N9-N12 having a gate drive signal that is delayed at the falling edge (rather than at the rising edge). When the rising speed of the pole of P1 is faster than the falling speed of the pole of P2, the length of time for N9 and N10 to be turned off is greatly shortened or substantially zero.

Figure 6 shows a different embodiment of a fully differential and complementary circuit in accordance with an embodiment of the present invention for driving a set of MOSFET gate terminals by conventional ECL logic to generate standard LVDS logic signals. In circuit 600, the output portion for switching from the CMOS driver provided by N1, N2, P1, and P2 to an LVDS output is replaced by the image shown in FIG.

The control MOSFET in Figure 6 is now PMOS devices P9 to P12, and the dynamic output signal balance can be degraded to the extent that devices P11 and P12 will be turned off and device P9 or P10 will be turned on. Figure 6 uses the same functional approach as the circuit 500 of Figure 5 to reduce this degradation by achieving a change in the edge of the gate drive signal. In this example, as with the drains of N1 and N2, the cross-coupling devices P7 and P8 delay the rising edge of the signal rather than the falling edge.

In some cases, circuit 600 shown in Figure 6 may encounter some problems. For example, a low level output under the TIA/EIA-644-A standard may be 1V less than the ground point, and is not sufficient to fully enhance the performance of the controls P11 and P12. In general, a well may be required to avoid a bulk effect. However, a device that is supplied with a 1.8V power supply can more easily solve this problem than the driving devices N9 and N10 in Fig. 5.

There are a variety of implementations to implement the invention. For example, the upper half of the P1 and P2 driver circuits in Figures 4-6 can be used in conjunction with the output connections of Figure 2 to provide improved phase noise bits compared to the circuit of Figure 1. A quasi-circuit. Although the input differential transistor pairs 402, 410, 405, and 412 (Q1 and Q4) are shown as BJTs, they can also be implemented using MOSFETs. To conserve power, the I2-I5 current source shown in Figures 4-6 can be dynamically changed depending on the operating frequency of the circuit. Alternatively, a non-linear current source can be used which can be reduced to a lower idle value once the capacitor-connected MOSFET is fully charged.

The voltage follower can also be changed from a BJT emitter follower to a MOSFET or even a JFET source follower. The polarity of the PNP/P-FET is unchanged for the NPN/N-FET, and the voltage connected to the circuit does not change with the coupler connection. As is well known in the art, some small changes to the bias level are required due to the different Vbe and Vgs _(on) levels. To perform this replacement, the voltage follower input is changed from a BJT base to a FET gate, the output is changed from a BJT emitter to a FET source, and the power supply is changed from a BJT collector to a FET drain. .

The illustrated implementation has an input that is compatible with ECL (emitter-coupled logic). In recent years, CML (current-mode logci) has proliferated. Those skilled in the art will appreciate that alternatives may be employed that omit the differential pair at the input and feed the differential current to resistors R1 through R4. Of course, it should be possible to adapt the input receiving circuit to accept any small signal logic input signal by using appropriate level conversion and impedance changes as necessary.

Figures 4-6 include current sources well known to those skilled in the art, which may be implemented using BJT or MOSFETs, and in some instances may even be implemented using only resistors.

The invention has been described with reference to certain specific exemplary embodiments, which are to be construed as a The invention may be modified within the scope of the appended claims without departing from the scope or spirit of the invention. Although the present invention has been described with reference to the specific structures, acts and materials, the present invention is not limited to the specific features disclosed, but may be practiced in various forms, some of which may be equivalent to the embodiments disclosed herein. The scope of the present invention extends to all equal results, actions, and materials as are included within the scope of the appended claims.

100. . . Circuit

105. . . resistance

110. . . resistance

115. . . Transistor

120. . . Transistor

125. . . Bias current

130. . . Emitter follower

135. . . Emitter follower

140. . . Bias current

145. . . Bias current

150. . . PMOS

155. . . PMOSFET

200. . . Circuit

210. . . PMOSFET

220. . . PMOSFET

230. . . CMOS inverter

240. . . CMOS inverter

300. . . Circuit

305. . . Bias current

310. . . Input transistor

315. . . Input transistor

320. . . Input transistor

325. . . Input transistor

330. . . Bias current

335. . . resistance

340. . . resistance

345. . . Voltage follower

350. . . Battery

352. . . Battery

355. . . resistance

357. . . resistance

360. . . Voltage follower

365. . . Voltage follower

367. . . Battery

370. . . Battery

375. . . Voltage follower

377. . . PMOSFET

380. . . PMOSFET

385. . . NMOSFET

390. . . NMOSFET

400. . . Fully differential and complementary circuits

402. . . Transistor

405. . . Transistor

407. . . Battery

410. . . Transistor

412. . . Transistor

415. . . Battery

420. . . resistance

425. . . resistance

427. . . Emitter follower

430. . . Emitter follower

435. . . resistance

437. . . resistance

440. . . Emitter follower

443. . . Emitter follower

445. . . PMOSFET

450. . . PMOSFET

455. . . NMOSFET

460. . . NMOSFET

470. . . Switching circuit

500. . . Circuit

502. . . Transistor

505. . . Transistor

507. . . Battery

510. . . Transistor

512. . . Transistor

515. . . Battery

520. . . resistance

525. . . resistance

527. . . Emitter follower

530. . . Emitter follower

535. . . resistance

537. . . resistance

540. . . Emitter follower

543. . . Emitter follower

545. . . PMOSFET

550. . . PMOSFET

555. . . NMOSFET

560. . . NMOSFET

570. . . Switching circuit

600. . . Circuit

602. . . Transistor

605. . . Transistor

607. . . Battery

610. . . Transistor

612. . . Transistor

615. . . Battery

620. . . resistance

625. . . resistance

627. . . Emitter follower

630. . . Emitter follower

635. . . resistance

637. . . resistance

640. . . Emitter follower

643. . . Emitter follower

645. . . PMOSFET

650. . . PMOSFET

655. . . NMOSFET

660. . . NMOSFET

670. . . Switching circuit

The present invention has been described and illustrated in the foregoing, by way of example, the exemplary embodiments, In all of the figures, like element symbols represent similar structures.

Figure 1 (Prior Art) illustrates a circuit for driving a PMOS gate pair by conventional ECL logic;

Figure 2 (Prior Art) shows prior art means for generating conventional CMOS logic signals;

Figure 3 (Prior Art) shows a fully differential and complementary implementation of a circuit for driving a set of MOSFET gates by ECL logic to generate conventional CMOS logic signals;

4 shows an exemplary embodiment of a fully differential and complementary circuit in accordance with an embodiment of the present invention for driving a set of MOSFET gate terminals by conventional ECL logic to generate conventional CMOS logic signals;

Figure 5 shows an exemplary embodiment of a fully differential and complementary circuit in accordance with an embodiment of the present invention for driving a set of MOSFET gates by conventional ECL logic to generate standard LVDS logic signals;

Figure 6 shows another alternative embodiment of a fully differential and complementary circuit in accordance with an embodiment of the present invention for driving a set of MOSFET gate terminals by conventional ECL logic to produce a standard LVDS logic signal.

400. . . Fully differential and complementary circuits

402. . . Transistor

405. . . Transistor

407. . . Battery

410. . . Transistor

412. . . Transistor

415. . . Battery

420. . . resistance

425. . . resistance

427. . . Emitter follower

430. . . Emitter follower

435. . . resistance

437. . . resistance

440. . . Emitter follower

443. . . Emitter follower

445. . . PMOSFET

450. . . PMOSFET

455. . . NMOSFET

460. . . NMOSFET

470. . . Switching circuit

Claims (44)

An apparatus for a CMOS clock driver, comprising: a first input receiving circuit for receiving a small signal logic input; a first voltage follower circuit coupled to the first voltage follower circuit a first input receiving circuit for generating a first set of voltage follower outputs; a first output circuit coupled to the first voltage follower circuit for receiving the first a set of voltage follower outputs as an input, and generating an output signal; a first switching circuit, the first voltage follower circuit is coupled to the first switching circuit; and a first capacitor and a second capacitor, the first The capacitor and the second capacitor comprise a charge storage device; wherein the first switching circuit is coupled to the first set of voltage follower outputs and coupled to the first capacitor and the second capacitor, and configured to be used for Reduce the phase noise level of these output signals. The device of claim 1, wherein the output signals correspond to complementary metal oxide semiconductor (CMOS) output signals. The device of claim 1, wherein the first switching circuit comprises: a first sub-circuit coupled to the first set of voltages The first sub-circuit is coupled to a first current source; and a second sub-circuit is coupled to the first set of voltage follower outputs The second sub-circuit is coupled to a second current source; wherein the first and second sub-circuits are coupled to each other. The device of claim 3, wherein the first sub-circuit comprises: a first P-channel metal oxide semiconductor (PMOS) transistor, and a drain of the first P-channel metal oxide semiconductor (PMOS) transistor Is coupled to the first output of the first set of voltage follower outputs, and the source of the first P-channel metal oxide semiconductor (PMOS) transistor is coupled to the first current source and the first capacitor . The device of claim 4, wherein the second sub-circuit comprises: a second PMOS transistor, the drain of the second PMOS transistor being coupled to the first set of voltage follower outputs The second output, the source of the second PMOS transistor is coupled to a second current source and the second capacitor, wherein the gate of the first PMOS transistor is connected to the second PMOS transistor The drain of the second PMOS transistor is connected to the drain of the first PMOS transistor. The device of claim 5, wherein: the first capacitor corresponds to a first N-channel metal oxide semiconductor (NMOS) transistor, and the gate of the first N-channel metal oxide semiconductor (NMOS) transistor Connecting to a source of the first PMOS transistor, wherein a source terminal and a 汲 terminal of the first N-channel NMOS transistor are connected to each other; and the second capacitor corresponds to a second NMOS transistor The gate of the second NMOS transistor is connected to the source of the second PMOS transistor, and the source terminal and the 汲 terminal of the second NMOS transistor are connected to each other. The device of claim 5, wherein the first capacitor and the second terminal of the second capacitor are coupled to a negative supply rail. The device of claim 5, wherein the second voltage follower circuit comprises: a second voltage follower sub-circuit, the second voltage is coupled to the second of the input of the coupler sub-circuit a collector of the PNP transistor and a second resistor, wherein the output of the second voltage with the coupler sub-circuit is connected to the drain of the second PMOS transistor in the first switching circuit, and the second voltage follower The supply power of the sub-circuit is connected to a negative supply rail, wherein the first resistor and the second resistor are connected to a negative supply rail. The device of claim 4, wherein the first input receiving circuit comprises: a first PNP transistor having a base connected to a first input of the small signal logic inputs, and an emitter of the first PNP transistor coupled to a third current source; And a second PNP transistor, the base of the second PNP transistor is connected to a second input of the small signal logic inputs, and the emitter of the second PNP transistor is connected to the third current source And wherein the first voltage follower circuit comprises: a first voltage follower sub-circuit, the input of the first voltage follower sub-circuit is connected to the collector of the first PNP transistor and a first a resistor, the output of the first voltage-synchronizing sub-circuit is connected to a drain of the first PMOS transistor in the first switching circuit, and the first voltage is connected to a negative power supply of the coupler sub-circuit Power rail. The device of claim 9, wherein the first output circuit comprises: a third NMOS transistor, the gate of the third NMOS transistor being connected to the output of the first voltage follower sub-circuit The source of the third NMOS transistor is connected to a negative supply rail, and the drain of the third NMOS transistor is connected to receive a first output signal of the output signals; and a fourth NMOS transistor The gate of the fourth NMOS transistor is connected to the output of the second voltage follower sub-circuit, the source of the fourth NMOS transistor is connected to a negative supply rail, and the fourth NMOS transistor is The bungee is connected to receive a second output signal of one of the output signals. The device of claim 1, wherein the small signal logic inputs are emitter coupled logic (ECL) inputs. The device of claim 1, wherein the first input receiving circuit comprises: a first PNP transistor, wherein a base of the first PNP transistor is connected to one of the small signal logic inputs. Input, and the emitter of the first PNP transistor is connected to a third current source; and a second PNP transistor, the base of the second PNP transistor is connected to one of the small signal logic inputs Two inputs, and an emitter of the second PNP transistor is coupled to the third current source. The device of claim 12, wherein an implementation of the third current source comprises at least one of: a double carrier junction transistor (BJT); and a MOS field effect transistor (MOSFET) ); a resistor; and any combination of the above. The device of claim 1, further comprising a complementary circuit comprising: a second input receiving circuit for receiving the small signal logic inputs; a second voltage follower circuit, the second a voltage follower circuit coupled to the second input receiving circuit for generating a second set of voltage followers An output circuit, the second output circuit is coupled to the second voltage follower circuit for receiving the second set of voltage follower outputs as an input, and generating the output signals; A second switching circuit is coupled to the second set of voltage follower outputs and configured to reduce phase noise levels of the output signals. The device of claim 14, wherein the second switching circuit comprises: a third sub-circuit connected to the first output of the second set of voltage follower outputs, and Is coupled to a fourth current source; and a fourth sub-circuit connected to the second output of the second set of voltage follower outputs and coupled to a fifth current source The third sub-circuit and the fourth sub-circuit are coupled to each other. The device of claim 15, wherein the third sub-circuit comprises: a fifth NMOS transistor, the drain of the fifth NMOS transistor is coupled to the second set of voltage follower outputs The first output, the source of the fifth NMOS transistor is coupled to the fourth current source and a third capacitor. The device of claim 16, wherein the fourth sub-circuit comprises: a sixth NMOS transistor, the drain of the sixth NMOS transistor is coupled to the second output of the second set of voltage follower outputs, and the source of the sixth NMOS transistor is coupled to a first a fifth current source and a fourth capacitor, wherein a gate of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor, and a gate of the sixth NMOS transistor is connected to the fifth NMOS transistor Bungee jumping. The device of claim 17, wherein: the third capacitor corresponds to a third PMOS transistor, and the gate of the third PMOS transistor is connected to a source of the fifth NMOS transistor, and The source terminal and the drain terminal of the third PMOS transistor are connected to each other; and the fourth capacitor corresponds to a fourth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the source of the sixth NMOS transistor And the source terminal and the 汲 extreme pole of the fourth PMOS transistor are connected to each other. The device of claim 17, wherein the third capacitor and the respective second ends of the fourth capacitor are coupled to a positive power supply rail. The device of claim 14, wherein the second input receiving circuit comprises: a first NPN transistor, the base of the first NPN transistor is connected to one of the small signal logic inputs. a logic input, wherein the emitter of the first NPN transistor is coupled to a sixth current source; a second NPN transistor, a base of the second NPN transistor is coupled to a second logic input of the small signal logic inputs, and an emitter of the second NPN transistor is coupled to the sixth current source . The device of claim 20, wherein the second voltage follower circuit comprises: a third voltage follower sub-circuit, the third voltage is connected to the first input of the coupler sub-circuit a collector of the NPN transistor and a third resistor, wherein the output of the third voltage follower sub-circuit is connected to the drain of the fifth NMOS transistor in the third sub-circuit of the second switching circuit, and the The supply of the third voltage with the coupler sub-circuit is connected to a positive supply rail; a fourth voltage follower sub-circuit, the input of the fourth voltage with the coupler sub-circuit is connected to the second NPN transistor a collector and a fourth resistor, wherein an output of the fourth voltage-synchronizing coupler sub-circuit is connected to a drain of the sixth NMOS transistor in the fourth sub-circuit of the second switching circuit, and the fourth voltage is The supply power of the coupler sub-circuit is connected to a positive supply rail, wherein the third resistor and the fourth resistor are connected to a positive supply rail. The device of claim 21, wherein the second output circuit comprises: a fifth PMOS transistor, the gate of the fifth PMOS transistor being connected to the output of the third voltage follower sub-circuit The source of the fifth PMOS transistor is connected to a positive power supply rail, and the drain of the fifth PMOS transistor is connected to one of the output signals of the output signals; a sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the output of the fourth voltage follower sub-circuit, and the source of the sixth PMOS transistor is connected to a positive supply rail, and the The drain of the sixth PMOS transistor is connected to one of the second output signals of the output signals. The device of claim 14, further comprising a low voltage differential signaling (LVDS) output circuit coupled to the first output circuit and the second The output circuit generates an LVDS output signal. The device of claim 23, wherein the LVDS output circuit comprises: a fifth sub-circuit coupled to the output signals of the first output circuit and the second output circuit And a sixth sub-circuit coupled to the output signals of the first output circuit, and the fifth sub-circuit is configured to: based on the output signals of the first output circuit Generate LVDS output signal. The device of claim 24, wherein the fifth sub-circuit comprises: a seventh PMOS transistor, wherein the drain of the seventh PMOS transistor is connected to the output signals from the first output circuit a first output signal, wherein a source of the seventh PMOS transistor is coupled to a first output signal of the output signals from the second output circuit; An eighth PMOS transistor, the drain of the eighth PMOS transistor is connected to a second output signal of the output signals from the first output circuit, and the source of the eighth PMOS transistor is connected to a second output signal of the output signals from the second output circuit, wherein one of the gates of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor, and the eighth PMOS transistor A gate is connected to the drain of the seventh PMOS transistor. The device of claim 25, wherein the sixth sub-circuit comprises: a ninth PMOS transistor, the gate of the ninth PMOS transistor being connected to the output signals from the first output circuit a first output signal, the source of the ninth PMOS transistor is connected to a seventh current source, and the drain of the ninth PMOS transistor is connected to one of the first output signals of the LVDS output signals; a tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to one of the output signals from the first output circuit, and the source of the tenth PMOS transistor is connected to the a seventh current source, wherein the drain of the tenth PMOS transistor is connected to one of the second output signals of the LVDS output signals; and an eleventh PMOS transistor, the gate connection of the eleventh PMOS transistor To the second output signal of the output signals from the first output circuit, the drain of the eleventh PMOS transistor is connected to an eighth power a source of the eleventh PMOS transistor connected to the first output signal of the LVDS output signal; and a twelfth PMOS transistor, the gate connection of the twelfth PMOS transistor And the first output signal from the output signals of the first output circuit, the drain of the twelfth PMOS transistor is connected to the eighth current source, and the source of the twelfth PMOS transistor The second output signal connected to the LVDS output signals. The device of claim 23, wherein the LVDS output circuit comprises: a fifth sub-circuit coupled to the output signals of the first output circuit and the second output circuit And a sixth sub-circuit coupled to the output signals of the second output circuit, and the fifth sub-circuit is configured to: based on the output signals of the second output circuit Generate LVDS output signal. The device of claim 27, wherein the fifth sub-circuit comprises: a seventh NMOS transistor, wherein the drain of the seventh NMOS transistor is connected to the output signals from the second output circuit a first output signal, wherein the source of the seventh NMOS transistor is connected to one of the output signals from the output signals of the first output circuit; and an eighth NMOS transistor, the eighth NMOS The drain of the transistor is connected to one of the output signals from the second output circuit, the second output signal And the source of the eighth NMOS transistor is connected to one of the output signals from the first output circuit, wherein one of the gates of the seventh NMOS transistor is connected to the eighth The drain of the PMOS transistor and one of the gates of the eighth NMOS transistor are connected to the drain of the seventh NMOS transistor. The device of claim 28, wherein the sixth sub-circuit comprises: a ninth NMOS transistor, the gate of the ninth NMOS transistor being connected to the output signals from the second output circuit a first output signal, the NMOS of the ninth NMOS transistor is connected to a seventh current source, and the source of the ninth NMOS transistor is connected to one of the first output signals of the LVDS output signals; a tenth NMOS transistor, the gate of the tenth NMOS transistor is connected to one of the output signals from the second output circuit, and the drain of the tenth NMOS transistor is connected to the a seventh current source, wherein the source of the tenth NMOS transistor is connected to one of the second output signals of the LVDS output signals; an eleventh NMOS transistor, the gate connection of the eleventh NMOS transistor To the second output signal of the output signals from the second output circuit, the source of the eleventh NMOS transistor is connected to an eighth current source, and the eleventh NMOS transistor is connected to the drain The first output signal connected to the LVDS output signals; a twelfth NMOS transistor, the gate of the twelfth NMOS transistor is connected to the first output signal of the output signals from the second output circuit, and the source of the twelfth NMOS transistor Connected to the eighth current source, the drain of the twelfth NMOS transistor is coupled to the second output signal of the LVDS output signals. An apparatus for a clock driver, comprising: an input receiving circuit for receiving a small signal logic input; and a voltage follower circuit coupled to the input receiving circuit for generating a plurality of voltage follower outputs; an output circuit coupled to the voltage follower circuit for receiving the plurality of voltage follower outputs as an input and generating an output signal; a first switching a circuit, the voltage isolating circuit is coupled to the first switching circuit; and the first capacitor and the second capacitor, the first capacitor and the second capacitor comprise a charge reservoir; wherein the switching circuit is connected to the plurality A voltage follower is output and coupled to the first capacitor and the second capacitor, and configured to reduce phase noise levels of the output signals. The device of claim 30, wherein the small signal logic inputs are emitter coupled logic (ECL) inputs. The device of claim 29, wherein: the input receiving circuit comprises a first input receiving circuit and a second input receiving circuit; the voltage follower circuit comprises a first voltage follower circuit and a second voltage a coupler circuit; and the output circuit includes a first output circuit and a second output circuit. The device of claim 32, wherein the switching circuit comprises: a first switching circuit coupled to the first voltage follower and the first output circuit; a switching circuit, the second switching circuit is coupled to the second voltage follower and the second output circuit. The device of claim 33, wherein the first switching circuit comprises: a first sub-circuit connected to the voltage follower output of the first voltage follower circuit a first output coupled to a first current source; and a second sub-circuit coupled to one of the voltage follower outputs of the first voltage follower circuit The second output is coupled to a second current source, wherein the first sub-circuit and the second sub-circuit are coupled to each other. The device of claim 34, wherein the first sub-circuit comprises: a first p-channel metal oxide semiconductor (PMOS) transistor, and a drain of the first p-channel metal oxide semiconductor (PMOS) transistor The first output of the first p-channel MOS transistor is coupled to the first current source and the first capacitor. The device of claim 35, wherein the second sub-circuit comprises: a second PMOS transistor, the drain of the second PMOS transistor being coupled to the first voltage follower circuit a second output, wherein a source of the second PMOS transistor is coupled to the second current source and the second capacitor, wherein a gate of the first PMOS transistor is connected to the second PMOS transistor And a gate of the second PMOS transistor is connected to the drain of the first PMOS transistor. The device of claim 36, wherein: the first capacitor corresponds to a first n-channel metal oxide semiconductor (NMOS) transistor, and the gate of the first n-channel metal oxide semiconductor (NMOS) transistor Connecting to a source of the first PMOS transistor, wherein a source terminal and a NMOS terminal of the first n-channel MOS transistor are connected to each other; and the second capacitor corresponds to a second NMOS transistor The gate of the second NMOS transistor is connected to the source of the second PMOS transistor, and the source terminal and the 汲 terminal of the second NMOS transistor are connected to each other. The device of claim 36, wherein the first capacitor and the second terminal of the second capacitor are coupled to a negative supply rail. The device of claim 33, wherein the second switching circuit comprises: a third sub-circuit connected to the first output of the second voltage follower circuit, and The fourth sub-circuit is coupled to a second output of the second voltage follower circuit and coupled to a fourth current source, wherein the fourth sub-circuit is coupled to a second current source The third sub-circuit and the fourth sub-circuit are coupled to each other. The device of claim 39, wherein the third sub-circuit comprises: a third NMOS transistor, the drain of the third NMOS transistor being coupled to the second voltage follower circuit a first output, and a source of the third NMOS transistor is coupled to the third current source and a third capacitor. The device of claim 39, wherein the fourth sub-circuit comprises: a fourth NMOS transistor, the drain of the fourth NMOS transistor being coupled to the second voltage follower circuit a second output, wherein the source of the fourth NMOS transistor is coupled to a fourth current source and a fourth The gate of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor. The device of claim 41, wherein: the third capacitor corresponds to a third PMOS transistor, and the gate of the third PMOS transistor is connected to the source of the third NMOS transistor, and The source terminal and the NMOS terminal of the third PMOS transistor are connected to each other; and the fourth capacitor corresponds to a fourth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the source of the fourth NMOS transistor And the source terminal and the 汲 extreme pole of the fourth PMOS transistor are connected to each other. The device of claim 41, wherein the third capacitor and the respective second ends of the fourth capacitor are coupled to a positive power supply rail. A device for a CMOS clock driver, comprising: an input receiving circuit for receiving a small signal logic input; and a voltage follower circuit coupled to the input receiving circuit for use Generating a voltage follower output; and an output circuit coupled to the voltage follower circuit for receiving the voltage follower output as an input and generating an output signal; a switching circuit The voltage follower circuit is coupled to the switching circuit; And at least one capacitor, comprising one or more charge storages; wherein the switching circuit is coupled to the voltage follower output and coupled to the at least one capacitor, and configured to reduce phase mismatch of the output signal The level of information.