JPH10303732A - Level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level conversion circuit which is capable of stably converting, level independently of an amplitude of an input signal and reducing current consumption. SOLUTION: In this circuit, an amplitude detection bias circuit BG receiving an input signal Vin sets a gate bias voltage applied to a P-channel transistor(TR) MA high and a gate bias voltage applied to an N-channel TR MB low, when the amplitude of the input signal is high. Conversely, the amplitude detection bias circuit BG receiving the input signal Vin sets a gate bias voltage applied to the P, channel transistor(TR) MA low and the gate bias voltage applied to the N-channel TR MB high, when the amplitude of the input signal is low, Thus, a through-current flowing to the P-channel TR MA and to the N-channel TR MB is decreased, and the latch circuit is driven stably, even if the amplitude of the input signal is small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to an ECL (Emitter Coupled L).
ogic) a small amplitude signal such as a signal level into a CMOS
(Complementary-MOS) The present invention relates to a level conversion circuit capable of low power consumption operation when converting to a large amplitude signal such as a signal level.

[0002]

2. Description of the Related Art Conventionally, a level conversion circuit of this type has been disclosed in, for example, Japanese Patent Application Laid-Open No. 7-98983, BiCMO.
It is used for the purpose of converting an ECL interface into a CMOS interface in a semiconductor integrated circuit such as an SRAM using the S technology.

[0003] Referring to FIG. 7, a level conversion circuit described in this publication will be described.
P for charging node N1 to first power supply potential Vcc
A channel transistor MA and an N-channel transistor M for discharging node N1 to a second power supply potential Vee.
B, capacitors CA and CB for transmitting the input signal Vin applied to the input node N2 to the gates of the P-channel transistor MA and the N-channel transistor MB by capacitive coupling, and for latching the signal potential of the node N1. And a latch circuit LA including inverters IVA and IVB. Inverter IVA has its input and output connected to nodes N1 and N3, respectively, and its input and output connected to nodes N3 and N1, respectively.

Further, in this level conversion circuit, the gate of P-channel transistor MA is set at a predetermined potential (Vcc- | Vt).
p |) and the gate of the N-channel transistor MB at a predetermined potential (Vee + Vtn).
And a resistor RB for clamping the RB. here,
Vtp and Vtn are P-channel transistors MA, respectively.
And the threshold voltage of the N-channel transistor MB. The predetermined potential is generated by diode-connecting transistors having the same threshold voltage as the P-channel transistor MA and the N-channel transistor MB.

Next, the operation will be described. Input node N
When the input signal Vin applied to 2 changes from the ECL high level to the ECL low level, the gate voltage of the P-channel transistor MA decreases for a certain time due to the capacitive coupling of the capacitor CA, and the P-channel transistor MA is turned on for a certain time. Become.

As a result, when node N1 rises and its potential exceeds the input threshold value of inverter IVA, node N1 is brought to the CMOS high level and node N3 is brought to the CMOS level by latch circuit LA composed of inverters IVA and IVB.
It is kept at S low level. After a certain time, P
The channel transistor MA is turned off because it is clamped to a high level by the resistor RA.
The signal levels of N1 and N3 are held by the latch circuit LA.

Similarly, when the input signal Vin changes from the ECL low level to the ECL high level, if the N-channel transistor MB is turned on for a certain period of time and the potential of the node N1 falls below the input threshold of the inverter IVA, the inverter IVA , IVB latch circuit LA
Node N1 attains a CMOS low level,
3 is held at the CMOS high level. In the configuration of the conventional level conversion circuit shown in FIG.
Since there is no DC current path to the power supply potential Vcc and the second power supply potential Vee, current consumption can be significantly reduced.

Further, P-channel transistors MA and N
The current flowing through the channel transistor MB is the inverter I
Since the current flows only for a short time for charging and discharging VA and IVB, the through current can be greatly reduced.

[0009]

However, the above-described conventional level conversion circuit has the following problems. That is, although the gates of the P-channel transistor MA and the N-channel transistor MB are clamped to approximately the threshold voltages of the respective transistors, the P-channel transistor MA and the N-channel transistor MB actually cause the P-channel transistors MA and N Through current flows from the first power supply potential Vcc to the second power supply potential Vee via the channel transistor MA and the N-channel transistor MB.

In order to reduce this through current, the gate bias voltage Vo1 of the P-channel transistor MA is increased by (Vcc
− | Vtp |), and the gate bias voltage Vo2 of the N-channel transistor MB is set to (Vee + Vtn).
There are ways to make it lower.

In this case, the P-channel transistor MA and the N-channel transistor MB must be turned on regardless of the magnitude of the input signal, and the amplitude of the input signal is set to Vi.
pp needs to satisfy the following expressions (1) and (2).

Vo1 <Vcc− | Vtp | + Vipp (1) Vo2> Vee + Vtn−Vipp (2) On the other hand, conversely to drive the latch circuit LA including the inverters IVA and IVB. It is necessary to lower the gate bias voltage Vo1 and increase the gate bias voltage Vo2 so that a necessary current can flow.

Here, the input signal amplitude V which varies with time
i (t) is input to the node N2, and the input signal amplitude Vi
Considering that the through current of the level conversion circuit shown in FIG.
The gate bias voltage Vo1 (t) of A is expressed by the following equation (1): Vo1 (t) = Vcc− | Vtp | + Vi (t) (3) Similarly, the gate bias voltage Vo2 ( From equation (2), t) is given by Vo2 (t) = Vee + Vtn-Vi (t) (4) However, when the input signal amplitude Vipp is smaller than the input signal amplitude Vi (t) with the gate bias voltage set by the equations (3) and (4), the gate bias voltages Vo1 and Vo2 are calculated by the equations (1) and (2). In some cases, the expression (2) cannot be satisfied. For this reason,
There is a disadvantage that the P-channel transistor MA and the N-channel transistor MB do not turn on, and the conventional level conversion circuit shown in FIG. 7 malfunctions.

Conversely, in order to make it possible to perform level conversion even when the input signal amplitude Vipp is sufficiently small, the gate bias voltage Vo1 is set sufficiently low and the gate bias voltage Vo2 is set sufficiently high according to the equations (1) and (2). But
At this time, since the through current through the P-channel transistor MA and the N-channel transistor MB becomes large, there is a disadvantage that the current consumption becomes larger than necessary for an input signal having a large input signal amplitude Vipp.

Therefore, an object of the present invention is to change the gate bias voltage in accordance with the input signal amplitude Vipp to stably perform the level conversion operation irrespective of the input signal amplitude and reduce the current consumption. A level conversion circuit is provided.

More specifically, when the input signal amplitude Vipp is large, the gate bias voltage applied to the P-channel transistor MA is increased and the N-channel transistor MB is applied within a range satisfying the equations (1) and (2). Set the gate bias voltage to be low to reduce the through current,
Conversely, when the input signal amplitude Vipp is small, the right side of the equation (1) is small and the right side of the equation (2) is large. Accordingly, the gate bias voltage applied to the P-channel transistor MA is reduced and the N-channel transistor is reduced. It is an object of the present invention to provide a level conversion circuit that can set a gate bias voltage applied to MB high and can stably drive a latch circuit even when an input signal amplitude Vipp is small.

[0017]

Therefore, a level conversion circuit according to the present invention includes a first P-channel transistor having a source connected to a first power supply and a drain connected to an output terminal, and a source connected to the first power supply. A first N-channel transistor connected to a lower-potential second power supply and having a drain connected to the output terminal, and an input terminal for applying an input signal to the first N-channel transistor.
A first capacitor and a second capacitor for transmitting a signal to each gate of the P-channel transistor and the first N-channel transistor by capacitive coupling, and a signal output from the output terminal based on the input signal amplitude. A latch circuit that latches the signal amplitude of the input signal, and a first circuit that detects a signal amplitude of the input signal and applies the signal amplitude from the first output terminal to the gate of the first P-channel transistor when the signal amplitude is large. When the gate bias voltage is high and the second gate bias voltage applied to the gate of the first N-channel transistor from the second output terminal is low, and when the signal amplitude is small, the first output terminal is The first gate bias voltage applied to the gate of the first P-channel transistor is low, and the first gate bias voltage is reduced from the second output terminal to the first gate voltage.
And an amplitude detecting bias circuit for controlling the second gate bias voltage applied to the gate of the N-channel transistor to be higher.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the level conversion circuit of the present invention. Note that components common to the conventional example are denoted by common reference characters / numbers.

The level conversion circuit 100 according to the present embodiment
Are a P-channel transistor MA for charging node N1 to a first power supply potential Vcc, an N-channel transistor MB for discharging node N1 to a second power supply potential Vee, and an input applied to input node N2. Signal Vin
Are respectively connected by P-channel transistors MA by capacitive coupling.
And capacitors CA and CB for transmitting to nodes NGA and NGB connected to respective gates of N-channel transistor MB.
And an amplitude detection bias circuit BG for detecting the signal amplitude Vipp of the input signal Vin and changing the bias voltages of the nodes NGA and NGB in response thereto, and a latch circuit LA.

Here, the latch circuit LA for latching the signal potential of the node N1 is composed of inverters IVA and IVB. The input and output of the inverter IVA are connected to the nodes N1 and N3, respectively.
The input and output of VB are connected to nodes N3 and N1, respectively.

The input I of the amplitude detection bias circuit BG is
N is connected to an input node N2, and two output terminals O1 and O2 of the amplitude detection bias circuit BG are connected to nodes NGA and NGB via resistors RA and RB.

Next, a basic level conversion operation of the level conversion circuit of the present invention will be described.

The input signal Vi applied to the input node N2
When n changes from the ECL high level to the ECL low level, the gate voltage of the P-channel transistor MA decreases for a certain time due to the capacitive coupling of the capacitor CA, and the P-channel transistor MA is turned on for a certain time.

As a result, when node N1 rises and its potential exceeds the input threshold value of inverter IVA, node N1 is brought to the CMOS high level and node N3 is brought to the CMOS level by latch circuit LA composed of inverters IVA and IVB.
It is kept at S low level. After a certain time, P
The channel transistor MA is turned off because it is clamped to a high level by the resistor RA.
The signal levels of N1 and N3 are held by the latch circuit LA.

Similarly, when the input signal Vin changes from the ECL low level to the ECL high level, when the N-channel transistor MB is turned on for a certain period of time and the potential of the node N1 falls below the input threshold of the inverter IVA, the inverter IVA , IVB latch circuit LA
Node N1 attains a CMOS low level,
3 is held at the CMOS high level.

The basic operation up to this point is described in FIG.
Is the same as the operation of the conventional level conversion circuit shown in FIG.

The amplitude detection bias circuit BG constituting the level conversion circuit of the present invention detects the input signal amplitude Vipp of the input signal Vin, and outputs the P-channel transistor MA via the output terminals O1 and O2 of the amplitude detection bias circuit BG. And a bias circuit for setting bias voltages V1 and V2 applied to each gate of the N-channel transistor MB. Assuming that the threshold values of the P-channel transistor MA and the N-channel transistor MB are Vtp and Vtn,
In the non-signal state, the gate bias voltages V1 and V2 are substantially (Vcc− | Vtp |) and (Vee + Vtn), respectively.
, And controls the gate bias voltages V1 and V2 according to the input signal amplitude Vipp.

Specifically, when the input signal amplitude Vipp is large, the gate bias voltage V1 is controlled to be high and the gate bias voltage V2 is low, and when the input signal amplitude Vipp is small, the gate bias voltage V1 is controlled. V1 is controlled to be low, and the gate bias voltage V2 is controlled to be high.

Next, the specific operation of the level conversion circuit according to the present invention will be described in more detail with reference to FIG.

Now, when the input signal Vin changes from a small amplitude to a large amplitude such as α → β → γ as shown by an arrow p in FIG. 2, the gate potential VG of the P-channel transistor MA
MA changes from small to large, such as α ′ → β ′ → γ ′. Further, the output terminal O1 is supplied from the amplitude detection bias circuit BG.
The gate bias voltage V1 output via the
As shown in the figure, the level changes from a low level to a high level in the order of a1 → a2 → a3.

Similarly, when the input signal Vin changes from a small amplitude to a large amplitude, the gate potential VGMB of the N-channel transistor MB changes from small to large as α ″ → β ″ → γ ″. The gate bias voltage V2 output from the amplitude detection bias circuit BG via the output terminal O2.
Changes from a high level to a low level in the order of α ″ → β ″ → γ ″ as shown by an arrow b.

Here, paying attention to the portion A in FIG. 2, even if the input signal amplitude Vipp changes, the lower peak value of the gate potential VGMA of the P-channel transistor MA is substantially constant and the voltage (Vcc- | Vtp) |) Lower. Therefore, the P-channel transistor MA satisfies the following equation (5) similar to the equation (1), and can be turned on.

V1 <Vcc− | Vtp | + Vipp (5) On the other hand, focusing attention on the portion B in FIG. 2, the input signal amplitude Vipp
, The upper peak value of the gate potential VGMB of the N-channel transistor MB is substantially constant and is higher than the voltage (Vee + Vtn). Therefore, the N-channel transistor MB satisfies the following expression (6) similar to the expression (2), and can be turned on.

V2> Vee + Vtn−Vipp (6) Accordingly, when the input signal amplitude Vipp is large, the gate bias voltages V2 and V1 are set to a3 and b3 in FIG. 2, so that the P-channel transistors MA and N The channel transistor MB is sufficiently turned off, and the level conversion operation can be performed with a small through current. Also,
When the input signal amplitude Vipp is small, the gate bias voltages V2 and V1 approach the threshold values of the P-channel transistor MA and the N-channel transistor MB as shown by a1 and b1 in FIG. It is possible to improve the problem of the increase in the through current, and to operate the level conversion circuit normally without increasing the through current. That is, the current is controlled to an optimum value according to the magnitude of the input signal Vin.

From the above description, the level conversion circuit according to the present invention requires a large circuit current in order to stably perform the level conversion which has been a problem in the conventional level conversion circuit, and conversely, the circuit current must be increased. If the level is reduced, the problem that the level conversion operation cannot be performed is improved. Even if the input signal amplitude Vipp changes greatly, not only the level conversion is performed stably, but also the through current is small and the power consumption is small. Has excellent features.

Next, the amplitude detection bias circuit BG constituting the level conversion circuit of the present invention will be described with reference to FIG.

The amplitude detection bias circuit BG includes an envelope detection circuit ED for detecting an envelope of an input signal, a variable resistance circuit RV, and a threshold bias circuit BS.

The envelope detection circuit ED has a node IN as an input terminal, nodes N9 and N10 as output terminals, and a capacitor CC and a resistor RC connected in parallel between the first power supply potential Vcc and the node N9.

Further, P-channel transistors MC and MD having their gates and drains connected are connected to nodes N9 and IN, respectively.
Are connected in series, and N-channel transistors ME and MF each having a gate and a drain connected are connected in series between the node N10 and the node IN.

Further, the second power supply potential Vee and the node N
A capacitor CD and a resistor RD are connected in parallel between the terminals 10.

The variable resistance circuit RV is connected to nodes N9 and N10.
Are input terminals, nodes O1 and O2 are output terminals, and a resistor R
E, an N-channel transistor MG whose drain is connected to the node O1, the gate is connected to the node N9, and the source is connected to one terminal of the resistor RE, the drain is the node O2, the gate is the node N10, and the source is the other terminal of the resistor RE. And a P-channel transistor MH connected to the P-channel transistor.

The threshold bias circuit BS has the nodes O1 and O2 as output terminals and has a source connected to the first power supply potential V.
cc, a P-channel transistor MI having a gate and a drain connected to the node O1, and a source connected to the second power supply potential Ve.
e includes an N-channel transistor MJ having a gate and a drain connected to the node O2, and a resistor RF connected to the nodes O1 and O2.

Next, the amplitude detection bias circuit BG shown in FIG.
Will be described with reference to FIG. Here, FIG. 4 is a signal waveform diagram showing a time change of each node voltage waveform of the amplitude detection bias circuit BG. FIG. 4A shows a case where the input signal amplitude Vipp is small, and FIG. 4B shows an input signal amplitude Vip.
The case where p is large is shown.

The voltage VN9 at the node N9 is supplied from the input terminal IN to the capacitor C via P-channel transistors MC and MD which perform a diode operation when the input signal is at the low potential Vinl.
By supplying electric charge to C, a voltage higher than low potential Vinl by the threshold voltage of P-channel transistors MC and MD, that is, as shown at time t1 in FIG. 4, VN9 = Vinl + 2 · | Vtp |・ It is clamped by (7). Increase the value of the resistor RC and increase the capacitance CC
And the time constant determined by the resistance RC is increased to some extent, the voltage VN9 is clamped to the value of the equation (7) for a certain period of time as shown by a dashed line in FIG. 4 even when the input signal Vin changes to a high potential. Will remain. With this operation, the voltage V
N9 detects an envelope on the low potential side of the input signal Vin.

Similarly, the voltage VN10 of the node N10 is set to N which performs a diode operation when the input signal is at the high potential Vinh.
Input terminal IN via channel transistors ME and MF
Is supplied to the capacitor CD from the high potential Vin.
The voltage is clamped to a voltage lower than h by the threshold voltage of the N-channel transistors ME and MF, that is, VN10 = Vinh−2 · Vtn (8) as shown at time t0 in FIG. Increase the value of the resistor RD and increase the capacitance CD
And the time constant determined by the resistance RD is increased to a certain degree, the voltage VN1 is maintained even when the input signal changes to a low potential.
0 remains clamped to the value of equation (8) for a certain period of time. With this operation, the voltage VN10 detects the envelope on the high potential side of the input signal Vin as indicated by the dashed line in FIG.

Next, the variable resistance circuit RV will be described with reference to FIG.
It changes with N9 and VN10. Here, assuming that the threshold voltages of the N-channel transistor MG and the P-channel transistor MH are the same as the threshold voltages of the N-channel transistor ME and the P-channel transistor MC forming the envelope detection circuit ED, respectively, Is given by the following equation (9).

VRE = (VN9−Vtn) − (VN10 + | Vtp |) (9) By substituting the equations (7) and (8) into the equation (9), VRE = | Vtp | + Vtn− ( Vinh−Vinl) (10), and since Vipp = Vinh−Vinl, (10)
The equation is as follows: VRE = | Vtp | + Vtn-Vipp (11) This relationship is shown at the right end of FIGS.
As can be seen from equation (11), the voltage VRE decreases as the input signal amplitude Vipp increases, and conversely, the input signal amplitude Vipp
It increases as pp decreases.

The current IRE is calculated by the following equation (12).

IRE = VRE / RE = (| Vtp | + Vtn−Vipp) / RE (12) However, the input signal amplitude Vipp increases, and Vip
Under the condition that p ≧ (| Vtp | + | Vtn |), no current IRE flows. From the equation (12), the input signal amplitude Vip
When p is large, the current IRE becomes small, and conversely, when the input signal amplitude Vipp is small, the current IRE becomes large. Current I
The current ID flowing through the P-channel transistor MI and the N-channel transistor MJ also changes due to RE, and the current I
If RE is small, current ID is small, and if current IRE is large, current ID is large.

The current ID changes the gate-source voltage of the P-channel transistor MI and the N-channel transistor MJ, and accordingly, the voltages V1 and V2 of the nodes O1 and O2 change. If the current ID is large, the voltage V1 is low and the voltage V2 is high. Conversely, if the current ID is small, the voltage V1 is high and the voltage V2 is low.

Therefore, when the input signal amplitude Vipp is small, the voltage V1 is low and the voltage V2 is high. Conversely, when the input signal amplitude Vipp is large, the voltage V1 is high and the voltage V2 is low.

In the description of FIG. 3, the input terminal IN and the node N
9, two P-channel transistors performing a diode operation are connected in series, and two N-channel transistors performing a diode operation are connected between the input terminal IN and the node N10.
Although the case of connecting in series has been described, the number is not necessarily limited to two, and the same effect can be obtained by connecting one or three or more in series.

Next, a second embodiment of the level conversion circuit of the present invention will be described with reference to FIG. FIG.
Components common to FIG. 3 and FIG. 3 are denoted by common reference characters / numbers.

Level conversion circuit 200 according to this embodiment
Are capacitive coupling type level conversion circuits LC1, LC2, amplitude detection bias circuits BG1, BG2, and a latch circuit LA.
And buffer circuits BF1 and BF2. The buffer circuits BF1 and BF2 receive the output signal of the latch circuit LA and drive a load connected to the output terminals Out1 and Out2.

Capacitively-coupled level conversion circuits LC1, LC2
Has the same circuit configuration as the capacitive coupling level conversion circuit LC in FIG. 1, and the amplitude detection bias circuits BG1 and BG2 have the same circuit configuration as the amplitude detection bias circuit BG shown in FIG. Further, envelope detection circuits ED1, ED2 constituting the amplitude detection bias circuits BG1, BG2, variable resistance circuits RV1, RV2, and threshold bias circuits BS1,
BS2 has the same circuit configuration as the envelope detection circuit ED, variable resistance circuit RV, and threshold bias circuit BS shown in FIG.

Level conversion circuit 200 according to the present embodiment
Performs level conversion using input signals applied to the input terminals IN1 and IN2 as differential inputs, so that even if the input signal contains many DC components, the input voltage can be detected and the bias voltage can be changed.

The amplitude detection bias circuits BG1, BG
2, two envelope detection circuits ED1 and ED
By sharing the two output nodes N9 and N10, the amplitude of the input signal can be detected even when the input signal contains many DC components.

Next, a second embodiment of the amplitude detection bias circuit of the present invention will be described with reference to FIGS.

The amplitude detecting bias circuit of the present invention has two circuits each having the same circuit configuration as the envelope detecting circuit ED, the variable resistor circuit RV, and the threshold bias circuit BS shown in FIG.
It comprises two envelope detection circuits ED1, ED2, a variable resistance circuit RV and a threshold bias circuit BS. The output nodes N9 and N10 of the envelope detection circuits ED1 and ED2 are commonly connected to each other, and are connected to the gates of a P-channel transistor and an N-channel transistor constituting the variable resistance circuit RV.

The amplitude detection bias circuit according to the present invention comprises an input signal vi1 applied to an input terminal IN1 and an input signal IN2
Are used to generate the voltages VN9 and VN10 of the nodes N9 and N10 shown in FIG. 3, so that the envelope detection circuits ED1 and ED2 are used.
Is independent of the fixed time determined by the time constant set by the capacitance CC and the resistance RC or the capacitance CD and the resistance RD. Even when the input signal contains a large amount of DC components, the clamping voltage is applied via the nodes N9 and N10. Thus, the bias voltage supplied to the threshold bias circuit BS can be controlled.

[0062]

As described above, the level conversion circuit of the present invention changes the gate bias voltage of the MOS transistor in accordance with the input signal amplitude, thereby performing the level conversion operation stably irrespective of the input signal amplitude. In addition, current consumption can be reduced.

Further, when level conversion is performed using an input signal applied to two input terminals as a differential input, even if the input signal contains many DC components, the input voltage can be detected and the bias voltage can be changed. In addition, level conversion can be performed for a wide input frequency range from DC to high frequency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a level conversion circuit of the present invention.

FIG. 2 is a signal waveform diagram for explaining an operation of the level conversion circuit shown in FIG.

FIG. 3 is a circuit diagram showing a first embodiment of the amplitude detection bias circuit of the present invention.

FIG. 4 is a signal waveform diagram for explaining an operation of the amplitude detection bias circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing a second embodiment of the level conversion circuit of the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the amplitude detection bias circuit of the present invention.

FIG. 7 is a circuit diagram showing a conventional level conversion circuit.

[Explanation of symbols]

BF1, BF2 Buffer circuit BG, BG1, BG2 Amplitude detection bias circuit BS, BS1, BS2 Threshold bias circuit CA, CB, CC, CD Capacitance ED, ED1, ED2 Envelope detection circuit IVA, IVB Inverter LA Latch circuit LC, LC1 , LC2 Capacitive coupling type level conversion circuit MA, MC, MD, MH, MIP channel transistor MB, ME, MF, MG, MJ N channel transistor RA, RB, RC, RD, RE, RF resistance RV, RV1, RV2 variable Resistance circuit

Claims (9)

[Claims] A first P-channel transistor having a source connected to a first power supply and a drain connected to an output terminal; a source connected to a second power supply having a lower potential than the first power supply; and a drain connected to the second power supply. A first N-channel transistor connected to an output terminal; and a second N-channel transistor for transmitting a signal from an input terminal for applying an input signal to each gate of the first P-channel transistor and the first N-channel transistor by capacitive coupling. A first capacitor and a second capacitor, a latch circuit for latching a signal output from the output terminal to a signal level larger than the input signal amplitude, and detecting a signal amplitude of the input signal, wherein the signal amplitude is large. In this case, the first gate bias voltage applied to the gate of the first P-channel transistor from the first output terminal is increased, and the first gate bias voltage is applied to the first P-channel transistor from the second output terminal. A second gate bias voltage applied to the gate of the channel transistor is reduced, and when the signal amplitude is small, a first gate bias voltage applied to the gate of the first P-channel transistor from the first output terminal And an amplitude detection bias circuit for controlling the second gate bias voltage applied from the second output terminal to the gate of the first N-channel transistor to be high. circuit. 2. The latch circuit according to claim 1, wherein an output of the first inverter is connected to an input of the second inverter, and an input of the first inverter is connected to an output of the second inverter. 2. The level conversion circuit according to 1. 3. A first resistor is inserted between the first output terminal and a gate of the first P-channel transistor,
2. The level conversion circuit according to claim 1, wherein a second resistor is inserted between the second output terminal and a gate of the first N-channel transistor. 4. An envelope detection circuit for detecting an envelope of an input signal and outputting a high potential of the envelope and a low potential of the envelope; and a high potential of the envelope. When the difference signal of the low potential of the envelope is large, a large current flows, and conversely, when the difference signal is small, a variable resistance circuit that flows a small current, and when the current flowing through the variable resistance circuit is large, When the voltage output to the first output terminal is low, the voltage output to the second output terminal is high, and when the current flowing through the variable resistance circuit is small, the voltage output to the first output terminal is And a threshold bias circuit that is high and reduces a voltage output to the second output terminal.
4. The level conversion circuit according to 2 or 3. 5. The envelope detection circuit according to claim 1, wherein one or a plurality of P-channel transistors having a gate and a drain connected in series are connected, and the input signal is sequentially DC-level-converted to a high potential side. A third resistor and a third capacitor are connected in parallel between the source of a P-channel transistor and the first power supply, and one or more N-channel transistors having a gate and a drain connected in series are connected to the input signal. , And sequentially level-converted to a lower potential side in a direct current manner, and a fourth resistor and a fourth capacitor are connected in parallel between the source of the last N-channel transistor and the second power supply. The level conversion circuit according to claim 4, wherein 6. The variable resistance circuit includes: a third N-channel transistor having a gate to which a low potential of the envelope is applied and a drain connected to the first output terminal; and a gate having a high potential of the envelope. A third P-channel transistor having an applied drain connected to the second output terminal; and a fifth resistor connected between the source of the third N-channel transistor and the third P-channel transistor. The level conversion circuit according to claim 4, wherein: 7. The threshold bias circuit includes a fourth P-channel transistor having a source connected to a first power supply, a gate and a drain connected to the first output terminal, and a source connected to a second power supply. A fourth N-channel transistor having a gate and a drain connected to the second output terminal; and a sixth resistor between each drain of the fourth P-channel transistor and the fourth N-channel transistor. 5. The level conversion circuit according to claim 4, wherein the level conversion circuit is connected. 8. A first P-channel transistor having a source connected to a first power supply and a drain connected to a first output terminal, and a source connected to a second power supply having a lower potential than the first power supply. A first N having a drain connected to the first output terminal;
A channel transistor; and a first capacitor for transmitting a signal by capacitive coupling from a first input terminal for applying a first input signal to each gate of the first P-channel transistor and the first N-channel transistor. A first capacitance-coupling type level conversion circuit having a first capacitor and a second capacitor; a second P-channel transistor having a source connected to the first power supply and a drain connected to the second output terminal; A second N-channel transistor connected to a second power supply having a lower potential than the first power supply and having a drain connected to the second output terminal; and a second input terminal for applying a second input signal to the second N-channel transistor. Capacitive coupling level having a third capacitance and a fourth capacitance for transmitting a signal to each gate of the P-channel transistor and the second N-channel transistor by capacitive coupling. A conversion circuit, wherein the first output terminal is connected to a first input terminal, and the second output terminal is connected to a second input terminal, and is larger than the first and second input signal amplitudes. A latch circuit for latching at a signal level; detecting a signal amplitude of the first input signal; and when the first signal amplitude is large, a third output terminal outputs the first P signal.
A first gate bias voltage applied to the gate of the channel transistor is increased, and a second gate bias voltage applied to the gate of the first N-channel transistor from a fourth output terminal is decreased, the first signal When the amplitude is small, the first gate bias voltage applied to the gate of the first P-channel transistor from the third output terminal is reduced, and the first gate bias voltage of the first N-channel transistor is reduced from the fourth output terminal. A first amplitude detection bias circuit for controlling the second gate bias voltage applied to the gate to be higher, and detecting a signal amplitude of the second input signal, and when the second signal amplitude is large, From the fifth output, the second P
A third gate bias voltage applied to the gate of the channel transistor is increased, and a fourth gate bias voltage applied to the gate of the second N-channel transistor from the sixth output terminal is decreased, so that the second signal When the amplitude is small, the third gate bias voltage applied to the gate of the second P-channel transistor from the sixth output terminal is reduced, and the third gate bias voltage of the second N-channel transistor is reduced from the sixth output terminal. A second amplitude detection bias circuit for controlling a fourth gate bias voltage applied to the gate to be higher. 9. A first P-channel transistor having a source connected to a first power supply and a drain connected to a first output terminal, and a source connected to a second power supply having a lower potential than the first power supply. A first N having a drain connected to the first output terminal;
A channel transistor; and a first capacitor for transmitting a signal by capacitive coupling from a first input terminal for applying a first input signal to each gate of the first P-channel transistor and the first N-channel transistor. A first capacitance-coupling type level conversion circuit having a first capacitor and a second capacitor; a second P-channel transistor having a source connected to the first power supply and a drain connected to the second output terminal; A second N-channel transistor connected to a second power supply having a lower potential than the first power supply and having a drain connected to the second output terminal; and a second input terminal for applying a second input signal to the second N-channel transistor. Capacitive coupling level having a third capacitance and a fourth capacitance for transmitting a signal to each gate of the P-channel transistor and the second N-channel transistor by capacitive coupling. A conversion circuit, wherein the first output terminal is connected to a first input terminal, and the second output terminal is connected to a second input terminal, and is larger than the first and second input signal amplitudes. A latch circuit for latching the signal at a signal level; detecting a first envelope of the first input signal;
A first envelope detection circuit for outputting a high potential of the envelope of the first envelope and a low potential of the first envelope; detecting a second envelope of the second input signal;
A second envelope detection circuit that outputs a high potential of the envelope of the second envelope and a low potential of the second envelope, and a high potential of the first and second envelopes and the first and second envelopes.
When the difference signal of the low potential of the envelope is large, a large current flows, and conversely, when the difference signal is small, a variable resistance circuit that flows a small current, and when the current flowing through the variable resistance circuit is large, The gate bias voltage applied to the gates of the first and second P-channel transistors is reduced, the gate bias voltage applied to the first and second N-channel transistors is increased, and the current flowing through the variable resistance circuit is small. In case,
Increasing the gate bias voltage applied to the gates of the first and second P-channel transistors,
And a threshold bias circuit for reducing a gate bias voltage applied to the N-channel transistor.