CN111208343A

CN111208343A - Self-calibration zero-crossing detection comparator

Info

Publication number: CN111208343A
Application number: CN202010036170.0A
Authority: CN
Inventors: 韩颖杰
Original assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Current assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Priority date: 2020-01-14
Filing date: 2020-01-14
Publication date: 2020-05-29
Anticipated expiration: 2040-01-14
Also published as: CN111208343B

Abstract

The invention discloses a self-calibration zero-crossing detection comparator which comprises a signal input module, a driving module, a storage module and a phase inverter, wherein the signal input module is used for receiving voltages at two ends of a synchronous rectifying tube, obtaining corresponding current according to the received voltages at the two ends of the synchronous rectifying tube and outputting the current to the driving module; the driving module is used for converting the current input by the signal input module and transmitting the current to the storage module; the storage module is used for storing the voltage converted by the current transmitted by the driving module, obtaining dynamic voltage caused by the current and outputting the dynamic voltage to the inverter; the inverter is used for inverting according to the value of the dynamic voltage and sending an inversion signal to the trigger of the switching power supply. The zero-crossing detection comparator of the invention adopts a self-calibration technology to reduce offset voltage, so that the zero-crossing detection is more accurate.

Description

Self-calibration zero-crossing detection comparator

Technical Field

The invention relates to an integrated circuit, in particular to a self-calibration zero-crossing detection comparator.

Background

In the switching power supply, the synchronous rectification technology adopts a power MOS tube with low on-resistance to replace a rectifier diode, so that the switching power supply has higher conversion efficiency. When the load is light, the zero crossing of the current of the synchronous rectifier tube needs to be detected, and the synchronous rectifier tube is closed, so that the conversion efficiency of the switching power supply when the load is light is improved.

And directly comparing the voltage drop at two ends of the synchronous rectifier tube by using a comparator, and judging whether the voltage drop is less than 0 or not, so that zero-crossing detection can be realized. The general comparator has offset voltage, and the offset voltage is required to be controlled to be very small for accurately detecting the current zero crossing. The traditional method is to add an extra trimming circuit or increase the area of a comparator to reduce the offset voltage, both of which increase the circuit cost, and the offset voltage changes with the temperature change and the aging, so that it is difficult to control the offset voltage to be small. In view of this, how to accurately reduce the offset voltage of the zero-cross detection comparator is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a zero-crossing detection circuit adopting a self-calibration technology, which reduces offset voltage through the self-calibration technology and enables zero-crossing detection to be more accurate.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a self-calibration zero-crossing detection comparator is used for comparing voltage drops at two ends of a synchronous rectifier tube in a switching power supply and specifically comprises a signal input module, a driving module, a storage module and a phase inverter. The signal input module is connected with the driving module, the driving module is connected with the storage module, and the storage module is connected with the phase inverter. The signal input module is used for receiving voltages at two ends of the synchronous rectifying tube, obtaining corresponding current according to the received voltages at the two ends of the synchronous rectifying tube and outputting the current to the driving module. The driving module is used for converting the current input by the signal input module and transmitting the current to the storage module. The storage module is used for storing the voltage corresponding to the current transmitted by the driving module, obtaining the dynamic voltage caused by the current and outputting the dynamic voltage to the inverter. The inverter is used for inverting according to the value of the dynamic voltage and sending an inversion signal to the trigger of the switching power supply.

Further, the signal input module includes a transconductance amplifier, a selection switch S1 and a selection switch S2. The non-inverting input end of the transconductance amplifier is connected with the output end of the synchronous rectifier tube through a selection switch S1, the non-inverting input end of the transconductance amplifier is connected with the input end of the synchronous rectifier tube through a selection switch S2, the inverting input end of the transconductance amplifier is connected with the output end of the synchronous rectifier tube, and the output end of the transconductance amplifier is connected with the driving module. When the selection switch S1 is turned on and the selection switch S2 is turned off, the non-inverting input terminal and the inverting input terminal of the transconductance amplifier are both connected to the output terminal voltage of the synchronous rectifier, and the transconductance amplifier obtains a first current according to the output terminal voltage of the synchronous rectifier and outputs the first current to the driving module. When the selection switch S1 is turned off and the selection switch S2 is turned on, the voltage at the input end of the synchronous rectifier is input to the non-inverting input end of the transconductance amplifier, the voltage at the output end of the synchronous rectifier is input to the inverting input end of the transconductance amplifier, and the transconductance amplifier obtains a second current according to the voltage at the input end and the voltage at the output end of the synchronous rectifier and outputs the second current to the driving module.

Further, the driving module comprises an NMOS transistor N1, a source of the NMOS transistor N1 is connected to the output terminal of the transconductance amplifier, a drain of the NMOS transistor N1 is connected to the storage module, and a gate of the NMOS transistor N1 is connected to the bias voltage. The bias voltage is used for enabling the NMOS transistor N1 to work in a common-gate state, the NMOS transistor N1 is used for converting the first current into a third current and transmitting the third current to the memory module, and the second current is converted into a fourth current, and the third current is stored in the memory module in a voltage form.

Further, the memory module includes a PMOS transistor P1, a capacitor C1, and a selection switch S3. The source of the PMOS transistor P1 is connected to the internal power supply of the switching power supply and the anode of the capacitor C1, and the cathode of the capacitor C1 is connected to the gate of the PMOS transistor P1 and to the drain of the PMOS transistor P1 through the selection switch S3. The PMOS transistor P1 works in a common-gate state, and the capacitor C1 is used for storing voltage information corresponding to the third current.

Further, the drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and to the inverter through the selection switch S4. The difference between the third current and the fourth current causes the drain voltage of the PMOS transistor P1 to change, the dynamic voltage of the drain of the PMOS transistor P1 is input to the inverter through the selection switch S4 by the PMOS transistor P1, and the output of the inverter is triggered to flip by the dynamic voltage of the drain of the PMOS transistor P1.

Further, the input terminal of the inverter is connected to the positive electrode of the capacitor C1 through the selection switch S5, and the output terminal of the inverter is connected to the set terminal of the flip-flop of the switching power supply. The inverter inverts according to the dynamic voltage of the drain of the PMOS pipe P1 and transmits an inversion signal to the set end of the trigger of the switching power supply.

Compared with the prior art, the invention has the following beneficial effects:

(1) the comparator adopts the signal input module to receive the voltages at the two ends of the synchronous rectifier tube, obtains the corresponding current according to the received voltages at the two ends of the synchronous rectifier tube and outputs the current to the driving module, the driving module converts the current input by the signal input module and transmits the current to the storage module, the storage module stores the voltage corresponding to the current transmitted by the driving module, obtains the dynamic voltage caused by the current and outputs the dynamic voltage to the inverter, the inverter overturns according to the value of the dynamic voltage and sends an overturning signal to the trigger of the switching power supply, and in such a way, the synchronous rectifier tube is controlled to be turned off by the overturning of the inverter, so that the conversion efficiency of the switching power supply is improved.

(2) The comparator of the invention converts offset voltage information into voltage to be stored in the storage unit in the calibration stage, converts the voltage stored in the storage unit into current with the offset voltage information in the comparison stage, compares the current with corresponding current generated by voltages at two ends of the synchronous rectifier tube, cancels the offset voltage of the comparator when the voltages at two ends of the synchronous rectifier tube are equal, namely, when the inductive current crosses zero, reduces the interference of the offset voltage on zero-crossing detection, leads the zero-crossing detection to be more accurate, and improves the conversion efficiency of the switching power supply.

(3) The comparator of the invention avoids the traditional method of adding an additional trimming circuit or increasing the area of the comparator to reduce the offset voltage by a self-calibration method, thereby saving the circuit cost and reducing the difficulty of maintaining the circuit.

Drawings

FIG. 1 is a block diagram of the system of the present invention.

Fig. 2 is a circuit diagram of a boost switching power supply according to an embodiment of the invention.

Fig. 3 is a waveform diagram of the operation of the boost switching power supply according to the embodiment of the invention.

Fig. 4 is a circuit diagram of a self-calibrating zero-crossing detection comparator according to an embodiment of the invention.

Fig. 5 is a timing diagram illustrating the operation of the zero-crossing comparator circuit according to the embodiment of the invention.

FIG. 6 is a circuit diagram of a comparator in a calibration phase according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of the comparator in the comparison stage according to the embodiment of the present invention.

In the drawings, the names of the parts corresponding to the reference numerals are as follows:

10-signal input module, 20-driving module, 30-storage module and 40-inverter.

Detailed Description

The present invention is further illustrated by the following figures and examples, which include, but are not limited to, the following examples.

A self-calibration zero-crossing detection comparator is used for comparing voltage drops at two ends of a synchronous rectifier tube in a switching power supply and specifically comprises a signal input module 10, a driving module 20, a storage module 30 and an inverter 40. The signal input module 10 is connected with the driving module 20, the driving module 20 is connected with the storage module 30, and the storage module 30 is connected with the inverter 40.

As shown in fig. 1, the signal input module 10 is configured to receive voltages at two ends of the synchronous rectifier, obtain corresponding currents according to the received voltages at two ends of the synchronous rectifier, and output the currents to the driving module 20. The driving module 20 is used for converting the current input by the signal input module and transmitting the converted current to the storage module 30. The storage module 30 is used for storing a voltage corresponding to the current transmitted by the driving module 20, obtaining a dynamic voltage caused by the current, and outputting the dynamic voltage to the inverter 40. The inverter 40 is configured to flip according to the value of the dynamic voltage and send a flip signal to the flip-flop of the switching power supply.

Referring to fig. 2, in the boost switch power circuit, one end of the inductor is connected to an input power Vin, and the other end is connected to the sw terminal, which is a pin of the chip. The drain of the power tube NL is connected to the sw terminal, the source is grounded, the gate is connected to the output terminal of the pulse width modulation circuit, and the pulse width modulation circuit outputs a driving voltage gate1 for controlling the switching or closing of the power tube NL. When the driving voltage gate1 is 1, the power tube NL is on, and when the driving voltage gate1 is 0, the power tube NL is off. The source of the power tube NH is connected with the sw end, the drain is connected with the output voltage Vout, the grid is connected with the output end of the pulse width modulation circuit, and the pulse width modulation circuit outputs a driving voltage gate2 for controlling the switching or closing of the power tube NH. When the driving voltage gate2 is equal to 1, the power transistor NH is turned on, and when the driving voltage gate2 is equal to 0, the power transistor NH is turned off. The filter capacitor C is connected to the output voltage Vout. The non-inverting input end of the comparator is connected with the output voltage Vout, the inverting input end of the comparator is connected with the sw end, and the output end of the comparator is connected with the set end of the trigger and used for transmitting the flip signal comp to the trigger. The reset end R of the trigger is connected with the driving voltage gate2, and the output end is connected with zc. When the driving voltage gate2 is 0, zc is reset to 0, and the driving voltage gate2 is 1, the flip-flop outputs zc to 1 when the flip-flop signal comp is flipped from 0 to 1.

Referring to fig. 3, the pwm circuit periodically and alternately outputs a driving voltage gate1 and a driving voltage gate2 to turn on the power transistor NL and the power transistor NH, respectively. When the driving voltage gate1 is 1, the power tube NL is turned on, the inductor current IL rises, the sw end voltage is IL × RNL, IL is the inductor current, and RNL is the on-resistance of the power tube NL. When the driving voltage gate2 is equal to 1, the power transistor NH is turned on, the inductor current IL decreases, the sw end voltage is Vout + IL × RNH, IL is the inductor current, and RNH is the on-resistance of the power transistor NH. The comparator detects the voltage between the voltage Vsw of the sw end and the output voltage Vout, when the inductance current IL is reduced to 0, the voltage Vsw of the sw end is equal to the output voltage Vout, the comparator generates the inversion from 0 to 1, and the output zc of the trigger is set to 1. After receiving the inversion from 0 to 1 of zc, the pulse width modulator sets the driving voltage gate2 to 0, the power tube NH is turned off, the inductor current IL does not drop, and the trigger reset zc is reset to 0 while the driving voltage gate2 is set to 0. While the drive voltage gate1 remains at 0, the pwm controller sets the drive voltage gate1 to 1 again and begins the next switching cycle.

In the switching process, the zero-crossing comparator is matched with the pulse width modulator, the power tube NH is closed when the inductive current IL is reduced to 0, and the switching power supply operates in an asynchronous rectification state, so that the conversion efficiency of the switching power supply is improved. If the comparator has a larger offset voltage voff, the inductance will drop to-voff/RNH, the comparator will flip from 0 to 1, and then the NH is turned off, so that the conversion efficiency of the switching power supply will be lowered.

Referring to fig. 4, the signal input module 10 includes a transconductance amplifier GM1, a selection switch S1, and a selection switch S2. The non-inverting input terminal of the transconductance amplifier GM1 is connected to the output terminal of the synchronous rectifier through the selection switch S1, i.e. the non-inverting input terminal of the transconductance amplifier GM1 receives the output voltage Vout through the selection switch S1. The non-inverting input terminal of the transconductance amplifier GM1 is connected to the input terminal of the synchronous rectifier through the selection switch S2, i.e., the non-inverting input terminal of the transconductance amplifier GM1 receives the sw terminal voltage Vsw through the selection switch S2. The inverting input terminal of the transconductance amplifier GM1 is connected to the output terminal of the synchronous rectifier, i.e. the inverting input terminal of the transconductance amplifier GM1 receives the output voltage Vout, and the output terminal of the transconductance amplifier is connected to the driver module.

When the selection switch S1 is turned on and the selection switch S2 is turned off, the non-inverting input terminal and the inverting input terminal of the transconductance amplifier GM1 both receive the output voltage Vout, and the transconductance amplifier GM1 obtains a first current according to the output voltage Vout and outputs the first current to the driving module. When the selection switch S1 is turned off and the selection switch S2 is turned on, the non-inverting input terminal of the transconductance amplifier GM1 inputs the sw terminal voltage, the inverting input terminal of the transconductance amplifier GM1 inputs the output voltage Vout, and the transconductance amplifier GM1 obtains a second current according to the sw terminal voltage and the output voltage Vout and outputs the second current to the driving module 20.

The driving module 20 comprises an NMOS transistor N1, the source electrode of the NMOS transistor N1 is connected with the output end of the transconductance amplifier GM1, and the drain electrode of the NMOS transistor N1 is connected with the storage module 30; the gate of the NMOS transistor N1 is connected to a bias voltage VB for operating the NMOS transistor N1 in a common gate state, the NMOS transistor N1 converts the first current into a third current and transmits the third current to the memory module 30, and the memory module 30 stores the third current in the form of a voltage. The NMOS transistor N1 converts the second current into a fourth current.

The memory module comprises a PMOS transistor P1, a capacitor C1 and a selection switch S3. The source of the PMOS tube P1 is connected with the internal power supply of the switch power supply and the anode of the capacitor C1, the cathode of the capacitor C1 is connected with the grid of the PMOS tube P1 and the drain of the PMOS tube P1 through the selection switch S3, and the drain of the PMOS tube P1 is connected with the drain of the NMOS tube N1 and the inverter 40 through the selection switch S4.

The PMOS tube P1 works in a common-gate state, the capacitor C1 is used for storing voltage information of a third current, the difference value of the third current and a fourth current enables the drain voltage of the PMOS tube P1 to change, the dynamic voltage of the drain of the PMOS tube P1 is input into the inverter through the selection switch S4 by the PMOS tube P1, and the output of the inverter 40 is triggered to turn by the dynamic voltage of the drain of the PMOS tube P1.

The input end of the inverter 40 is connected with the anode of the capacitor C1 through the selection switch S5; the output terminal of the inverter 40 is connected to the set terminal of the flip-flop of the switching power supply. The inverter 40 inverts according to the dynamic voltage of the drain of the PMOS transistor P1, and transmits an inverted signal comp to the set terminal of the flip-flop of the switching power supply.

Referring to fig. 5, when the driving voltage gate2 is equal to 0, the power transistor NH is in the off state, and the comparator is operated in the calibration stage, and does not detect whether the current of the power transistor NH crosses zero. When the driving voltage gate2 is equal to 1, the power tube NH is turned on, and the comparator operates in the comparison stage, where the comparison detects whether the current of the power tube NH crosses zero.

Referring specifically to fig. 6, the comparator operates in the calibration phase. The selection switches S1, S3, S are turned on, and S2, S4 are turned off. The non-inverting input end and the inverting input end of the transconductance amplifier GM1 both receive an input voltage Vout, the input voltages Vout are mutually offset, and a first current with the offset voltage voff of the transconductance amplifier GM1 is output across the output end of the amplifier GM1, wherein the first current is GM × voff, and GM is a transconductance coefficient of the transconductance amplifier GM 1.

The bias voltage VB generates a bias current IB, the NMOS tube N1 works in a common-gate state, the first current is changed into a third current IB-gm voff through the NMOS tube N1, the third current simultaneously flows through the PMOS tube P1, the drain electrode and the gate electrode of the P1 are connected together through the selection switch S3, and the PMOS tube P1 is in a saturation region at the moment. Current formula according to saturation region

I is the drain current of PMOS transistor P1, i.e. the third current, k is the process parameter of PMOS transistor P1, vt is the threshold voltage of PMOS transistor P1, w and l are the width sum of PMOS transistor P1Long. The source-gate voltage of the PMOS pipe P1 can be obtained by substituting the formula

Since the selection switch S3 is turned on, the voltage across the capacitor C1 is equal to the source-gate voltage vgs of the PMOS transistor P1. The information of the offset voltage voff of the transconductance amplifier GM1 is converted into voltage information and stored on the capacitor C1. Due to the turn-off of the selection switch S4, the turn-on of the selection switch S5, the input terminal of the inverter 40 is connected to the internal power source through the selection switch S5, and the inverted signal comp of the output of the inverter 40 is 0.

Referring to fig. 7, the comparator operates in the comparison phase. The selection switches S1, S3, and S5 are turned off, and the selection switches S2 and S4 are turned on. Non-inverting input terminal of transconductance amplifier GM1_swThe voltage at the end, the inverting input terminal of the transconductance amplifier GM1 receives the output voltage Vout, and the transconductance amplifier GM1 outputs the second current GM (Vsw-Vout + voff) in combination with the offset voltage voff of the transconductance amplifier GM 1. The NMOS transistor N1 operates in the common gate state, and the drain current of the NMOS transistor N1 is IB-gm (Vsw-Vout + voff), i.e., the fourth current. Since the selection switch S3 is in the off state, the voltage of the capacitor C1 is still at the voltage vgs in the calibration phase, so the source-gate voltage of the PMOS transistor P1 is also vgs. Current formula according to saturation region

The drain current of PMOS transistor P1 is IB-gm voff, and voltage vgs is reduced to a current with offset voltage voff information by PMOS transistor P1.

At the beginning of the comparison phase, Vsw is greater than the output voltage Vout, and at this time, the drain current IB-gm (Vsw-Vout + voff) of the NMOS transistor N1 is smaller than the drain current IB-gm voff of the PMOS transistor P1, the drain voltage of the PMOS transistor P1 starts to decrease, and due to the conduction of the select switch S4, the select switch S5 is turned off, and the dynamic voltage at the drain of the PMOS transistor P1 is transmitted to the input terminal of the inverter 40 through the select switch S4.

When the drain current IB-gm (Vsw-Vout + voff) of the NMOS transistor N1 is equal to the drain current IB-gm voff of the PMOS transistor P1, i.e., Vsw is equal to Vout, the dynamic voltage value is equal to the inversion threshold of the inverter 40, and the inversion signal output by the inverter 40 is inverted from 0 to 1. It can be seen that the switching threshold of the comparator is Vsw ═ Vout, and when the inductor current IL crosses zero, the term of the offset voltage voff of the transconductance amplifier GM1 is cancelled, so that the zero-crossing detection is more accurate.

The self-calibration zero-crossing detection comparator of the invention is divided into two stages of calibration and comparison when in work, and the offset voltage voff information of the transconductance amplifier GM1 is converted into voltage vgs to be stored on the storage unit 30 in the calibration stage; in the comparison stage, vgs forms a current IB-GM + voff with an offset voltage voff on the PMOS transistor P1, and compares the current IB-GM (Vsw-Vout + voff) with a current IB-GM generated by the transconductance amplifier GM1 receiving the voltage across the synchronous rectifier, and since the inductive current crosses zero when Vsw is Vout, the synchronous rectifier is turned off, thereby improving the conversion efficiency of the switching power supply. When Vsw is Vout, the offset voltage voff term of the comparator is cancelled, and zero-crossing detection is not affected, so that the purpose of the invention is achieved by reducing the offset voltage voff, and the zero-crossing detection is more accurate.

The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, but all changes that can be made by applying the principles of the present invention and performing non-inventive work on the basis of the principles shall fall within the scope of the present invention.

Claims

1. A self-calibration zero-crossing detection comparator is used for comparing voltage drops at two ends of a synchronous rectifier tube in a switching power supply, and is characterized by comprising a signal input module (10), a driving module (20) connected with the signal input module (10), a storage module (30) connected with the driving module (20) and an inverter (40) connected with the storage module (30);

the signal input module (10) is used for receiving voltages at two ends of the synchronous rectifier tube, obtaining corresponding current according to the received voltages at the two ends of the synchronous rectifier tube and outputting the current to the driving module (20); the driving module (20) is used for converting the current input by the signal input module (10) and transmitting the current to the storage module (30); the storage module (30) is used for storing a voltage corresponding to the current transmitted by the driving module (20), obtaining a dynamic voltage caused by the current and outputting the dynamic voltage to the inverter (40); the inverter (40) is used for generating overturn according to the value of the dynamic voltage and sending an overturn signal to a trigger of the switching power supply.

2. The self-calibrating zero-crossing detection comparator as claimed in claim 1, characterized in that the signal input module (10) comprises a transconductance amplifier GM1, a selection switch S1 and a selection switch S2;

the non-inverting input end of the transconductance amplifier is connected with the output end of the synchronous rectifying tube through a selection switch S1, the non-inverting input end of the transconductance amplifier GM1 is connected with the input end of the synchronous rectifying tube through a selection switch S2, the inverting input end of the transconductance amplifier GM1 is connected with the output end of the synchronous rectifying tube, and the output end of the transconductance amplifier GM1 is connected with the driving module (20);

when the selection switch S1 is turned on and the selection switch S2 is turned off, the non-inverting input terminal and the inverting input terminal of the transconductance amplifier are both connected to the output terminal voltage of the synchronous rectifier tube, and the transconductance amplifier obtains a first current according to the output terminal voltage of the synchronous rectifier tube and outputs the first current to the driving module; when the selection switch S1 is turned off and the selection switch S2 is turned on, the non-inverting input terminal of the transconductance amplifier GM1 inputs the input terminal voltage of the synchronous rectifier tube, the inverting input terminal of the transconductance amplifier GM1 inputs the output terminal voltage of the synchronous rectifier tube, and the transconductance amplifier GM1 obtains a second current according to the input terminal voltage and the output terminal voltage of the synchronous rectifier tube and outputs the second current to the driving module (20).

3. The self-calibrating zero-crossing detection comparator as claimed in claim 2, wherein the driving module comprises an NMOS transistor N1;

the source electrode of the NMOS tube N1 is connected with the output end of the transconductance amplifier GM 1; the drain electrode of the NMOS tube N1 is connected with the storage module (30); the gate of the NMOS transistor N1 is connected with a bias voltage VB;

the bias voltage VB is used for enabling the NMOS tube N1 to work in a common-gate state, the NMOS tube N1 is used for converting the first current into a third current and transmitting the third current to the storage module (30), and the second current is converted into a fourth current; the third current is stored as a voltage on the memory module (30).

4. A self-calibrating zero-crossing detection comparator as claimed in claim 3, characterized in that the storage module (30) comprises a PMOS transistor P1, a capacitor C1 and a selection switch S3;

the source electrode of the PMOS tube P1 is connected with the internal power supply of the switch power supply and the anode of the capacitor C1, the cathode of the capacitor C1 is connected with the grid electrode of the PMOS tube P1 and is connected with the drain electrode of the PMOS tube P1 through the selection switch S3;

the PMOS tube P1 works in a common-gate state, and the capacitor C1 is used for storing voltage information corresponding to the third current.

5. The self-calibrating zero-crossing detection comparator as claimed in claim 4, wherein the drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and to the inverter through a selection switch S4;

wherein, the difference value of the third current and the fourth current causes the drain voltage of the PMOS pipe P1 to change, the dynamic voltage of the drain of the PMOS pipe P1 is input to the inverter by the PMOS pipe P1 through the selection switch S4, and the output of the inverter (40) is triggered to turn by the dynamic voltage of the drain of the PMOS pipe P1.

6. A self-calibrating zero-crossing detection comparator as claimed in claim 4, characterized in that the input of the inverter (40) is connected to the positive pole of a capacitor C1 via a selection switch S5; the output end of the phase inverter (40) is connected with the position end of a trigger of the switching power supply;

the inverter (40) inverts according to the dynamic voltage of the drain electrode of the PMOS pipe P1 and transmits an inversion signal to a setting end of a trigger of the switching power supply.