CN109660109B - Self-adaptive zero-crossing detection circuit suitable for switching power supply - Google Patents
Self-adaptive zero-crossing detection circuit suitable for switching power supply Download PDFInfo
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- CN109660109B CN109660109B CN201811473289.3A CN201811473289A CN109660109B CN 109660109 B CN109660109 B CN 109660109B CN 201811473289 A CN201811473289 A CN 201811473289A CN 109660109 B CN109660109 B CN 109660109B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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Abstract
The invention discloses a self-adaptive zero-crossing detection circuit suitable for a switching power supply, which comprises an up-down counter, an offset voltage dynamic regulation circuit and a zero-crossing comparator, wherein the up-down counter is connected with the offset voltage dynamic regulation circuit, the offset voltage dynamic regulation circuit is connected with the zero-crossing comparator, the zero-crossing comparator is connected with a control end of the switching power supply and the up-down counter, and the up-down counter is used for performing up-down counting and outputting a logic signal according to a zero-crossing detection signal output by the zero-crossing comparator; the offset voltage dynamic adjusting circuit is used for receiving the logic signal output by the up-down counter and converting the logic signal into offset voltage; the zero-crossing comparator is used for outputting a zero-crossing detection signal according to the voltage of the common end of the power tube and the synchronous rectifier tube of the switching power supply and the magnitude of the offset voltage output by the offset voltage dynamic adjusting circuit. The invention can simultaneously eliminate the influence of random imbalance and time delay of the zero-crossing comparator and accurately detect the reverse current of the switching power supply.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a self-adaptive zero-crossing detection circuit suitable for a switching power supply.
Background
In order to improve the conversion efficiency of the switching power supply, the switching power supply generally adopts a synchronous rectification structure, namely, a synchronous rectification transistor replaces a traditional diode to finish the rectification of the inductive current. However, when the output load is small, the inductor current will be reversed to cause energy loss, and for this reason, a zero-crossing detection circuit is required to detect the reverse current of the synchronous rectification transistor. When the zero-crossing detection circuit detects the current reversal of the synchronous rectifier tube, the zero-crossing detection circuit sends a signal to turn off the synchronous rectifier transistor so as to prevent the current reversal. However, due to the influence of semiconductor manufacturing process deviation, ambient temperature and operating voltage, the zero-cross detection circuit has random input offset voltage and time delay, which causes the time from the detection of the reverse current by the zero-cross detection circuit to the signal generation to turn off the synchronous rectification transistor to be inaccurate: (1) when the turn-off time of the synchronous rectification transistor is too early, the inductive current continues current by depending on the body diode of the synchronous rectification transistor, and larger body diode loss is generated; (2) when the turn-off time of the synchronous rectifier transistor is too late, the inductive current is reversed, and the loss is increased; meanwhile, the common end (SW) of the power tube and the synchronous rectification transistor has large ringing voltage, so that the voltage stress of the transistor and the inductor is increased, the loss of the power tube is aggravated, and the EMI problem is introduced; accurate zero-crossing detection circuitry is therefore required to turn off the synchronous rectification transistors in time to reduce power loss, device stress and EMI problems.
In current applications, switching power supplies are developed towards high voltage, high frequency and large current. In high-voltage application, the change rate of the inductive current is higher, and higher requirements are put forward on the reaction speed of the zero-crossing detection circuit; in high-frequency application, the switching period is shortened, the zero-crossing detection circuit needs extra blanking time, and higher requirements are also put forward on the reaction speed of the zero-crossing detection circuit; in large-current application, the body diode loss and the inductive current in the asynchronous state are reversed, so that the efficiency of the converter is reduced, and higher requirements are provided for the precision of a zero-crossing detection circuit.
In the prior art, the zero-crossing detection precision is increased by amplifying the common end (SW) voltages of a power tube and a synchronous rectification transistor according to a certain proportion and then connecting the amplified common end (SW) voltages to the input end of a zero-crossing detection circuit or adjusting the time delay of an output signal of the zero-crossing detection circuit. The voltage of a common terminal (SW) of the power tube and the synchronous rectifier transistor is amplified according to a certain proportion and then is connected to the input end of the zero-crossing comparator, so that the influence of the delay of the zero-crossing detection circuit on the zero-crossing detection precision is only reduced, the response speed of the zero-crossing detection circuit can be accelerated, but the influence of the offset of the zero-crossing detection circuit cannot be eliminated; the zero-crossing detection circuit adjusts the output signal delay to increase the zero-crossing detection precision, can reduce the influence of the offset of the zero-crossing detection circuit to a certain extent, but cannot reduce the influence of the delay of the zero-crossing detection circuit. Therefore, the prior art cannot simultaneously eliminate the influence of the misadjustment and the time delay of the zero-crossing detection circuit, cannot obtain an accurate zero-crossing detection circuit, and cannot be applied to high-voltage high-frequency large-current design.
The above background disclosure is only for the purpose of assisting understanding of the concept and technical solution of the present invention and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.
Disclosure of Invention
In order to solve the technical problems, the invention provides a self-adaptive zero-crossing detection circuit suitable for a switching power supply, which can simultaneously eliminate the influences of random misadjustment and time delay of a zero-crossing comparator and accurately detect the reverse current of the switching power supply.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention discloses a self-adaptive zero-crossing detection circuit suitable for a switching power supply, wherein the switching power supply comprises a power tube and a synchronous rectifier tube, the self-adaptive zero-crossing detection circuit comprises an up-down counter, an offset voltage dynamic regulation circuit and a zero-crossing comparator, the output end of the up-down counter is connected with the input end of the offset voltage dynamic regulation circuit, the output end of the offset voltage dynamic regulation circuit is connected with the input end of the zero-crossing comparator, and the output end of the zero-crossing comparator is connected with the control end of the switching power supply and the input end of the up-down counter, wherein: the up-down counter is used for performing up-down counting according to the zero-crossing detection signal output by the zero-crossing comparator and outputting a logic signal; the offset voltage dynamic adjusting circuit is used for receiving the logic signal output by the up-down counter and converting the logic signal into an offset voltage; the zero-crossing comparator is used for outputting the zero-crossing detection signal according to the voltage of the common end of the power tube and the synchronous rectifying tube and the magnitude of the offset voltage output by the offset voltage dynamic adjusting circuit.
Preferably, a positive input end of the zero-crossing comparator is connected to a common end of the power tube and the synchronous rectifier tube, and a negative input end of the zero-crossing comparator is connected to an output end of the offset voltage dynamic adjusting circuit; therefore, the zero-crossing comparator can collect the voltage of the common end of the power tube and the synchronous rectifier tube and can also collect the offset voltage output by the offset voltage dynamic adjusting circuit.
Preferably, when the current of the synchronous rectifier tube is reversed, the positive terminal voltage of the zero-crossing comparator is greater than the negative terminal voltage, and the zero-crossing detection signal is at a high level; when the current of the synchronous rectifier tube is in the positive direction, the positive end voltage of the zero-crossing comparator is smaller than the negative end voltage, and the zero-crossing detection signal is in a low level; the up-down counter is supplied with an input signal for up-down counting by outputting a high level or a low level.
Preferably, the offset voltage dynamic adjustment circuit adopts a digital-to-analog conversion circuit; the logic circuit is used for converting the code value of the logic signal output by the up-down counter into the offset voltage of the negative end of the zero-crossing comparator.
Preferably, the adaptive zero-crossing detection circuit further includes an inverter and a D flip-flop, the inverter and the D flip-flop are connected between the output end of the zero-crossing comparator and the input end of the up-down counter, the input end of the inverter is connected to the output end of the zero-crossing comparator, the output end of the inverter is connected to the clock end of the D flip-flop and the control end of the switching power supply, and the positive output end of the D flip-flop is connected to the input end of the up-down counter; the zero-crossing detection signal output by the zero-crossing comparator is converted into a signal which can be collected and applied by an up-down counter through an inverter and a D trigger.
Preferably, when the zero-crossing detection signal output by the zero-crossing comparator is at a high level, the output signal of the positive output terminal of the D flip-flop is kept unchanged; when the zero-crossing detection signal output by the zero-crossing comparator is at a low level, setting the output signal of the positive output end of the D trigger to be 1 at the rising edge of the output signal of the inverter; the output signal is kept unchanged or set to 1, so that the up-down counter correspondingly performs up-down counting.
Preferably, the up-down counter samples the output signal of the positive output terminal of the D flip-flop at a rising edge of its clock signal, and when the output signal of the positive output terminal of the D flip-flop is at a low level, the up-down counter is decremented by 1; when the output signal of the positive output end of the D trigger is in a high level, the up-down counter is increased by 1; by setting the output signal to low level or high level, the up-down counter is decreased by 1 or increased by 1, so that a logic signal can be further output.
Preferably, the hold control signal terminal of the up-down counter receives the control signal of the switching power supply to control the effective time of the up-down counter for performing the up-down processing, and when the hold control signal of the up-down counter is at a high level, the up-down counter does not perform the up-down operation; when the holding control signal of the up-down counter is in a low level, the up-down counter performs up-down operation; the effective time of the addition and subtraction processing of the addition and subtraction counter is effectively controlled through the step, and the calculation efficiency of the self-adaptive zero-crossing detection circuit is improved.
Compared with the prior art, the invention has the beneficial effects that: the invention adopts the self-adaptive zero-crossing detection circuit to detect the reverse current of the switching power supply, utilizes the voltage of the common end of the power tube and the synchronous rectifier tube, utilizes the addition and subtraction counter and the offset voltage dynamic regulation circuit to self-adaptively regulate the precision of the zero-crossing detection circuit, can simultaneously reduce the influence of the offset and the time delay of the zero-crossing detection circuit on the precision of the zero-crossing detection, accurately detect the reverse current of the switching power supply, meet the application requirement of high voltage, high frequency and large current, and simultaneously reduce the influence of the loss of a converter, EMI, the stress of a transistor and the like.
Drawings
FIG. 1 is a block diagram of a buck switching power supply architecture with reverse current detection;
FIG. 2 is a functional block diagram of an adaptive zero crossing detection circuit in accordance with a preferred embodiment of the present invention;
fig. 3 is a logic timing diagram of an adaptive zero crossing detection circuit in accordance with a preferred embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and preferred embodiments.
Fig. 1 is a block diagram of a power architecture of a buck switching power supply with reverse current detection, which is a scenario of an adaptive zero-crossing detection circuit according to a preferred embodiment of the present invention, where the switching power supply includes a power tube HSPMOS, a synchronous rectifier LSNMOS, a first inverter 101, a loop control logic circuit 102, a loop PWM comparator, a loop error amplifier circuit EA, an internal oscillator circuit osc, a first and gate 103, a second and gate 104, a first nand gate 105, a second nand gate 106, and an adaptive zero-crossing detection circuit 200, a common terminal of the power tube HSPMOS and the synchronous rectifier LSNMOS is a SW terminal, the SW terminal is connected to a switching power converter output voltage Vout, another terminal of the power tube HSPMOS is connected to an input voltage signal Vin, and another terminal of the synchronous rectifier LSNMOS is connected to a reference GND; a driving signal HSDRV of the power tube HSPMOS is connected with an output end of a first inverter 101, an input end of the first inverter 101 is connected with a loop control logic circuit 102, the loop control logic circuit 102 is connected with an output end of a loop pulse width modulation comparator PWM (a loop pulse width modulation signal PWM output by the loop pulse width modulation comparator PWM is input to the first inverter 101 through the loop control logic circuit 102), a positive end of the loop pulse width modulation comparator PWM is connected with an output end of a loop error amplifier circuit EA, a negative end of the loop pulse width modulation comparator PWM is connected with an internal oscillator circuit osc, and the internal oscillator circuit osc receives a loop switching frequency signal clk and generates a ramp signal Vramp to be output to the negative end of the loop control logic circuit 102; the positive end of the loop error amplifier circuit EA is connected with an internal reference voltage Vref, the negative end of the loop error amplifier circuit EA is connected with a voltage division feedback signal Vfb of the output voltage of the switching power supply converter, and the voltage division feedback signal Vfb is generated by the output voltage Vout of the switching power supply converter and the ground reference voltage GND; the driving signal LSDRV of the synchronous rectifier tube LSNMOS is connected with the output end of the first AND gate 103, the first input end of the first AND gate 103 is connected with the output end of the first inverter 101, the second input end is connected with the output end of the second NAND gate 106, the first input end of the second NAND gate 106 is connected with the output end of the first NAND gate 105, the second input end is connected with the output end of the second AND gate 104, the first input end of the first NAND gate 105 is connected with the output end of the first inverter 101, the second input end is connected with the output end of the second NAND gate 106, the first input end of the second AND gate 104 is connected with the self-adaptive zero-crossing detection circuit 200, and the second input end is connected with the driving signal HSDRV.
As shown in fig. 2, the adaptive zero-crossing detection circuit 200 of the preferred embodiment of the present invention includes a zero-crossing comparator 201, an offset voltage dynamic adjustment circuit 202, the output end of the zero-crossing comparator 201 is connected with the input end of the second inverter 204, the positive end is connected with the SW end, the negative end is connected with the output end of the offset voltage dynamic adjusting circuit 202, the input end of the offset voltage dynamic adjusting circuit 202 is connected with the output end of the up-down counter 203, the input end of the up-down counter 203 is connected with the positive output end of the D flip-flop 205, the output end of the second inverter 204 is connected with the clock end of the D flip-flop, the input end of the D flip-flop 205 is connected with the internal logic high level VDD, and the reset end is connected with the driving signal HSDRV of the power tube HSPMOS (the driving signal HSDRV of the power tube HSPMOS periodically resets the output signal UD of the D flip-flop 205). In addition, Hold control signal Hold terminal of the up-down counter 203 is connected to the output terminal of the first nand gate 105.
The working principle of the self-adaptive zero-crossing detection circuit 200 of the preferred embodiment of the present invention is as follows: the negative end of the zero-crossing comparator 201 is connected with the output end of the offset voltage dynamic adjusting circuit 202, and the dynamic adjusting voltage of the negative end is offset voltage Voff output by the offset voltage dynamic adjusting circuit 202 and superimposed on the basis of GND; when the current of the synchronous rectifier tube LSNMOS is reversed, the voltage of the positive end of the zero-crossing comparator 201 is higher than that of the negative end, the zero-crossing comparator 201 outputs a high level, and an output signal UD of the positive output end of the D flip-flop remains unchanged; when the current of the synchronous rectifier tube LSNMOS is positive, the positive terminal voltage of the zero-crossing comparator 201 is lower than the negative terminal voltage, the zero-crossing comparator 201 outputs a low level, the output signal UD of the positive output terminal of the D flip-flop is set to 1 at the rising edge of the output signal zcd of the second inverter 204 (i.e., an effective output signal obtained after the output signal of the zero-crossing comparator 201 passes through the second inverter 204), and UD becomes a logic high level. The up-down counter 203 realizes up-down counting and changes code values of logic signals D0-D7; the up-down counter 203 samples the voltage of the output signal UD at the positive output terminal of the D flip-flop at the rising edge of the clock signal udclk, and when the rising edge of udclk samples UD is low, the up-down counter 203 decrements by 1, whereas when the rising edge of udclk samples UD is high, the up-down counter 203 increments by 1. The Hold control signal Hold of the up/down counter 203 controls the active time of the up/down counter 203, when Hold is high, the up/down counter 203 does not perform the up/down operation, the code values of the output logic signals D0 to D7 remain unchanged, and when Hold is low, the up/down counter 203 performs the up/down counting according to the sampling signal along the rising edge of the clock signal udclk. The offset voltage dynamic adjustment circuit 202 adopts a digital-to-analog converter to convert the code values of the logic signals D0-D7 output by the up-down counter 203 into the offset voltage Voff at the negative end of the zero-crossing comparator 201, wherein the offset voltage Voff increases when the code values of the logic signals D0-D7 output by the up-down counter 203 increase, and the offset voltage Voff decreases when the code values of the logic signals D0-D7 output by the up-down counter 203 decrease; and the signals among the zero-crossing comparator 201, the offset voltage dynamic adjusting circuit 202 and the up-down counter 203 are self-adaptively adjusted until an accurate zero-crossing detection signal is obtained.
As shown in fig. 3, which is a timing chart of main signals of the adaptive zero-crossing detection circuit according to the preferred embodiment of the present invention, when the inductor current IL has not yet decreased to zero due to the detuning and delay of the zero-crossing comparator 201, the active output signal zcd of the zero-crossing comparator 201 changes from high to low, indicating that there is an inductor current IL reversal at this time, turning off the synchronous rectifier LSNMOS, the inductor current IL freewheeling through the body diode of the synchronous rectifier LSNMOS, the voltage at the SW terminal is about-0.7V, zcd changes from low to high, the output signal UD at the forward output terminal of the D flip-flop is set to 1, and UD changes to a logic high level; meanwhile, the Hold control signal Hold of the up-down counter 203 changes from high to low, and the up-down counter 203 no longer holds; the rising edge sample UD of the clock signal udclk of the up-down counter 203 is at a high level, the up-down counter 203 outputs code values D0-D7 plus 1, and the code values D0-D7 increase the offset voltage Voff at the negative end of the zero-crossing comparator after passing through the offset voltage dynamic adjustment circuit 202. When the inductor current IL drops to zero, the voltage at the SW terminal rises from-0.7V to the output voltage Vout, and the active output signal zcd of the zero-crossing comparator goes from high to low again. This process continues with a gradual increase in Voff until accurate reverse current detection is achieved. When the inductor current IL has decreased to a negative value, the active output signal zcd of the zero-crossing comparator 201 changes from high to low, indicating that there is an inductor current IL reversal, turning off the synchronous rectifier LSNMOS; at this time, the voltage at the SW terminal rises rapidly, zcd is kept at low level, the UD signal is kept at low level, the rising edge of the clock signal udclk of the up-down counter 203 samples UD at low level, the up-down counter 203 outputs code values D0 to D7 and 1, and the code values D0 to D7 pass through the offset voltage dynamic adjustment circuit 202, and then the negative offset voltage Voff of the zero-crossing comparator is reduced. This process continues with a gradual decrease in Voff until accurate reverse current detection is achieved. Therefore, the self-adaptive zero-crossing detection circuit of the preferred embodiment of the invention can eliminate the influence of random misadjustment and time delay of the zero-crossing comparator at the same time and accurately detect the reverse current of the switching power supply.
The self-adaptive zero-crossing detection circuit of the preferred embodiment of the invention has the advantages that the input voltage range is 4-14V and the output voltage range is 3-4.5V within the temperature range of-40-125 ℃, and accurate reverse current detection can be obtained through transient simulation verification of all process corners.
The above preferred embodiment is an example in which the adaptive zero-cross detection circuit is applied to a buck-type switching power supply, and the adaptive zero-cross detection circuit of the preferred embodiment of the present invention is also applicable to a boost-type switching power supply and a buck-type switching power supply, and the working principle of the adaptive zero-cross detection circuit is the same as that described above, and is not described herein again.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.
Claims (4)
1. The self-adaptive zero-crossing detection circuit is characterized by comprising an up-down counter, a digital-to-analog converter, a second phase inverter, a D trigger and a zero-crossing comparator, wherein the output end of the up-down counter is connected with the input end of the digital-to-analog converter, the output end of the digital-to-analog converter is connected with the negative input end of the zero-crossing comparator, the positive input end of the zero-crossing comparator is connected with the common end of the power tube and the synchronous rectifier, the output end of the zero-crossing comparator is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the control end of the switching power supply and the clock end of the D trigger, and the input end of the up-down counter is connected with the positive output end of the D trigger, the input end and the reset end of the D flip-flop are respectively connected with a high level and a driving signal of the power tube, and the driving signal periodically resets an output signal UD of the D flip-flop; wherein:
the up-down counter is used for performing up-down counting according to the output signal UD and outputting a code value; the digital-to-analog converter is used for converting the code value into an offset voltage; the zero-crossing comparator is used for outputting the zero-crossing detection signal according to the voltage of the common end and the offset voltage; an effective output signal zcd is obtained after the zero-crossing detection signal passes through the second inverter; when the inductive current has not decreased to zero, the active output signal zcd goes from high to low, turning off the synchronous rectifier, freewheeling the inductive current through the body diode of the synchronous rectifier, the active output signal zcd goes from low to high, the output signal UD of the D flip-flop is set to 1, meanwhile, the hold control signal of the up-down counter goes from high to low, the up-down counter no longer holds, the clock signal rising edge of the up-down counter samples the output signal to high, and the up-down counter output code value is increased by 1.
2. The adaptive zero-crossing detection circuit according to claim 1, wherein when the zero-crossing detection signal output by the zero-crossing comparator is high level, the output signal of the positive output terminal of the D flip-flop is kept unchanged.
3. The adaptive zero-crossing detection circuit according to claim 1, wherein the up-down counter samples the output signal of the positive output terminal of the D flip-flop at a rising edge of a clock signal thereof, and the up-down counter is decremented by 1 when the output signal of the positive output terminal of the D flip-flop is at a low level.
4. An adaptive zero-crossing detection circuit according to any one of claims 1 to 3, wherein the hold control signal terminal of the up-down counter receives a control signal of the switching power supply to control the active time of the up-down counter for performing the up-down process, and when the hold control signal of the up-down counter is at a high level, the up-down counter does not perform the up-down operation.
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| CN111208343B (en) * | 2020-01-14 | 2022-05-10 | 上海南芯半导体科技股份有限公司 | Self-calibration zero-crossing detection comparator |
| CN111458559A (en) * | 2020-04-26 | 2020-07-28 | 电子科技大学 | Self-adaptive zero-crossing detection circuit |
| CN111711344B (en) * | 2020-06-18 | 2024-05-07 | 拓尔微电子股份有限公司 | Self-calibration zero-crossing detection circuit of switching power supply |
| CN114137463B (en) * | 2020-10-12 | 2024-03-19 | 上海富芮坤微电子有限公司 | Automatic calibration device and calibration method for zero crossing point detection circuit of switching power supply |
| CN114878901A (en) * | 2022-05-24 | 2022-08-09 | 重庆邮电大学 | DC-DC zero-crossing current detection circuit capable of eliminating offset voltage influence of comparator |
| CN115436689B (en) * | 2022-09-23 | 2023-09-01 | 陕西省电子技术研究所有限公司 | Null position testing device based on double operational amplifiers and Hall current sensors |
| CN117491724B (en) * | 2024-01-02 | 2024-04-05 | 江苏展芯半导体技术股份有限公司 | Inductance current zero-crossing detection method and circuit |
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| CN103616556A (en) * | 2013-11-22 | 2014-03-05 | 矽力杰半导体技术(杭州)有限公司 | Zero-cross detection circuit and detection method used for synchronous buck converter |
| CN106877653A (en) * | 2017-04-14 | 2017-06-20 | 东南大学 | The circuit and its method of a kind of DCM switching power converters controlling dead error time |
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