CN114675073A - Closed-loop self-adaptive zero-crossing detection circuit suitable for BOOST type switching power supply - Google Patents
Closed-loop self-adaptive zero-crossing detection circuit suitable for BOOST type switching power supply Download PDFInfo
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Abstract
The invention relates to a closed-loop self-adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply, which comprises a state detector, a state encoder, an up-down counter, a digital-to-analog converter and a comparator which are sequentially connected, wherein the state encoder comprises a delay circuit, a first trigger and a second trigger which are connected with the delay circuit, and a first AND gate, a second AND gate and a third AND gate which are connected with the first trigger, and the first AND gate, the second AND gate and the third AND gate are all connected with the second trigger. The invention adopts the closed-loop self-adaptive zero-crossing detection circuit to detect the inductive current in the switching power supply, samples the current of the synchronous rectifier tube, utilizes the reference voltage of the state detector, the state encoder, the up-down counter and the digital-to-analog converter automatic state regulation comparator, and self-adaptively and accurately detects the inductive zero-crossing signal, reduces the influence on the zero-crossing detection caused by delay or circuit maladjustment, thereby reducing the power consumption of the switching power supply and increasing the system efficiency.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a closed-loop self-adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply.
Background
Most of the existing BOOST type switching power converters use a synchronous rectification structure, and compared with an asynchronous rectification structure, the BOOST type switching power converters can reduce power consumption caused by a freewheeling diode and improve system efficiency. In the application of the synchronous BOOST converter, when a system is in a heavy load state, the inductive current works in a CCM mode, the current cannot be reduced to zero in a working period, and the conduction loss of the synchronous rectifier tube is low due to low conduction impedance; when the system is in a light load state, the inductive current works in a DCM mode, the current can be reduced to zero, and if the synchronous rectifier tube is not turned off timely, the current backflow phenomenon can be caused, and the performance of the system is influenced. Therefore, a zero-crossing detection unit is needed in the synchronous rectification structure, so that the synchronous rectification tube is timely turned off when the inductive current is zero. However, due to the influence of offset voltage caused by the delay of the converter, the offset of the comparator and some parasitic parameters, the signal generated by the zero-crossing detection circuit cannot play a role of closing the synchronous rectifier tube when the inductor flows to zero, which causes some defects: 1) when the synchronous rectifier tube is turned off late, the current flows backward, and the reverse current flows through the substrate of the synchronous rectifier tube to cause extra loss; 2) when the synchronous rectifier tube is turned off earlier, the inductor performs follow current through the body diode of the synchronous rectifier tube, so that larger body diode power consumption is caused; 3) the back-flow of current can also cause jitter in the input voltage, causing system instability.
The existing zero-crossing detection technology detects the state of an inductive current by sampling the SW end voltage, namely amplifying the SW end voltage and then connecting the amplified SW end voltage to the input end of a zero-crossing detection circuit, and the method reduces the time delay of the zero-crossing detection circuit but does not eliminate the influence of the maladjustment of the zero-crossing detection circuit; or the influence on the precision is reduced by reducing the delay time of the transmission of the output signal of the zero-crossing detection circuit, and the method does not consider the delay of the zero-crossing detection circuit; or the synchronous rectifier tube is turned off in advance according to the delay time tested in advance, and the method is only suitable for a specific circuit and cannot obtain the universal delay time.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a closed-loop self-adaptive zero-crossing detection circuit suitable for a BOOST switching power supply, which can eliminate the influence of various delays on the precision of the zero-crossing detection circuit while adjusting the offset of the zero-crossing detection circuit and can accurately detect the inductive current.
The invention provides a closed-loop self-adaptive zero-crossing detection circuit suitable for a BOOST type switching power supply, which comprises a state detector, a state encoder, an up-down counter, a digital-to-analog converter and a comparator which are sequentially connected, wherein the state encoder comprises a delay circuit, a first trigger and a second trigger which are connected with the delay circuit, and a first AND gate, a second AND gate and a third AND gate which are connected with the first trigger, and the first AND gate, the second AND gate and the third AND gate are all connected with the second trigger.
Further, an input end of the state detector is connected to the SW end of the BOOST type switching power supply, and an output end of the state detector is connected to the data input end of the first flip-flop and the data input end of the second flip-flop respectively.
Furthermore, the input end of the delay circuit is connected with the gate of the synchronous rectifier tube in the BOOST type switching power supply, the first output end of the delay circuit is connected with the clock input end of the first trigger, and the second output end of the delay circuit is connected with the clock input end of the second trigger.
Further, a first output end of the first trigger is connected to the first input end of the first and gate and the first input end of the second and gate, respectively, and a second output end of the first trigger is connected to the first input end of the third and gate.
Further, a first output end of the second trigger is connected to a second input end of the first and gate, and a second output end of the second trigger is connected to a second input end of the second and gate and a second input end of the third and gate, respectively.
Further, the output end of the first and gate, the output end of the second and gate and the output end of the third and gate are all connected with the up-down counter.
Furthermore, the inverting input end of the comparator is connected with the digital-to-analog converter, the non-inverting input end of the comparator is connected with a current/voltage conversion module, and the output end of the comparator is connected with a logic driving module in the BOOST type switching power supply.
Further, the current/voltage conversion module is connected to a drain of a synchronous rectifier in the BOOST-type switching power supply to convert a current of the synchronous rectifier into a voltage across the synchronous rectifier.
Further, the state detector is configured to detect a voltage at the terminal SW of the BOOST-type switching power supply and output a state signal; the state encoder is configured to encode the state signal and output an encoded signal; the up-down counter is set to count up and down the coded signal, convert the coded signal into a counting signal and output the counting signal; the digital-to-analog converter is arranged to convert the counting signal into a reference voltage and input the reference voltage to the inverting input end of the comparator; the comparator is configured to compare the reference voltage with voltages across the synchronous rectifier tube and output a zero crossing detection signal.
The invention adopts a closed-loop self-adaptive zero-crossing detection circuit to detect the inductive current in the switching power supply, samples the current of the synchronous rectifier tube, utilizes the reference voltage of the state detector, the state encoder, the up-down counter and the digital-to-analog converter automatic state regulation comparator to self-adaptively and accurately detect the inductive zero-crossing signal, and reduces the influence on the zero-crossing detection caused by delay or circuit maladjustment, thereby reducing the power consumption of the switching power supply and increasing the system efficiency.
Drawings
Fig. 1 is a topology of a BOOST type switching power converter.
Fig. 2 is a schematic block diagram of a closed-loop adaptive zero-crossing detection circuit suitable for a BOOST-type switching power supply according to the present invention.
Fig. 3 is a diagram illustrating a digital-to-analog conversion waveform of the reference voltage Vref in fig. 2.
Fig. 4(a) -4 (c) are operation timing diagrams of the closed-loop adaptive zero-crossing detection circuit for the BOOST-type switching power supply according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The closed-loop self-adaptive zero-crossing detection circuit provided by the invention is applied to a BOOST type switching power supply, and the BOOST type switching power supply comprises an input voltage Vin, an inductor L, a power tube M1, a synchronous rectifier tube M2 and a logic drive module DRIVER as shown in figure 1A load capacitor CLAnd a load resistor RL. One end of the inductor L is connected to the positive electrode of the input voltage Vin, and the other end is connected to the drain of the power transistor M1 and the drain of the synchronous rectifier transistor M2. Load capacitance CLOne end of the second diode is connected to the source of the synchronous rectifier M2, and the other end is grounded. Load resistance RLAnd a load capacitor CLIn parallel, i.e. load resistance RLOne end of the synchronous rectifier is also connected to the source of the synchronous rectifier M2, and the other end is grounded. The negative electrode of the input voltage Vin and the source of the power transistor M1 are both grounded. The grid of the power tube M1 and the grid of the synchronous rectifier tube M2 are set to be LG and UG respectively, and are connected with the output end of the logic driving module DRIVER. Meanwhile, the common connection point of the inductor L, the drain of the power tube M1 and the drain of the synchronous rectifier tube M2 is set as the SW end, and the load resistor R is setLThe voltage across is Vout.
As shown in fig. 2, the closed-loop adaptive zero-crossing detection circuit for a BOOST-type switching power supply of the present invention includes a state detector 1, a state encoder 2, an up-down counter 3, a digital-to-analog converter 4, and a comparator 5, which are connected in sequence. The state encoder 2 includes a delay circuit 21, a first flip-flop 22 and a second flip-flop 23 connected to the delay circuit 21, and a first and gate 24, a second and gate 25, and a third and gate 26 connected to the first flip-flop 22, and the first and gate 24, the second and gate 25, and the third and gate 26 are also connected to the second flip-flop 23.
Specifically, the input terminal of the state detector 1 is connected to the SW terminal of the BOOST-type switching power supply, and is configured to detect the voltage at the SW terminal of the switching power supply, and the output terminal of the state detector 1 outputs the state signal SWDET.
The state encoder 2 is arranged to encode the state signal SWDET output by the state detector 1 and to output an encoded signal. Specifically, the output terminal of the state detector 1 is connected to the data input terminal of the first flip-flop 22 and the data input terminal of the second flip-flop 23, respectively. The input terminal of the delay circuit 21 is connected to the gate UG of the synchronous rectifier M2, the first output terminal CLK1 is connected to the clock input terminal of the first flip-flop 22, and the second output terminal CLK2 is connected to the clock input terminal of the second flip-flop 23. First input of first flip-flop 22The output end P1 is respectively connected with a first input end of the first AND gate 24 and a first input end of the second AND gate 25, and a second output end
Then to the first input of the third and gate 26. The first output P2 of the second flip-flop 23 is connected to a second input of the first and-gate 24, the second output
Then to a second input of the second and-gate 25 and a second input of the third and-gate 26, respectively. The output terminal of the first and gate 24, the output terminal of the second and gate 25, and the output terminal of the third and gate 26 are connected to the up-down counter 3. The output ends of the first and gate 24, the second and gate 25 and the third and gate 26 are set to be Q1, Q2 and Q3 respectively, and then the state encoder 2 outputs encoding signals Q1/Q2/Q3.
The up-down counter 3 is configured to up-down count the encoded signal Q1/Q2/Q3 output from the state encoder 2, convert the encoded signal Q1/Q2/Q3 into count signals < C7-C0 >, and output the count signals < C7-C0 >.
The digital-to-analog converter 4 is arranged to count the signal<C7～C0>Converted to a reference voltage Vref, and input to the inverting input terminal of the comparator 5. The non-inverting input terminal of the comparator 5 is connected to a current/voltage (I/V) conversion module 6, and the I/V conversion module 6 is connected to the drain of the synchronous rectifier M2 for connecting the current I flowing through the synchronous rectifier M2M2Converted to a voltage VM2. A comparator 5 for comparing reference voltages Vref and VM2And outputs a zero-crossing detection signal ZCD, and the output end of the comparator 5 is connected with the logic drive module DRIVER of the switching power supply to control the on-off of the switching power supply through the zero-crossing detection signal ZCD. The principle that the zero-crossing detection signal ZCD controls the on-off of the switching power supply is as follows: when the rising edge of the output signal CLK1/CLK2 of the delay circuit 21 comes, when the current flowing through the synchronous rectifier M2 is a forward current, indicating that the turn-off time of the synchronous rectifier M2 is too early, the body diode current exists in the synchronous rectifier M2, and the zero-crossing detection signal ZCD output by the comparator 5 changes from low to high; when in useThe current flowing through the synchronous rectifier M2 is a reverse current, which indicates that the turn-off time of the synchronous rectifier M2 is too late, the current flows backward, and the zero-crossing detection signal ZCD output by the comparator 5 changes from high to low.
The working principle of the closed-loop self-adaptive zero-crossing detection circuit is as follows: when the zero-crossing turn-off signal of the synchronous rectifier tube M2 is too early, the voltage at the switch power supply SW is higher than a set high voltage threshold (the set high voltage threshold is between the input voltage Vin and the output voltage Vout of the switch power supply), and the output signal SWDET of the state detector 1 is at a high level; when the zero-crossing off signal of the synchronous rectifier tube M2 is too late, the voltage at the SW terminal is smaller than the set low-voltage threshold (the set low-voltage threshold is determined according to the input voltage Vin of the switching power supply), and the output signal SWDET of the state detector 1 is at a low level at this time. Delaying the rising edge of the gate signal UG of the synchronous rectifier tube M2 by Tdelay1 and Tdelay2(Tdelay 2), respectively>Tdelay1) to obtain pulse signals CLK1, CLK2 and output signals of the flip- flops 22, 23
Transitions (transitions from 1 to 0 or 0 to 1) occur at the rising edges of CLK1, CLK2, respectively, with the level of signal SWDET, and remain unchanged for the remainder of the time. Output signals of flip- flops 22, 23
The signals are transmitted to AND gates 24, 25 and 26, and are logically combined to obtain output signals Q1/Q2/Q3 of the state encoder 2. When the off time of the signal UG is too early, the output Q1 is high, and the counter 3 is incremented by 1; when the turn-off time of the signal UG is too late, the output Q3 is at a high level, and the counter 3 is decremented by 1; when the off-time of signal UG happens when the inductor current drops to zero, output Q2 is high and counter 3 remains unchanged. The DAC 4 is used to convert the data outputted from the counter 3 into the reference voltage Vref of the comparator 5, which is a binary number of 8 bits<C7：C0>When the value of (3) is increased, the reference voltage Vref is increased; when in use<C7：C0>When the value of (3) is decreased, the reference voltage Vref is decreased; when in use<C7：C0>The reference voltage Vref remains unchanged when the value of (d) is unchanged. The comparator 5 is used for converting the current of the synchronous rectifier tube M2 through I/VThe output voltage is compared with the reference voltage Vref output by the digital-to-analog converter 4, and a zero-crossing detection signal ZCD is output to the logic driving module DRIVER of the switching power supply to control the on/off of the switching tubes M1 and M2. According to the invention, an accurate zero-crossing detection signal is obtained through closed-loop self-adaptive adjustment of the state detector 1, the state encoder 2, the up-down counter 3, the digital-to-analog converter 4 and the comparator 5.
Fig. 3 is a diagram illustrating a digital-to-analog conversion waveform of the reference voltage Vref. It can be seen from the figure that, with the sampling detection of the SW terminal voltage by the state detector 1 and the output of the signal of the state encoder 2, the counter 3 performs the 1-subtracting operation, and meanwhile, the Vref gradually decreases with the value of the counter 3, the adaptive zero-crossing detection process continues until the zero-crossing signal of the circuit can be accurately detected, and finally, the Vref maintains and stabilizes near the Vm value, thereby completing the closed-loop adaptive zero-crossing detection process. After the continuous self-adaptive zero-crossing detection process is stable, the zero-crossing detection state is maintained to be switched back and forth between a little earlier and a little later, the reference voltage Vref is also correspondingly switched back and forth between increase and decrease near a certain fixed value, and the value is Vm.
Fig. 4(a) -fig. 4(b) are timing diagrams of the operation of the closed-loop adaptive zero-crossing detection circuit suitable for the BOOST-type switching power supply of the present invention. In fig. 4(a), when LG is high and UG is high, the inductor current charges, when LG and UG simultaneously go low, the inductor starts freewheeling and the voltage at SW jumps to Vout; inductive current ILUG goes high when not reducing to zero, the synchronous rectifier M2 is closed, the inductor L continues to discharge through a body diode of the synchronous rectifier M2 at the moment, the voltage of the SW end is about Vout +0.7V, rising edges of UG are delayed to obtain pulse signals CLK1 and CLK2, the state encoder 2 is triggered at rising edges of CLK1 and CLK2, the output Q1 is high, the counter 3 is added with 1, and the output Q1 is output<C7:C0>The value of the reference voltage Vref is transmitted to the digital-to-analog converter 4, the voltage of the SW end is maintained near Vin until the next inductor charging period, and the voltage is reduced to zero again; this process continues, increasing Vref, until a precise current status signal is obtained. In FIG. 4(b), the inductor current ILAfter the voltage drops to zero, the synchronous rectifier M2 is still not turned off, Vout charges the inductor L reversely, and the inductor is chargedThe flow IL decreases to a negative value; at the moment when the synchronous rectifier tube M2 is turned off, the voltage at the SW terminal suddenly drops from Vout to about-0.7V, and simultaneously the output signals CLK1 and CLK2 of the delay circuit 21 are obtained, after the rising edges of CLK1 and CLK2 are triggered and logically integrated, the output Q3 of the state encoder 2 is at a high level, the counter 3 is decremented by 1,<C7:C0>inputting the code value into a digital-to-analog converter 4, reducing the reference voltage Vref, stabilizing the SW terminal voltage near the Vin value until the next inductor charging period is reduced to zero again; this process continues, reducing Vref until a precise status signal is obtained. In FIG. 4(c), the synchronous rectifier M2 is just at the inductor current ILTurning off when the voltage drops to zero, and reducing the voltage of the SW end from Vout to Vin at the moment of UG turning-off until the voltage of the SW end drops to zero again in the next inductor charging period; the output Q2 of state encoder 2 is high, the value of counter 3 is unchanged, and the value of reference voltage Vref is also unchanged. Therefore, the closed-loop self-adaptive zero-crossing detection circuit realizes the precision adjustment of zero-crossing detection signals under all conditions, eliminates the influence of circuit delay or offset voltage, and enables the BOOST type switching power supply to accurately detect the inductive current.
The closed-loop self-adaptive zero-crossing detection circuit performs transient simulation, and can achieve the purpose under the conditions that the simulation temperature range is-40-125 ℃, the input voltage range is 2.1-5.5V, and the output voltage range is 6.5-10.5V, so that accurate state signals are obtained.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and various modifications may be made to the above-described embodiment of the present invention. For example, the principles of the present invention are equally applicable to BUCK-type or BUCK-BOOST type circuits. All simple and equivalent changes and modifications made according to the claims and the content of the specification of the present application fall within the scope of the claims of the present patent application. The invention has not been described in detail in order to avoid obscuring the invention.
Claims (9)
1. The closed-loop self-adaptive zero-crossing detection circuit is characterized by comprising a state detector, a state encoder, an up-down counter, a digital-to-analog converter and a comparator which are sequentially connected, wherein the state encoder comprises a delay circuit, a first trigger and a second trigger which are connected with the delay circuit, a first AND gate, a second AND gate and a third AND gate which are connected with the first trigger, and the first AND gate, the second AND gate and the third AND gate are all connected with the second trigger.
2. The closed-loop adaptive zero-crossing detection circuit for a BOOST-type switching power supply according to claim 1, wherein an input terminal of the status detector is connected to the SW terminal of the BOOST-type switching power supply, and an output terminal of the status detector is connected to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop respectively.
3. The closed-loop adaptive zero-crossing detection circuit for a BOOST type switching power supply according to claim 1, wherein an input terminal of the delay circuit is connected to a gate of a synchronous rectifier in the BOOST type switching power supply, a first output terminal of the delay circuit is connected to a clock input terminal of the first flip-flop, and a second output terminal of the delay circuit is connected to a clock input terminal of the second flip-flop.
4. The closed-loop adaptive zero-crossing detection circuit suitable for the BOOST-type switching power supply according to claim 1, wherein a first output terminal of the first flip-flop is connected to a first input terminal of the first and-gate and a first input terminal of the second and-gate, respectively, and a second output terminal of the first flip-flop is connected to a first input terminal of the third and-gate.
5. The closed-loop adaptive zero-crossing detection circuit suitable for the BOOST type switching power supply as claimed in claim 4, wherein a first output end of the second flip-flop is connected to a second input end of the first AND gate, and a second output end of the second flip-flop is respectively connected to a second input end of the second AND gate and a second input end of the third AND gate.
6. The closed-loop adaptive zero-crossing detection circuit suitable for the BOOST-type switching power supply according to claim 1, wherein the output end of the first and gate, the output end of the second and gate and the output end of the third and gate are connected to the up-down counter.
7. The closed-loop adaptive zero-crossing detection circuit for a BOOST-type switching power supply according to claim 1, wherein an inverting input terminal of the comparator is connected to the digital-to-analog converter, a non-inverting input terminal of the comparator is connected to a current/voltage conversion module, and an output terminal of the comparator is connected to a logic driving module in the BOOST-type switching power supply.
8. The closed-loop adaptive zero-crossing detection circuit for a BOOST-type switching power supply according to claim 7, wherein the current/voltage conversion module is connected to a drain of a synchronous rectifier in the BOOST-type switching power supply to convert a current of the synchronous rectifier into a voltage across the synchronous rectifier.
9. The closed-loop adaptive zero-crossing detection circuit for BOOST-type switching power supplies according to claim 8,
the state detector is arranged to detect the voltage of the BOOST type switch power supply SW end and output a state signal;
the state encoder is configured to encode the state signal and output an encoded signal;
the up-down counter is used for performing up-down counting on the coded signals, converting the coded signals into counting signals and outputting the counting signals;
the digital-to-analog converter is arranged to convert the count signal into a reference voltage and input the reference voltage to an inverting input of the comparator;
the comparator is configured to compare the reference voltage with voltages across the synchronous rectifier tube and output a zero crossing detection signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117937949A (en) * | 2024-03-20 | 2024-04-26 | 辰芯半导体（深圳）有限公司 | Zero-crossing detection circuit and DC-DC converter circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117937949A (en) * | 2024-03-20 | 2024-04-26 | 辰芯半导体（深圳）有限公司 | Zero-crossing detection circuit and DC-DC converter circuit |
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