CN110429801B - Chip control circuit based on SR technology and implementation method - Google Patents
Chip control circuit based on SR technology and implementation method Download PDFInfo
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- CN110429801B CN110429801B CN201910739511.8A CN201910739511A CN110429801B CN 110429801 B CN110429801 B CN 110429801B CN 201910739511 A CN201910739511 A CN 201910739511A CN 110429801 B CN110429801 B CN 110429801B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a chip control circuit based on SR technology and a realization method thereof, comprising comparators OP1, OP2, OP3, a Gate switch control circuit, a driver, a switch S and a current control circuit, wherein Vds is compared with threshold voltage through the comparators OP1 and OP2, so that the Gate switch control circuit outputs a control signal to the driver for controlling the switch of a MOS tube grid; in the process of secondary afterflow of the transformer, secondary current is gradually reduced, Vds is smaller and smaller, when Vds is smaller than a certain value, the comparator OP3 controls the switch S to be closed, the grid voltage of the MOS tube is reduced, meanwhile, the current control circuit controls the pull-down current of the MOS tube through the grid voltage of the MOS tube, Ron and the secondary current, the pull-down current is properly reduced, regulation and control are convenient, the problem of excessive adjustment when the grid voltage of the comparator OP3 is controlled is avoided, the power consumption of the whole circuit is reduced, the working efficiency of the circuit is improved, the comparator has the characteristic of quick response, and the regulation speed is improved.
Description
Technical Field
The invention relates to the technical field of synchronous rectification, in particular to a chip control circuit based on an SR technology and an implementation method.
Background
In a conventional AC-DC system, as shown in fig. 1, a diode is disposed on the secondary side, and since the requirement for energy efficiency is higher and higher, the forward voltage drop of the diode is generally above 0.7V, which is particularly large in power consumption, in order to achieve high energy efficiency, the SR technology is more and more used, that is, an SR (synchronous rectification) chip and an MOS transistor replace the original diode, so that the voltage drop of the diode is reduced, and the overall efficiency is improved; when the SR control is realized, the Vds voltage of the secondary MOS tube is sampled, the switch of the SR Gate is controlled through the Vds voltage, and the Vds is the voltage difference between the VD pin and the VSS pin of the chip.
In the existing method, Vds is modulated within a limited interval by comparing the voltage of Vds with a threshold voltage, an adopted circuit diagram is shown in fig. 2, the circuit consists of three comparators, a voltage source, two diodes and a driver, and finally the control of the input Vds within-36 mV to-30 mV is realized, but when the Gate voltage is reduced, the Gate voltage is not convenient to regulate and control, and the smaller the Gate voltage is, the larger the influence on the Ron of an MOS transistor is, the more the Gate is reduced, the larger the Ron is, the larger the Vds I is caused, the power consumption is increased, and the efficiency of the whole system is reduced.
Disclosure of Invention
The invention aims to provide a chip control circuit based on an SR technology and an implementation method thereof, and solves the problems that the existing control method is high in power consumption, low in efficiency and inconvenient in Gate voltage regulation and control.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a chip control circuit based ON SR technology comprises a transformer, a MOS tube, comparators OP1, OP2, OP3, a Gate switch control circuit with signal input ends ON, OFF and a signal output end, a driver with an input end connected with the signal output end of the Gate switch control circuit, a switch S connected with the output end of the driver, and a current control circuit connected with the other end of the switch S, wherein the inverting input end of the comparator OP1 is connected with a threshold voltage Vth1, the non-inverting input end of the comparator OP2 is connected with a threshold voltage Vth2, the inverting input end of the comparator OP3 is connected with a threshold voltage Vth3, the non-inverting input ends of the comparators OP1 and OP3 and the inverting input end of the comparator OP2 are connected with the drain of the MOS tube, the output end of the comparator OP1 is connected with the signal input end OFF of the Gate switch control circuit, the output end of the comparator 2 is connected with the signal input end ON of the Gate switch control circuit, and the connecting point of the output end of the driver and the switch S is connected with the grid electrode of the MOS tube.
Further, the threshold voltages Vth1, Vth2 and Vth3 are all provided by independent voltage sources, the threshold voltage values are sequentially reduced, and the other ends of the voltage sources are connected with the source electrode of the MOS tube and grounded.
Furthermore, the current control circuit comprises a resistor R1 and a resistor R2 which are connected in series, wherein one end of the resistor R1 is connected with the grid electrode of the MOS tube, the other end of the resistor R2 is grounded, a first voltage-current conversion circuit is connected to the connection point of the resistors R1 and R2, an amplifier is connected to the drain electrode of the MOS tube, a second voltage-current conversion circuit is connected to the output end of the amplifier, and a current selection circuit, the input end of the current selection circuit is respectively connected to the first voltage-current conversion circuit and the second voltage-current conversion circuit, and the output end of the current selection.
Furthermore, the current selection circuit comprises an operational amplifier, an NMOS tube with a grid connected to the output end of the operational amplifier, a variable resistor with one end connected with the source electrode of the NMOS tube and the other end grounded, and a plurality of comparators with positive phase input ends connected with input voltage, wherein the positive phase input ends of the operational amplifier are connected with the drain electrode of the MOS tube, the negative phase input ends of the operational amplifier are connected with the source electrode of the NMOS tube, the negative phase input ends of the comparators are connected with different threshold voltages, and output signals of the comparators are used for controlling the adjustment of the resistance value of the variable resistor.
Based on the chip control circuit based on the SR technology, the invention also provides an implementation method of the circuit, which comprises the following steps:
(1) different threshold voltages Vth1, Vth2 and Vth3 are set according to circuit design requirements, and the source of the MOS transistor is grounded, namely: when Vs is 0V, the voltage Vd connected between the non-inverting input terminal of the comparator OP1 and the inverting input terminal of the comparator OP2 is Vds;
(2) the comparators OP1 and OP2 control the Gate switch control circuit to output control signals to the driver, so as to control the switching of the Gate of the MOS tube;
(3) in the process of follow current of the secondary side of the transformer, the Vds is gradually increased, when the Vds is larger than a certain value, the comparator OP3 controls the switch S to be closed, the grid voltage of the MOS tube is reduced, meanwhile, the pull-down current of the MOS tube is controlled through the current control circuit, excessive adjustment of the grid voltage of the MOS tube is avoided, and intelligent control is achieved.
Specifically, in step (2): when Vds is less than Vth2, the comparator OP1 outputs low level, the comparator OP2 outputs high level, and the MOS transistor is controlled to be turned on through a Gate switch control circuit and a driver.
Specifically, in step (2): when Vds is greater than Vth1, the comparator OP1 outputs high level, the comparator OP2 outputs low level, and the MOS transistor is controlled to be closed through a Gate switch control circuit and a driver.
Specifically, in step (2): when Vth2< Vds < Vth1, the comparators OP1 and OP2 output low and the driver output is in high impedance state.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention compares Vds with threshold voltage through comparators OP1 and OP2, so that a Gate switch control circuit outputs a control signal to a driver for controlling the switching of the Gate of an MOS tube; in the process of secondary afterflow of the transformer, secondary current is gradually reduced, Vds is smaller and smaller, when Vds is smaller than a certain value, the comparator OP3 controls the switch S to be closed, the grid voltage of the MOS tube is reduced, meanwhile, the current control circuit controls the pull-down current of the MOS tube through the grid voltage of the MOS tube, Ron and the secondary current, the pull-down current is properly reduced, regulation and control are convenient, the problem of excessive adjustment when the grid voltage of the comparator OP3 is controlled is avoided, the power consumption of the whole circuit is reduced, the working efficiency of the circuit is improved, the comparator has the characteristic of quick response, and the regulation speed is improved.
(2) In the process of adjusting the grid voltage, after the freewheeling current crosses zero, the voltage value of Vds is greater than Vth1, and the comparator OP1 is triggered, so that the purpose of preventing the MOS tube from current reversal can be achieved.
Drawings
Fig. 1 is a circuit diagram of a conventional ACDC system.
Fig. 2 is a circuit diagram of a conventional control method.
FIG. 3 is a circuit diagram of a chip control circuit according to the present invention.
Fig. 4 is a circuit diagram of a current control circuit according to the present invention.
Fig. 5 is a circuit diagram of the current selection circuit of fig. 4.
Detailed Description
The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.
Examples
As shown in fig. 3, the chip control circuit based ON SR technology disclosed by the present invention comprises a transformer, a MOS transistor, comparators OP1, OP2, OP3, a Gate switch control circuit having signal input terminals ON, OFF and signal output terminals, a driver having an input terminal connected to the signal output terminal of the Gate switch control circuit, a switch S connected to the output terminal of the driver, and a current control circuit connected to the other terminal of the switch S, wherein the inverting input terminal of the comparator OP1 is connected to a threshold voltage Vth1, the non-inverting input terminal of the comparator OP2 is connected to a threshold voltage Vth2, the inverting input terminal of the comparator OP3 is connected to a threshold voltage Vth3, the non-inverting input terminals of the comparators OP1, OP3 and the inverting input terminal of the comparator OP2 are both connected to the drain of the MOS transistor, the output terminal of the comparator OP1 is connected to the signal input terminal OFF of the Gate switch control circuit, the output terminal of the comparator OP2 is connected to the signal input terminal ON of the Gate switch control circuit, and the connecting point of the output end of the driver and the switch S is connected with the grid electrode of the MOS tube. In this embodiment, the threshold voltages Vth1, Vth2 and Vth3 are all provided by independent voltage sources, the threshold voltage values decrease sequentially, and the other end of the voltage source is connected with the source of the MOS transistor and grounded.
As shown in fig. 4, the current control circuit includes a resistor R1 and a resistor R2 connected in series, one end of which is connected to the gate of the MOS transistor and the other end of which is connected to ground, a first voltage-to-current conversion circuit connected to the connection point of the resistors R1 and R2, an amplifier connected to the drain of the MOS transistor, a second voltage-to-current conversion circuit connected to the output end of the amplifier, and a current selection circuit having input ends connected to the first voltage-to-current conversion circuit and the second voltage-to-current conversion circuit, respectively, wherein the output end of the current selection circuit outputs a pull-down current.
As shown in fig. 5, the current selection circuit includes an operational amplifier, an NMOS transistor having a gate connected to an output terminal of the operational amplifier, a variable resistor having one end connected to a source of the NMOS transistor and the other end grounded, and a plurality of comparators having a positive phase input terminal connected to an input voltage, wherein a non-phase input terminal of the operational amplifier is connected to a drain of the MOS transistor, a negative phase input terminal of the operational amplifier is connected to a source of the NMOS transistor, negative phase input terminals of the comparators are connected to different threshold voltages, and an output signal of the comparator is used to control a resistance of the variable resistor.
In addition to the current selection circuit proposed above, the present embodiment provides two other ways of current selection, namely: the smaller of the two currents is selected, the two currents are multiplied. In the current control circuit, one of the voltage-current conversion circuits is in a discrete digital processing mode, pull-down current control is realized through the current selection circuit, the plurality of comparators are used for judging the voltage range of the grid voltage and outputting digital signals to control the current of the NMOS tube, and the current of the NMOS tube or the current of the NMOS tube after being amplified again is the pull-down current output.
Based on the chip control circuit based on the SR technology, the invention also provides an implementation method of the circuit, which comprises the following steps:
firstly, different threshold voltages Vth1, Vth2 and Vth3 are set according to circuit design requirements, in this embodiment, the threshold voltage values are-5 mV, -15mV and-35 mV in sequence, and the voltage difference Vds between the drain and the source of the MOS transistor is Vd-Vs, since the source of the MOS transistor is grounded, that is: when Vs is 0V, the voltage Vd connected between the non-inverting input terminal of the comparator OP1 and the inverting input terminal of the comparator OP2 is Vds;
secondly, the Gate switch control circuit is controlled by the comparators OP1 and OP2 to output control signals to the driver for controlling the switching of the Gate of the MOS tube. Specifically, in step (2): when Vds is less than Vth2, the comparator OP1 outputs low level, the comparator OP2 outputs high level, and the MOS tube is controlled to be opened through a Gate switch control circuit and a driver; when Vds is greater than Vth1, the comparator OP1 outputs high level, the comparator OP2 outputs low level, and the MOS tube is controlled to be closed through a Gate switch control circuit and a driver; when Vth2< Vds < Vth1, the comparators OP1 and OP2 output low and the driver output is in high impedance state.
In the process of follow current of the secondary side of the transformer, the secondary side current is gradually reduced, Vds is increased, in order to avoid the situation that Vds is too large, Vds voltage is in contact with an external noise signal to enable the comparator OP1 to be turned off, when Vds is larger than a certain value, the comparator OP3 controls the switch S to be closed, the grid voltage of the MOS tube is reduced, the value of Vds is enabled to be in a reasonable state, in the actual control process, after the follow current crosses zero, no matter how the grid voltage is pulled down to adjust, Vds can be larger than Vth1, the comparator OP1 can be triggered, and the current reversal of the MOS tube can be effectively prevented. However, when the gate voltage of the MOS transistor is reduced, the influence of the gate voltage on the on-resistance Ron of the MOS transistor becomes larger, and the too much reduction of the gate voltage easily causes the Ron to be too large, so that the Vds voltage is also too large, which causes the Vds I to be too large, thereby increasing the power consumption and reducing the overall system efficiency.
Therefore, in order to avoid the problem of excessive adjustment when the comparator OP3 controls the grid voltage, the pull-down current of the MOS tube is controlled by the current control circuit, the pull-down current can be intelligently adjusted according to the grid voltage, Ron and the magnitude of the secondary current of the MOS tube, and if the grid voltage is lower, the Ron is larger or the secondary current is smaller, the pull-down current can be properly reduced by the current control circuit, the power consumption of the whole circuit is reduced, the excessive adjustment of the grid voltage of the MOS tube is avoided, the intelligent control is realized, and the comparator has the characteristic of quick response, so that the adjustment speed is favorably improved.
The above-mentioned embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or changes made within the spirit and scope of the main design of the present invention, which still solve the technical problems consistent with the present invention, should be included in the scope of the present invention.
Claims (7)
1. A chip control circuit based ON SR technology comprises a transformer, a MOS tube, and is characterized by further comprising comparators OP1, OP2, OP3, a Gate switch control circuit with signal input ends ON, OFF and a signal output end, a driver with the input end connected with the signal output end of the Gate switch control circuit, a switch S connected with the output end of the driver, and a current control circuit connected with the other end of the switch S, wherein the inverting input end of the comparator OP1 is connected with a threshold voltage Vth1, the non-inverting input end of the comparator OP2 is connected with a threshold voltage Vth2, the inverting input end of the comparator OP3 is connected with a threshold voltage Vth3, the non-inverting input ends of the comparators OP1 and 3 and the inverting input end of the comparator OP2 are connected with the drain of the MOS tube, the output end of the comparator OP1 is connected with the signal input end OFF of the Gate switch control circuit, and the output end of the comparator 2 is connected with the signal input end of the Gate switch control circuit ON, the connection point of the output end of the driver and the switch S is connected with the grid electrode of the MOS tube, and the output end of the comparator OP3 is connected with the switch S and used for controlling the switch S to be closed;
the current control circuit comprises a resistor R1 and a resistor R2 which are connected with the grid electrode of the MOS tube and the other end of the MOS tube in series, a first voltage current conversion circuit connected to the connection point of the resistors R1 and R2, an amplifier connected to the drain electrode of the MOS tube, a second voltage current conversion circuit connected to the output end of the amplifier, and a current selection circuit of which the input end is connected to the first voltage current conversion circuit and the second voltage current conversion circuit respectively, wherein the output end of the current selection circuit outputs pull-down current.
2. The chip control circuit based on the SR technology as claimed in claim 1, wherein said threshold voltages Vth1, Vth2 and Vth3 are all provided by independent voltage sources, and Vth1> Vth3> Vth2, and the other end of said voltage source is connected to the source of the MOS transistor and grounded.
3. The chip control circuit based on the SR technology of claim 2, wherein the current selection circuit comprises an operational amplifier, an NMOS transistor having a gate connected to an output terminal of the operational amplifier, a variable resistor having one end connected to a source of the NMOS transistor and the other end connected to ground, and a plurality of comparators having a positive input terminal connected to an input voltage, a positive input terminal of the operational amplifier being connected to a drain of the MOS transistor, a negative input terminal of the operational amplifier being connected to a source of the NMOS transistor, negative input terminals of the comparators being connected to different threshold voltages, and an output signal of the comparators being used to control the adjustment of the resistance of the variable resistor.
4. The method for realizing the chip control circuit based on the SR technology as claimed in any one of claims 1-3, comprising the steps of:
(1) different threshold voltages Vth1, Vth2 and Vth3 are set according to circuit design requirements, and the source of the MOS transistor is grounded, namely: vs =0V, the voltage Vd = Vds connected between the positive input terminal of the comparator OP1 and the negative input terminal of the comparator OP 2;
(2) the comparators OP1 and OP2 control the Gate switch control circuit to output control signals to the driver, so as to control the switching of the Gate of the MOS tube;
(3) in the process of follow current of the secondary side of the transformer, the Vds is gradually increased, when the Vds is larger than a certain value, the comparator OP3 controls the switch S to be closed, the grid voltage of the MOS tube is reduced, meanwhile, the pull-down current of the MOS tube is controlled through the current control circuit, excessive adjustment of the grid voltage of the MOS tube is avoided, and intelligent control is achieved.
5. The method for implementing the chip control circuit based on the SR technology as claimed in claim 4, wherein in step (2): when Vds is less than Vth2, the comparator OP1 outputs low level, the comparator OP2 outputs high level, and the MOS transistor is controlled to be turned on through a Gate switch control circuit and a driver.
6. The method for implementing the chip control circuit based on the SR technology as claimed in claim 4, wherein in step (2): when Vds is greater than Vth1, the comparator OP1 outputs high level, the comparator OP2 outputs low level, and the MOS transistor is controlled to be closed through a Gate switch control circuit and a driver.
7. The method for implementing the chip control circuit based on the SR technology as claimed in claim 4, wherein in step (2): when Vth2< Vds < Vth1, the comparators OP1 and OP2 output low and the driver output is in high impedance state.
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| CN201910739511.8A CN110429801B (en) | 2019-08-12 | 2019-08-12 | Chip control circuit based on SR technology and implementation method |
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| CN201910739511.8A CN110429801B (en) | 2019-08-12 | 2019-08-12 | Chip control circuit based on SR technology and implementation method |
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| CN110429801A CN110429801A (en) | 2019-11-08 |
| CN110429801B true CN110429801B (en) | 2021-04-13 |
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Address after: Room 214, No.1000 Chenhui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200120 Patentee after: Shanghai Nanxin Semiconductor Technology Co.,Ltd. Address before: Room 309, 22 Boxia Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200120 Patentee before: SOUTHCHIP SEMICONDUCTOR TECHNOLOGY (SHANGHAI) Co.,Ltd. |