CN111786661A

CN111786661A - Self-calibration zero-crossing comparator and direct-current conversion circuit

Info

Publication number: CN111786661A
Application number: CN202010920512.5A
Authority: CN
Inventors: 龚坤林
Original assignee: Suzhou Saixin Electronic Technology Co ltd
Current assignee: Suzhou Saixin Electronic Technology Co.,Ltd.
Priority date: 2020-09-04
Filing date: 2020-09-04
Publication date: 2020-10-16
Anticipated expiration: 2040-09-04
Also published as: CN111786661B

Abstract

The invention discloses a self-calibration zero-crossing comparator and a direct current conversion circuit. The self-calibrating zero-crossing comparator comprises: the device comprises a first comparison module, a logic module, a compensation module and a second comparison module; the first comparison module is used for comparing the reference voltage with the sampling voltage and outputting a state signal; the logic module is used for generating a logic control signal according to the state signal; the compensation module is used for biasing the first power supply signal to generate a bias signal and compensating the sampling voltage according to the logic control signal to generate a compensation signal; the second comparison module is used for comparing the sizes of the offset signal and the compensation signal and outputting a zero-crossing comparison signal. The invention can improve the precision of the zero-crossing comparator on the basis of not increasing the cost.

Description

Self-calibration zero-crossing comparator and direct-current conversion circuit

Technical Field

The embodiment of the invention relates to the technical field of zero-crossing detection, in particular to a self-calibration zero-crossing comparator and a direct-current conversion circuit.

Background

In a DC-DC circuit, the power efficiency of the system is highly required. In order to consider both heavy load and light load, a Pulse Width Modulation (PWM) control mode is generally adopted by a DC-DC power supply during heavy load, and output is adjusted by adjusting a duty ratio at a fixed frequency; the power supply can adopt a Pulse Frequency Modulation (PFM) control mode during light load, and the efficiency is improved by reducing the switching frequency. When the load current is large, the system works in a Continuous Current Mode (CCM), and the average value of the inductive current is a triangular wave equal to the load current; when the load current is reduced to a certain extent, the triangular wave of the inductor current will partly go below zero. In order to prevent energy loss caused by reverse inductive current, the switching tube needs to be turned off when the inductive current is zero. Therefore, a zero-crossing comparison circuit is required to detect whether the inductor current is zero.

When the inductor current drops to zero, the sampling voltage at the sampling point is zero. Therefore, in the conventional zero-crossing detection circuit, a comparator is usually used to directly compare the sampling voltage of a sampling point with a zero signal, and if the voltage of the sampling point is detected to be greater than zero, it is determined that the inductive current enters a negative current region, and the switching tube needs to be closed. The inaccuracy of zero-cross detection can be caused by the problems of the precision and the time delay of the comparator, so that great cost needs to be paid when the chip is designed to improve the precision, and the cost of power consumption and circuit reliability needs to be paid if the time delay of the comparator and the whole circuit needs to be reduced. Therefore, the accuracy and the cost of the existing zero-crossing comparator have a contradiction relation.

Disclosure of Invention

The embodiment of the invention provides a self-calibration zero-crossing comparator and a direct current conversion circuit, which are used for improving the precision of the zero-crossing comparator on the basis of not increasing the cost.

In a first aspect, an embodiment of the present invention provides a self-calibration zero-crossing comparator, where the self-calibration zero-crossing comparator includes: the device comprises a first comparison module, a logic module, a compensation module and a second comparison module;

a first input end of the first comparison module is connected with a reference voltage, and a second input end of the first comparison module is connected with a sampling voltage and is used as an input end of the self-calibration zero-crossing comparator; the first comparison module is used for comparing the reference voltage with the sampling voltage and outputting a state signal;

the input end of the logic module is electrically connected with the output end of the first comparison module; the logic module is used for generating a logic control signal according to the state signal;

a first input end of the compensation module is connected with a first power supply signal, a second input end of the compensation module is connected with the sampling voltage, and a control input end of the compensation module is electrically connected with an output end of the logic module; the compensation module is used for biasing the first power supply signal to generate a bias signal and compensating the sampling voltage according to the logic control signal to generate a compensation signal;

a first input end of the second comparison module is electrically connected with a second output end of the compensation module, a second input end of the second comparison module is electrically connected with a first output end of the compensation module, and an output end of the second comparison module is used as an output end of the self-calibration zero-crossing comparator; the second comparison module is used for comparing the magnitudes of the offset signal and the compensation signal and outputting a zero-crossing comparison signal.

Optionally, the logic control signal comprises an n-bit logic control signal; wherein n is an integer greater than or equal to 4;

the compensation module includes: the circuit comprises a first transistor, a second transistor, a first pull-up power supply, a first current mirror, a second current mirror, a first resistor and a compensation unit group; the compensation unit group comprises n compensation units connected in series, each compensation unit comprises a control end and serves as the control end of the compensation unit group;

the grid electrode of the first transistor is a first input end of the compensation module, a first pole of the first transistor and a first pole of the second transistor are both connected to the first power supply signal, and a second pole of the first transistor is electrically connected with a second end of the first resistor; the first end of the first resistor is electrically connected with the second end of the first current mirror and is used as the first output end of the compensation module; the output end of the first pull-up power supply is electrically connected with the first end of the first current mirror and the first end of the second current mirror respectively; the grid electrode of the second transistor is a second input end of the compensation module; the first end of the compensation unit group is electrically connected with the second end of the second current mirror and is used as the second output end of the compensation module; and the second end of the compensation unit group is electrically connected with the second pole of the second transistor, and the n control ends of the compensation unit group are electrically connected with the n-bit logic control signals in a one-to-one correspondence manner.

Optionally, the compensation unit further comprises: a compensation resistor and a compensation transistor; the compensation resistor and the compensation transistor are connected in parallel; on a branch of the compensation unit, along the direction opposite to the current flow direction, the resistance value of a compensation resistor in the mth compensation unit is 2 times that of a compensation resistor in the m-1 th compensation unit; wherein m is more than or equal to 2 and less than or equal to n, and m is an integer.

Optionally, the first comparing module includes: the first NOR gate, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the second pull-up power supply, the third current mirror and the first NOR gate group; wherein the first set of NOT gates comprises an odd number of series connected NOT gates;

the first pole of the third transistor is the second input end of the first comparison module; a first end of the first NOR gate is connected with a first driving signal, a second end of the first NOR gate is connected with a second driving signal, and an output end of the first NOR gate is electrically connected with a grid electrode of the third transistor; a second pole of the third transistor is electrically connected to a gate of the fourth transistor; a first pole of the fourth transistor is electrically connected with a first pole of the fifth transistor, a gate of the fifth transistor and a gate of the sixth transistor respectively; an output end of the second pull-up power supply is electrically connected with a second pole of the fifth transistor and a second pole of the sixth transistor respectively; a first electrode of the sixth transistor is electrically connected with a first electrode of the seventh transistor and a first end of the first non-gate group respectively; the grid electrode of the seventh transistor is a first input end of the first comparison module; a first end of the third current mirror is electrically connected with a second pole of the fourth transistor and a second pole of the seventh transistor respectively, and a second end of the third current mirror is connected to the first power supply signal; the second end of the first non-gate group is the output end of the first comparison module.

Optionally, the first comparing module further includes: a first capacitor;

the first end of the first capacitor is electrically connected with the second pole of the third transistor and the grid electrode of the fourth transistor respectively, and the second end of the first capacitor is connected to the first power supply signal.

Optionally, the logic module includes: a second NOR gate, a flip-flop and a counter;

a first end of the second nor gate is connected to a first driving signal, a second end of the second nor gate is connected to a second driving signal, and an output end of the second nor gate is electrically connected to a clock end of the flip-flop; the input end of the trigger is the input end of the logic module, and the output end of the trigger is electrically connected with the input end of the counter; and the output end of the counter is the output end of the logic module.

Optionally, the second comparing module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fourth current mirror, a fifth current mirror, a third pull-up power supply, and a second not gate group; wherein the second set of NOT gates comprises an even number of NOT gates connected in series;

a gate of the eighth transistor is a first input end of the second comparing module, and a first pole of the eighth transistor is electrically connected with a first pole of the ninth transistor, a gate of the ninth transistor, and a gate of the tenth transistor, respectively; an output end of the third pull-up power supply is electrically connected with a second pole of the ninth transistor, a second pole of the tenth transistor and a second pole of the twelfth transistor respectively; a first electrode of the tenth transistor is electrically connected to a first electrode of the eleventh transistor and a gate electrode of the twelfth transistor, respectively; the grid electrode of the eleventh transistor is a second input end of the second comparison module; a first end of the fourth current mirror is electrically connected with a second pole of the eighth transistor and a second pole of the eleventh transistor respectively, and a second end of the fourth current mirror is connected to the first power supply signal; a first pole of the twelfth transistor is electrically connected with a first end of the fifth current mirror and a first end of the second non-gate group respectively; the second end of the fifth current mirror is connected to the first power supply signal; and the second end of the second non-gate group is the output end of the second comparison module.

In a second aspect, an embodiment of the present invention provides a dc conversion circuit, including: a transformation module, a drive module and a self-calibration zero-crossing comparator as provided by any embodiment of the invention;

the first output end of the driving module is electrically connected with the first control end of the transformation module, the second output end of the driving module is electrically connected with the second control end of the transformation module, and the input end of the driving module is electrically connected with the output end of the self-calibration zero-crossing comparator; and the input end of the self-calibration zero-crossing comparator is electrically connected with the sampling end of the transformation module.

Optionally, the conversion module includes a thirteenth transistor, a fourteenth transistor, a first inductor, a second capacitor, and a first power supply;

a grid electrode of the thirteenth transistor is used as a first control end of the conversion module, and a first pole of the thirteenth transistor is electrically connected with an output end of the first power supply; a second pole of the thirteenth transistor is electrically connected with a first pole of the fourteenth transistor and a first end of the first inductor respectively and serves as a sampling end of the conversion module; a gate of the fourteenth transistor is used as a second control end of the conversion module, and a second pole of the fourteenth transistor is connected to a first power signal and is electrically connected with a second end of the second capacitor; the second end of the first inductor is electrically connected with the first end of the second capacitor; the first end of the second capacitor is the output end of the transformation module.

Optionally, the driving module comprises: the device comprises a feedback module, a pulse width modulation module, a pulse frequency modulation module and a drive control module;

the first end of the feedback module is electrically connected with the output end of the transformation module, the second end of the feedback module is connected with the first power supply signal, and the output end of the feedback module is electrically connected with the second input end of the pulse width modulation module and the second input end of the pulse frequency modulation module respectively; a first input end of the pulse width modulation module is connected with a first reference signal, and an output end of the pulse width modulation module is electrically connected with a first input end of the driving control module; a first input end of the pulse frequency modulation module is connected with a second reference signal, and an output end of the pulse frequency modulation module is electrically connected with a second input end of the driving control module; the third input end of the drive control module is used as the input end of the drive module, the first output end of the drive control module is used as the first output end of the drive module, and the second output end of the drive control module is used as the second output end of the drive module.

In the embodiment of the invention, the zero-crossing comparison signal is output by comparing the sizes of the offset signal and the compensation signal, and the zero-crossing turnover point of the system is substantially adjusted by the zero-crossing comparison signal. The first power supply signal is artificially biased by the compensation module, so that the sampling voltage can be compensated in an upward or downward direction, and the zero-crossing turnover point is corrected. And the comparison precision is improved by monitoring and adjusting the zero-crossing turning point in real time. The sampling voltage which needs to be compensated upwards or downwards is determined by a logic module through logic operation, and the strict precision requirement and speed requirement on a comparator are not required. Therefore, the first comparison module and the second comparison module can adopt comparators with general precision, thereby reducing the manufacturing cost. Therefore, compared with the prior art, the embodiment of the invention can improve the precision of the zero-crossing comparator on the basis of not increasing the cost.

Drawings

Fig. 1 is a schematic structural diagram of a self-calibration zero-crossing comparator according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a compensation module according to an embodiment of the present invention;

fig. 3 is a schematic circuit structure diagram of a first comparing module according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a logic module according to an embodiment of the present invention;

fig. 5 is a schematic circuit structure diagram of a second comparing module according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a dc conversion circuit according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a dc conversion circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a current waveform of the first inductor L1 when the conversion module operates in the CCM mode according to an embodiment of the present invention;

fig. 9 is a waveform diagram of the current of the first inductor L1 and the voltage at the sampling point SW when the current of the first inductor L1 in the transform module has a negative value according to an embodiment of the present invention;

fig. 10 is a waveform diagram illustrating the current of the first inductor L1 and the voltage at the sampling point SW when the zero-crossing flipping point is too early according to the embodiment of the present invention;

fig. 11 is a waveform diagram illustrating a current of the first inductor L1 and a voltage of the sampling point SW when the zero-crossing flip point is too late according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The embodiment of the invention provides a self-calibration zero-crossing comparator. Fig. 1 is a schematic structural diagram of a self-calibration zero-crossing comparator according to an embodiment of the present invention, and as shown in fig. 1, the self-calibration zero-crossing comparator includes: the first comparison module 110, the logic module 120, the compensation module 130 and the second comparison module 140;

a first input end 111 of the first comparing module 110 is connected to a reference voltage Vref, and a second input end 112 of the first comparing module 110 is connected to a sampling voltage Vsamp and serves as an input end of a self-calibration zero-crossing comparator; the first comparing module 110 is configured to compare the reference voltage Vref and the sampling voltage Vsamp, and output a status signal.

The input end 121 of the logic module 120 is electrically connected with the output end 113 of the first comparison module 110; the logic module 120 is configured to generate a logic control signal according to the status signal.

A first input end 131 of the compensation module 130 is connected to the first power signal VSS, a second input end 132 of the compensation module 130 is connected to the sampled voltage Vsamp, and a control input end 133 of the compensation module 130 is electrically connected to the output end 122 of the logic module 120; the compensation module 130 is configured to bias the first power signal VSS to generate a bias signal, and compensate the sampling voltage Vsamp according to the logic control signal to generate a compensation signal.

The first input 141 of the second comparing module 140 is electrically connected to the second output 135 of the compensating module 130, the second input 142 of the second comparing module 140 is electrically connected to the first output 134 of the compensating module 130, and the output 143 of the second comparing module 140 serves as the output of the self-calibration zero-crossing comparator; the second comparing module 140 is configured to compare the magnitudes of the offset signal and the compensation signal, and output a zero-crossing comparison signal ZC.

The reference voltage Vref can be set correspondingly according to the change rule of the sampling voltage Vsamp in practical application, and the application does not limit the size of the reference voltage Vref. Alternatively, the first power signal VSS may be a ground signal.

The first comparing module 110 is configured to compare the reference voltage Vref and the sampling voltage Vsamp, and output a status signal. Illustratively, when the zero crossing trip point is earlier than the actual zero crossing point, assuming that the reference voltage Vref is greater than the sampling voltage Vsamp, the first comparing module 110 outputs a status signal indicating that the reference voltage Vref is large, such as output 1. When the zero crossing flip point is later than the actual zero crossing point, the first comparing module 110 outputs a state signal indicating that the reference voltage Vref is small, such as 0, assuming that the reference voltage Vref is less than the sampling voltage Vsamp.

The logic module 120 is configured to generate a logic control signal according to the status signal, and the logic control signal controls a compensation manner of the compensation module 130 for the sampling voltage Vsamp. For example, the logic module 120 may set the initial logic control signal to control the compensation module 130 to generate the initial compensation amount to form the initial compensation signal. When the status signal output by the first comparing module 110 is 1, the logic module 120 outputs a logic control signal for controlling the compensation module 130 to compensate the sampling voltage Vsamp downwards; when the status signal output by the first comparing module 110 is 0, the logic module 120 outputs a logic control signal for controlling the compensation module 130 to compensate the sampling voltage Vsamp upwards.

In this embodiment, the compensation direction and the compensation amount of the compensation module 130 are determined by the logic operation of the logic module 120, so that the comparison module is not required to have high precision and speed, the first comparison module 110 and the second comparison module 140 can achieve general precision, and the cost of the self-calibration zero-crossing comparator is not increased.

The compensation module 130 is a key module to correct the roll-over point of the self-calibrating zero-crossing comparator. In the compensation module 130, the compensation amount of the sampling voltage Vsamp is positive, and if the first power signal VSS is not processed, the compensation signal is directly compared with the first power signal VSS, which means that only the sampling voltage Vsamp can be compensated in the forward direction. Therefore, an offset amount is introduced on the basis of the first power supply signal VSS to form an offset signal to increase a compensation range of the compensation signal for the sampling voltage Vsamp. After the offset is introduced, the compensation signal is compared with the offset signal, and although the compensation amount of the sampling voltage Vsamp is still positive, when the compensation amount is smaller than the offset amount, the compensation is equivalent to negative compensation. In practical applications, the offset of the compensation module 130 with respect to the first power signal VSS can be set according to requirements, and the offset remains unchanged, and the logic module 120 only controls the compensation amount of the compensation module 130 with respect to the sampling voltage Vsamp.

Before the self-calibration zero-crossing comparator is applied, the compensation amount of the compensation module 130 for the sampling voltage Vsamp is first set to be close to the offset amount for the first power signal VSS, so as to prevent an error caused by an excessively large difference between the initial compensation amount and the initial offset amount when the required compensation amount is small.

Illustratively, the compensation module 130 first sets an offset to be superimposed on the first power signal VSS to form an offset signal. When the logic module 120 generates a logic control signal that is compensated downward; the compensation module 130 reduces the compensation amount according to the logic control signal, and performs negative compensation on the sampled voltage Vsamp to form a compensation signal. When the logic module 120 generates an up compensated logic control signal; the compensation module 130 increases the compensation amount according to the logic control signal, and performs forward compensation on the sampling voltage Vsamp to form a compensation signal.

In the present embodiment, the compensation module 130 artificially biases the first power signal VSS, so that the unidirectional compensation mode can be extended to compensate the sampled voltage Vsamp in both the upward and downward directions, thereby expanding the correction range of the zero-crossing flip point.

The second comparing module 140 is configured to compare the magnitudes of the offset signal and the compensation signal, and output a zero-crossing comparison signal ZC. Illustratively, when the compensation signal is less than the offset signal, the second comparison module 140 outputs a zero-crossing comparison signal ZC representing a delayed zero-crossing trip point, such as output 1; when the compensation signal is greater than the offset signal, the second comparison module 140 outputs a zero-crossing comparison signal ZC representing that zero-crossing inversion is performed immediately, such as 0.

The self-calibration zero-crossing comparator provided by the embodiment of the invention outputs the zero-crossing comparison signal by comparing the sizes of the bias signal and the compensation signal, and substantially adjusts the zero-crossing turning point of the system by the zero-crossing comparison signal. The first power supply signal is artificially biased by the compensation module, so that the sampling voltage can be compensated in an upward or downward direction, and the zero-crossing turnover point is corrected. And the comparison precision is improved by sampling in real time and adjusting the zero-crossing turning point. The sampling voltage which needs to be compensated upwards or downwards is determined by a logic module through logic operation, and the strict precision requirement and speed requirement on a comparator are not required. Therefore, the first comparison module and the second comparison module can adopt comparators with general precision, thereby reducing the manufacturing cost. Therefore, the embodiment of the invention can improve the precision of the zero-crossing comparator on the basis of not increasing the cost.

In addition to the above embodiments, the present embodiment supplements the structure of the compensation module. Fig. 2 is a schematic circuit diagram of a compensation module according to an embodiment of the present invention. As shown in fig. 2, the logic control signal includes an n-bit logic control signal; wherein n is an integer greater than or equal to 4. The compensation module includes: a first transistor M1, a second transistor M2, a first pull-up power source VS1, a first current mirror I1, a second current mirror I2, a first resistor R1, and the compensation unit group 210; the compensation unit group 210 includes n compensation units connected in series, each compensation unit includes a control terminal, and the control terminal is used as the control terminal of the compensation unit group 210.

The gate of the first transistor M1 is a first input terminal of the compensation module, a first pole of the first transistor M1 and a first pole of the second transistor M2 are both connected to a first power signal, and a second pole of the first transistor M1 is electrically connected to a second terminal of the first resistor R1; a first end of the first resistor R1 is electrically connected with a second end of the first current mirror I1 and is used as a first output end of the compensation module; the output end of the first pull-up power source VS1 is respectively and electrically connected with the first end of the first current mirror I1 and the first end of the second current mirror I2; the gate of the second transistor M2 is the second input terminal of the compensation module; a first end of the compensation unit group 210 is electrically connected with a second end of the second current mirror I2 and serves as a second output end of the compensation module; the second terminal of the compensation unit group 210 is electrically connected to the second pole of the second transistor M2, and the n control terminals of the compensation unit group 210 are electrically connected to the n-bit logic control signals in a one-to-one correspondence.

In fig. 2, for example, the logic control signals include 4-bit logic control signals, that is, the logic control signals are Vctl <3:0 overall, and include a first bit logic control signal Vctl0, a second bit logic control signal Vctl1, a third bit logic control signal Vctl2, and a fourth bit logic control signal Vctl 3. Meanwhile, taking the example that the compensation unit group 210 includes 4 compensation units, the compensation unit group 210 includes a first compensation unit 211, a second compensation unit 212, a third compensation unit 213 and a fourth compensation unit 214.

With continued reference to fig. 2, further, the compensation unit further comprises: a compensation resistor and a compensation transistor; the compensation resistor and the compensation transistor are connected in parallel; on the branch of the compensation unit, along the direction opposite to the current flow direction, the resistance value of the compensation resistor in the mth compensation unit is 2 times of the resistance value of the compensation resistor in the m-1 th compensation unit; wherein m is more than or equal to 2 and less than or equal to n, and m is an integer.

Specifically, the first compensation unit 211 includes a first compensation resistor RB1 and a first compensation transistor MB1 connected in parallel, the second compensation unit 212 includes a second compensation resistor RB2 and a second compensation transistor MB2 connected in parallel, the third compensation unit 213 includes a third compensation resistor RB3 and a third compensation transistor MB3 connected in parallel, and the fourth compensation unit 214 includes a fourth compensation resistor RB4 and a fourth compensation transistor MB4 connected in parallel. The gate of the first compensation transistor MB1 is used as the control terminal of the first compensation unit 211, and is connected to the first bit logic control signal Vctl 0; the gate of the second compensation transistor MB2 is used as the control terminal of the second compensation unit 212, and is connected to the second bit logic control signal Vctl 1; the gate of the third compensation transistor MB3 is used as the control terminal of the third compensation unit 213, and is connected to the third bit logic control signal Vctl 2; the gate of the fourth compensation transistor MB4 is used as the control terminal of the fourth compensation unit 214, and is connected to the fourth logic control signal Vctl 3. The control terminals of the four compensation units together constitute the control terminal of the compensation unit group 210.

The working principle of the compensation module is as follows: the first current mirror I1 and the second current mirror I2 serve as dc current sources and provide equal constant dc current, whose value is denoted as Idc. The gate of the first transistor M1 is connected to the first power signal VSS, and the threshold voltage of the first transistor M1 is denoted as V_thM1. The gate of the second transistor M2 is connected to the sampling voltage Vsamp, and the threshold voltage of the second transistor M2 is denoted as V_thM2. The resistance value of the first compensation resistor RB1 is denoted as R, then the resistance value of the second compensation resistor RB2 is 2 × R, the resistance value of the third compensation resistor RB3 is 4 × R, and the resistance value of the fourth compensation resistor RB4 is 8 × R; alternatively, the first resistor R1 may have a resistance of 8 × R, and the logic control signal Vctl may be<3:0>Which is a four-bit binary number, the initial value of which may be set to 1000.

The offset signal Vo1 output by the first output of the compensation module is calculated according to the following equation: vo1= VSS + Idc 8R + V_thM1. The compensation signal Vo2 output by the second output terminal of the compensation module is calculated according to the following formula: vo2= Vsamp + Idc R_{General assembly}+V_thM2. Wherein R is_{General assembly}Representation compensationThe sum of the resistances of the compensation resistors connected in the branch. In any compensation unit, when the logic control signal accessed to the grid of the compensation transistor is 1, the compensation transistor is conducted and short-circuits the compensation resistors connected in parallel at two ends of the compensation transistor; when the logic control signal accessed to the gate of the compensation transistor is 0, the compensation transistor is turned off, and the compensation resistor is accessed to the compensation branch.

As shown in fig. 2, the compensation module can control the number of compensation resistors connected to the compensation unit group 210 by changing the value of the logic control signal Vctl <3:0>, so as to change the value of the compensation signal Vo 2. And the resistance values of the compensation resistors are set to be R, 2R, 4R and 8R from small to large according to the four-bit binary logic control signal Vctl <3:0>, which is equivalent to controlling the adjustment precision of the compensation quantity to be Idc R. Setting the resistance value of the first resistor R1 to 8 × R corresponds to adjusting the adjustment range of the compensation amount to [ -Idc × 8 × R, Idc × 7 × R ].

If the precision of the compensation module needs to be improved, the control bit number of the logic block control signal can be increased and the number of the compensation units in the compensation unit group 210 can be correspondingly increased. If the adjustment range of the compensation amount needs to be adjusted, the resistance value of the first resistor R1 can be adjusted according to needs.

Fig. 3 is a schematic circuit structure diagram of a first comparing module according to an embodiment of the present invention. As shown in fig. 3, the present embodiment complements the specific structure of the first comparison module on the basis of the above-described embodiment.

The first comparison module comprises: a first nor gate H1, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a second pull-up power source VS2, a third current mirror I3, and a first nor gate group 310; wherein the first not gate group 310 includes an odd number of not gates connected in series. In fig. 3, the first not gate group 310 includes three not gates, which are a first not gate X1, a second not gate X2, and a third not gate X3, respectively, and the three are connected end to end in series.

A first terminal of the third transistor M3 is a second input terminal of the first comparing block; a first end of the first nor gate H1 is connected to the first driving signal HDRV, a second end of the first nor gate H1 is connected to the second driving signal LDRV, and an output end of the first nor gate H1 is electrically connected to a gate of the third transistor M3; the second pole of the third transistor M3 is electrically connected to the gate of the fourth transistor M4; a first pole of the fourth transistor M4 is electrically connected to a first pole of the fifth transistor M5, a gate of the fifth transistor M5, and a gate of the sixth transistor M6, respectively; an output terminal of the second pull-up power source VS2 is electrically connected to the second pole of the fifth transistor M5 and the second pole of the sixth transistor M6, respectively; a first pole of the sixth transistor M6 is electrically connected with a first pole of the seventh transistor M7 and a first end of the first nor gate group 310, respectively; the gate of the seventh transistor M7 is the first input terminal of the first comparing module; a first end of the third current mirror I3 is electrically connected to the second pole of the fourth transistor M4 and the second pole of the seventh transistor M7, respectively, and a second end of the third current mirror I3 is connected to the first power signal; the second terminal of the first not-gate set 310 is the output terminal of the first comparing module.

The third current mirror I3 is a dc current source for providing transistor bias current. Alternatively, the second pull-up power source VS2 and the first pull-up power source VS1 may be the same pull-up power source. Optionally, when the self-calibration zero-crossing comparator is applied to a synchronous BUCK direct current conversion circuit (BUCK circuit), the first drive signal HDRV and the second drive signal LDRV are both generated by a control module in the BUCK circuit; the first driving signal HDRV is used for driving a main switching tube, and the second driving signal LDRV is used for driving a synchronous tube.

The working principle of the first comparison module is as follows: the gate of the third transistor M3 corresponds to the enable terminal of the first comparison module. When the first driving signal HDRV and the second driving signal LDRV are both 0, the first nor gate H1 outputs 1 to turn on the third transistor M3, and the first comparing module starts to compare the sampled voltage Vsamp with the reference voltage Vref.

When the sampling voltage Vsamp is greater than the reference voltage Vref, the fourth transistor M4 is turned on, the seventh transistor M7 is turned off, the fifth transistor M5 and the sixth transistor M6 are both turned on, the first pole of the sixth transistor M6 outputs a high level, and the state signal V1 output after inversion and shaping of odd not gates in the first not gate group 310 is 0.

When the sampling voltage Vsamp is smaller than the reference voltage Vref, the fourth transistor M4 is turned off, the seventh transistor M7 is turned on, the fifth transistor M5 and the sixth transistor M6 are both turned off, the first pole of the seventh transistor M7 outputs a low level, and the state signal V1 output after inversion and shaping of odd not gates in the first not gate group 310 is 1.

According to the first comparison module provided by the embodiment of the invention, when the first drive signal and the second drive signal are both zero, the sampling voltage is collected and compared with the reference voltage, so that errors caused by line delay can be eliminated, and the response speed of the self-calibration zero-crossing comparator is improved.

With continued reference to fig. 3, optionally, the first comparison module further comprises a first capacitor C1. A first end of the first capacitor C1 is electrically connected to the second pole of the third transistor M3 and the gate of the fourth transistor M4, respectively, and a second end of the first capacitor C1 is connected to the first power signal.

The first capacitor C1 can filter noise of the sampling voltage Vsamp, so that the stable sampling voltage Vsamp is compared with the reference voltage Vref, thereby reducing the influence of spikes and the like caused by voltage fluctuation on the comparison result.

Fig. 4 is a schematic circuit structure diagram of a logic module according to an embodiment of the present invention. As shown in fig. 4, the present embodiment further supplements the specific structure of the logic module in addition to the above embodiments.

The logic module comprises: a second nor gate H2, a flip-flop 410, and a counter 420.

A first end of the second nor gate H2 is connected to the first driving signal HDRV, a second end of the second nor gate H2 is connected to the second driving signal LDRV, and an output end of the second nor gate H2 is electrically connected to the clock terminal Clk of the flip-flop 410; the input terminal 411 of the flip-flop 410 is an input terminal of the logic module, and the output terminal 412 of the flip-flop 410 is electrically connected to the input terminal 421 of the counter 420; the output 422 of the counter is the output of the logic module.

Alternatively, the flip-flop 410 may be a D flip-flop, and when the clock Clk thereof is turned on high, the flip-flop 410 transfers the input state signal V1 to the counter 420. Alternatively, according to the above embodiments, the counter 420 may be a four-bit up-down counter to output a four-bit logic control signal Vctl <3:0 >. When the status signal V1 is 1, the counter 420 increments by 1; when the status signal V1 is 0, the counter 420 is decremented by 1. When the compensation accuracy needs to be changed, the number of bits of the counter 420 may be changed accordingly.

Fig. 5 is a schematic circuit structure diagram of a second comparing module according to an embodiment of the present invention. As shown in fig. 5, in addition to the above embodiments, the present embodiment further supplements the specific structure of the second comparison module.

The second comparison module includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a fourth current mirror I4, a fifth current mirror I5, a third pull-up power source VS3, and a second non-gate group 510; wherein the second not gate group 510 comprises an even number of not gates connected in series. In fig. 5, the second not gate group 510 includes two not gates (a fourth not gate X4 and a fifth not gate X5) connected in series.

A gate of the eighth transistor M8 is a first input terminal of the second comparing module, and a first pole of the eighth transistor M8 is electrically connected to a first pole of the ninth transistor M9, a gate of the ninth transistor M9 and a gate of the tenth transistor M10, respectively; an output terminal of the third pull-up power source VS3 is electrically connected to the second pole of the ninth transistor M9, the second pole of the tenth transistor M10, and the second pole of the twelfth transistor M12, respectively; a first pole of the tenth transistor M10 is electrically connected to a first pole of the eleventh transistor M11 and a gate of the twelfth transistor M12, respectively; the gate of the eleventh transistor M11 is the second input terminal of the second comparing module; a first end of the fourth current mirror I4 is electrically connected to the second pole of the eighth transistor M8 and the second pole of the eleventh transistor M11, respectively, and a second end of the fourth current mirror I4 is connected to the first power signal; a first pole of the twelfth transistor M12 is electrically connected to the first terminal of the fifth current mirror I5 and the first terminal of the second nor gate group 510, respectively; the second end of the fifth current mirror I5 is connected to the first power supply signal; the second terminal of the second not-gate set 510 is the output terminal of the second comparing module.

The fourth current mirror I4 and the fifth current mirror I5 are both dc power supplies, and are used for providing bias current for the transistors. Alternatively, the third pull-up power source VS3 may be the same pull-up power source as the first pull-up power source VS1 and the second pull-up power source VS 2.

The working principle of the second comparison module is as follows:

when the compensation signal Vo2 is greater than the bias signal Vo1, the eighth transistor M8 is turned on and the eleventh transistor M11 is turned off; the first electrode of the eighth transistor M8 outputs a low level, so that the ninth transistor M9 and the tenth transistor M10 are turned on, the first terminal of the tenth transistor M10 outputs a high level, so that the twelfth transistor M12 is turned off, the first terminal of the second non-gate group 510 is connected to a low level, and after shaping of the second non-gate group 510, the second comparing module outputs 0.

When the compensation signal Vo2 is less than the bias signal Vo1, the eighth transistor M8 is turned off and the eleventh transistor M11 is turned on; the ninth transistor M9 and the tenth transistor M10 are turned off; the first terminal of the eleventh transistor M11 outputs a low level, so that the twelfth transistor M12 is turned on, the first terminal of the second non-gate group 510 is connected to a high level, and after shaping of the second non-gate group 510, the second comparing module outputs 1.

In this embodiment, the zero-cross comparison signal ZC can stably

output

0 or 1 by shaping an even number of non-gates in the second non-gate group 510.

The embodiment of the invention also provides a direct current conversion circuit, and the direct current conversion circuit can be applied to the self-calibration zero-crossing comparator provided by any embodiment of the invention.

Fig. 6 is a schematic structural diagram of a dc conversion circuit according to an embodiment of the present invention. As shown in fig. 6, the dc conversion circuit includes: a transformation module 620, a drive module 610, and a self-calibrating zero-crossing comparator 630 as provided by any of the embodiments of the invention;

the first output end 611 of the driving module 610 is electrically connected to the first control end 621 of the transformation module 620, the second output end 612 of the driving module 610 is electrically connected to the second control end 622 of the transformation module 620, and the input end 613 of the driving module 610 is electrically connected to the output end 631 of the self-calibration zero-crossing comparator 630; the input 632 of the self-calibrating zero-crossing comparator 630 is electrically connected to the sampling terminal 623 of the transformation module 620.

The first output end 611 of the driving module 610 outputs a first driving signal, and the second output end 612 of the driving module 610 outputs a second driving signal. The first driving signal and the second driving signal are used to control the operation mode of the transformation module 620. The self-calibration zero-crossing comparator 630 determines whether the zero-crossing flip point of the transformation module 620 is advanced or delayed by collecting the sampling voltage of the transformation module 620, and outputs a zero-crossing comparison signal according to the determination result to the driving module 610, so as to modify the second driving signal output by the driving module 610.

According to the direct current conversion circuit provided by the embodiment of the invention, the driving module corrects the second driving signal according to the zero-crossing comparison signal output by the self-calibration zero-crossing comparator, so that the working state of the conversion module is controlled, and the zero-crossing turning point is changed to improve the working efficiency and reduce the energy consumption. The self-calibration zero-crossing comparator outputs a zero-crossing comparison signal by comparing the magnitudes of the offset signal and the compensation signal. The first power supply signal is artificially biased by the compensation module, so that the sampling voltage can be compensated in an upward or downward direction, and the zero-crossing turnover point is corrected. And the comparison precision is improved by sampling in real time and adjusting the zero-crossing turning point. The sampling voltage which needs to be compensated upwards or downwards is determined by a logic module through logic operation, and the strict precision requirement and speed requirement on a comparator are not required. Therefore, the first comparison module and the second comparison module can adopt comparators with general precision, thereby reducing the manufacturing cost. Therefore, the embodiment of the invention can improve the precision of the zero-crossing comparator and reduce the energy consumption of the direct current conversion circuit on the basis of not increasing the cost.

On the basis of the above embodiment, further, the conversion module may include a synchronous BUCK dc conversion circuit (BUCK circuit). Fig. 7 is a schematic circuit structure diagram of a dc conversion circuit according to an embodiment of the present invention. As shown in fig. 7, the transforming module includes a thirteenth transistor M13, a fourteenth transistor M14, a first inductor L1, a second capacitor C2, and a first power supply VDD.

A gate of the thirteenth transistor M13 is used as a first control terminal of the conversion module, and a first pole of the thirteenth transistor M13 is electrically connected to the output terminal of the first power supply VDD; a second pole of the thirteenth transistor M13 is electrically connected to the first pole of the fourteenth transistor M14 and the first end of the first inductor L1, respectively, and serves as a sampling end of the transformation module; a gate of the fourteenth transistor M14 is used as a second control terminal of the inverter module, and a second pole of the fourteenth transistor M14 is connected to the first power signal and electrically connected to a second terminal of the second capacitor C2; the second end of the first inductor L1 is electrically connected with the first end of the second capacitor C2; the first terminal of the second capacitor C2 is the output terminal of the transform module.

Wherein the sampling point of the transform module is denoted by SW. When the load current is large, the conversion module operates in CCM mode, and the current waveform on the first inductor L1 is as shown in fig. 8. The waveform of the inductor current is a triangular wave whose average value is equal to the load current Iload 1. The time Ton at which the triangular wave rises is a time at which the thirteenth transistor M13 is turned on in fig. 7, and Toff is a time at which the thirteenth transistor M13 is turned off in fig. 7.

It can be seen from fig. 9 that if the load current is reduced to a certain level (i.e., Iload 2), the triangular wave of the current of the first inductor L1 may be partially below 0A, i.e., the first inductor L1 may have a negative current for a while. The inductor current will flow from the output of the conversion module to ground or to the first power supply VDD during this time, which causes a significant loss of energy and thus is extremely inefficient. In order to improve efficiency and reduce energy loss, the fourteenth transistor M14 needs to be turned off in time when the current of the first inductor L1 drops to 0, so as to avoid the generation of reverse current. The transform module is operated in Discontinuous Conduction Mode (DCM).

In fig. 9, Ton denotes a time when the thirteenth transistor M13 is turned on, Toff denotes a time when the thirteenth transistor M13 is turned off, and the fourteenth transistor M14 is turned on at the start of Toff; t1 represents the time for the current of the first inductor L1 to drop from an inverted peak to 0; t2 represents the time for the current of the first inductor L1 to fall from the positive peak to 0; t3 represents the time from 0 to the peak reversal of the current of the first inductor L1.

Corresponding to the current of the first inductor L1, in this case, the voltage at the sampling point SW changes as shown in fig. 9, when Toff starts (M2 is on), the current of the first inductor L1 is Iid2 at the positive peak, and the voltage at the sampling point SW is-V2 = -Iid2 Rdson, where Rdson is the on-resistance of the fourteenth transistor M14. When the current of the first inductor L1 drops to 0A, the voltage at the sampling point SW is 0V. When the current of the first inductor L1 decreases to the inverse peak value-Iid 1, the voltage at the sampling point SW is V3= Iid1 Rdson. Therefore, whether the current of the first inductor L1 crosses zero can be determined by the voltage value of the sampling point SW.

With continued reference to fig. 7, when the fourteenth transistor M14 is turned on, the fourteenth transistor M14 is turned off when the system finds that the current zero crossing of the first inductor L1, and the thirteenth transistor M13 is also turned off. At this time, two situations exist, one is that the zero crossing point is found to be too early, namely the zero crossing overturning point is earlier than the actual zero crossing point; the other is to find the zero crossing point too late, i.e. the zero crossing point is later than the actual zero crossing point.

Fig. 10 is a waveform diagram illustrating the current of the first inductor L1 and the voltage at the sampling point SW when the zero-crossing flipping point is too early according to an embodiment of the present invention. As shown in fig. 10, t1 is a time point when the fourteenth transistor M14 is actually turned off. At time t1, the current of the first inductor L1 is actually "positive", at this time, the fourteenth transistor M14 and the thirteenth transistor M13 are both turned off, and the inductor current can only freewheel through the body diode of the fourteenth transistor M14, so the voltage at the sampling point SW directly becomes-Vd 2, where Vd2 is the forward conduction voltage of the body diode of the fourteenth transistor M14. Until time t2, the next cycle begins, the thirteenth transistor M13 is turned on, and the voltage at the sampling point SW is pulled high again.

Fig. 11 is a waveform diagram illustrating a current of the first inductor L1 and a voltage of the sampling point SW when the zero-crossing flip point is too late according to an embodiment of the present invention. As shown in fig. 11, the time t3 is a time point when the fourteenth transistor M14 is actually turned off. At time t3, the current of the first inductor L1 is actually "negative", at this time, the fourteenth transistor M14 and the thirteenth transistor M13 are both turned off, and the current of the first inductor L1 can only freewheel through the body diode of the thirteenth transistor M13, so the voltage at the sampling point SW directly becomes VDD + Vd1, where Vd1 is the forward conduction voltage of the body diode of the thirteenth transistor M13. Until time t4, the next cycle begins with the thirteenth transistor M13 turning on, and the voltage at the sampling point SW is about VDD.

From the above analysis, it can be seen that if the zero crossing flip point is too early or too late, the voltage at the sampling point SW at the time of the flip is-Vd 2 or VDD + Vd 1. Therefore, the reference voltage of the first comparison module in the self-calibration zero-crossing comparator can be within the range of (-Vd 2, VDD + Vd 1). Alternatively, the reference voltage may be VDD/2, where the accuracy requirement for the first comparison block is VDD/4, and is therefore easily implemented.

For the direct current conversion circuit, the precision of the self-calibration zero-crossing comparator is within +/-R (Idc) of Rdson after a plurality of clock cycles. Therefore, the self-calibration zero-crossing comparator with required precision can be obtained by only reasonably setting the values of Idc and R.

Optionally, in the dc conversion circuit, the self-calibration zero-crossing comparator may operate all the time; or when the system is started, the self-calibration zero-crossing comparator runs for a plurality of periods to meet the precision requirement and then stops working.

With continued reference to fig. 7, further, the drive module includes: a feedback module 710, a pulse width modulation module 720, a pulse frequency modulation module 730, and a driving control module 740.

A first end of the feedback module 710 is electrically connected to an output end of the transformation module 620, a second end of the feedback module 710 is connected to the first power signal, and output ends of the feedback module 710 are electrically connected to a second input end of the pulse width modulation module 720 and a second input end of the pulse frequency modulation module 730, respectively; a first input terminal of the pulse width modulation module 720 is connected to a first reference signal Vrefr1, and an output terminal of the pulse width modulation module 720 is electrically connected to a first input terminal of the driving control module 740. Optionally, the pulse width modulation module 720 adjusts the output according to the first reference signal Vrefr1 and the output signal of the feedback module 710. For example, the first reference signal Vrefr1 may be set by itself according to the range and variation of the output signal of the feedback module 710. A first input end of the pulse frequency modulation module 730 is connected to the second reference signal Vrefr2, and an output end of the pulse frequency modulation module 730 is electrically connected to a second input end of the driving control module 740. Optionally, the pulse frequency modulation module 730 adjusts the output according to the second reference signal Vrefr2 and the output signal of the feedback module 710. For example, the second reference signal Vrefr2 may be set by itself according to the range and variation of the output signal of the feedback module 710. A third input terminal of the driving control module 740 is used as an input terminal of the driving module, a first output terminal of the driving control module 740 is used as a first output terminal of the driving module, and a second output terminal of the driving control module 740 is used as a second output terminal of the driving module.

Specifically, the feedback module 710 is composed of a second resistor R2, a third resistor R3, and an amplifier CM 1. The second resistor R2 and the third resistor R3 are connected in series and then connected in parallel to two ends of the second capacitor C2, the first input end of the amplifier CM1 is connected with the feedback reference signal Vfbref, and the second input end of the amplifier CM1 is connected between the second resistor R2 and the third resistor R3. The output voltage of the transformation module is divided by the second resistor R2 and the third resistor R3 to generate a feedback signal, and the amplifier CM1 amplifies an error between the feedback reference signal Vfbref and the feedback signal and generates a feedback output signal.

When the system is overloaded, the pwm module 720 adjusts the duty cycle according to the feedback output signal to adjust the output. When the system is lightly loaded, the pulse frequency modulation module 730 increases the efficiency by reducing the switching frequency according to the feedback output signal. Optionally, an oscillation circuit may be further included in the driving control module 740 to adjust the switching period.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A self-calibrating zero-crossing comparator, comprising: the device comprises a first comparison module, a logic module, a compensation module and a second comparison module;

2. The self-calibrating zero-crossing comparator according to claim 1, wherein the logic control signal comprises an n-bit logic control signal; wherein n is an integer greater than or equal to 4;

3. The self-calibrating zero-crossing comparator according to claim 2, wherein the compensation unit further comprises: a compensation resistor and a compensation transistor; the compensation resistor and the compensation transistor are connected in parallel; on a branch of the compensation unit, along the direction opposite to the current flow direction, the resistance value of a compensation resistor in the mth compensation unit is 2 times that of a compensation resistor in the m-1 th compensation unit;

wherein m is more than or equal to 2 and less than or equal to n, and m is an integer.

4. The self-calibrating zero-crossing comparator according to claim 1, wherein the first comparing module comprises: the first NOR gate, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the second pull-up power supply, the third current mirror and the first NOR gate group; wherein the first set of NOT gates comprises an odd number of series connected NOT gates;

5. The self-calibrating zero-crossing comparator according to claim 4, wherein the first comparing module further comprises: a first capacitor;

6. The self-calibrating zero-crossing comparator according to claim 1, wherein the logic module comprises: a second NOR gate, a flip-flop and a counter;

7. The self-calibrating zero-crossing comparator according to claim 1, wherein the second comparing module comprises: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fourth current mirror, a fifth current mirror, a third pull-up power supply, and a second not gate group; wherein the second set of NOT gates comprises an even number of NOT gates connected in series;

8. A dc conversion circuit, comprising: a transformation module, a drive module and a self-calibrating zero-crossing comparator as claimed in any one of claims 1 to 7;

9. The dc conversion circuit of claim 8, wherein the conversion module comprises a thirteenth transistor, a fourteenth transistor, a first inductor, a second capacitor, and a first power supply;

10. The dc conversion circuit according to claim 8 or 9, wherein the driving module includes: the device comprises a feedback module, a pulse width modulation module, a pulse frequency modulation module and a drive control module;