CN111490679A - Boost DC-DC control circuit - Google Patents

Boost DC-DC control circuit Download PDF

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Publication number
CN111490679A
CN111490679A CN202010468360.XA CN202010468360A CN111490679A CN 111490679 A CN111490679 A CN 111490679A CN 202010468360 A CN202010468360 A CN 202010468360A CN 111490679 A CN111490679 A CN 111490679A
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voltage
tube
pmos
control circuit
resistor
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不公告发明人
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Shenzhen Canding Microelectronics Co ltd
Shanghai Canrui Technology Co ltd
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Shenzhen Canding Microelectronics Co ltd
Shanghai Canrui Technology Co ltd
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Priority to CN202010468360.XA priority Critical patent/CN111490679A/en
Publication of CN111490679A publication Critical patent/CN111490679A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1563—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators without using an external clock
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a boost DC-DC control circuit, comprising: the source electrode of the synchronous tube is connected with the voltage input end through the energy storage inductor, and the drain electrode of the synchronous tube is connected with the voltage output end; the drain electrode and the source electrode of the switching tube are connected in parallel with the source electrode and the ground of the synchronous tube; the two divider resistors are connected in series with the voltage output end and the ground and output sampling voltage; the error amplifier compares and amplifies the sampling voltage and the first reference voltage to generate a direct current control signal; the current sampling and PWM comparison circuit samples the working current of the synchronous tube and generates a PWM signal according to the working current and the direct current control signal; and the power driving circuit controls the switching tube and the synchronous tube to be alternately conducted. The current sampling and PWM comparison circuit is used for sampling the current of the synchronous tube, and comparing the sampling signal with the output VEA of the error amplifier to generate the PWM control signal so as to integrate the current sampling circuit and the PWM comparator circuit together, thereby reducing the direct current consumption of the control circuit.

Description

Boost DC-DC control circuit
Technical Field
The invention relates to a DC-DC control circuit, in particular to a boosting DC-DC control circuit.
Background
With the development of semiconductor technology, the function integration of mobile electronic devices such as mobile phones and wearable products is more and more abundant, the power consumption of the devices is more and more large, the requirement for the capacity of a battery is increased, and the requirements of people for the standby time and the working time of the electronic devices are increased. Conventional Boost DC-DC converters, such as the Boost DC-DC converter disclosed in patent document CN104539145B, have complex control schemes and large current consumption, and are increasingly unable to meet the requirements of mobile electronic devices for low power consumption.
Thus, there is a need for a boost DC-DC control circuit having low power consumption characteristics.
Disclosure of Invention
The invention aims to provide a boost DC-DC control circuit to simplify the circuit and reduce the power consumption.
In order to achieve the above object, the present invention provides a step-up DC-DC control circuit, comprising: the source electrode of the synchronous PMOS tube is connected with a voltage input end through an energy storage inductor, and the drain electrode of the synchronous PMOS tube is connected with a voltage output end; the drain electrode and the source electrode of the switch NMOS tube are connected between the source electrode of the synchronous PMOS tube and the ground in parallel; the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between the voltage output end and the ground, and a sampling voltage is output between the first voltage-dividing resistor and the second voltage-dividing resistor; the error amplifier is arranged to compare and amplify the sampling voltage and a first reference voltage to generate a direct current control signal at an output end of the error amplifier; the first input end of the current sampling and PWM comparison circuit is connected with the output end of the error amplifier, the first input end and the second input end of the current sampling and PWM comparison circuit are respectively connected with the source electrode and the voltage output end of the synchronous PMOS tube, the current sampling and PWM comparison circuit is set to sample the working current of the synchronous PMOS tube during the starting period of the synchronous PMOS tube and generate a PWM signal according to the working current of the synchronous PMOS tube and the direct current control signal; and the input end of the power driving circuit is connected with the output end of the current sampling and PWM comparison circuit, the first output end of the power driving circuit is connected with the grid electrode of the switch NMOS tube, and the second output end of the power driving circuit is connected with the grid electrode of the synchronous PMOS tube so as to control the switch NMOS tube and the synchronous PMOS tube to be alternately conducted.
The current sampling and PWM comparison circuit comprises a first comparator, a first Schmitt phase inverter, a first NMOS tube and a first PMOS tube, wherein the first comparator and the first Schmitt phase inverter are sequentially connected, a drain electrode of the first NMOS tube and a drain electrode of the first PMOS tube are connected with a non-inverting input end of the first comparator, and a drain electrode of the second NMOS tube is connected with an inverting input end of the first comparator; the grid electrode of the first NMOS tube is in short circuit with the grid electrode of the second NMOS tube and is a first input end of the current sampling and PWM comparison circuit, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded through a first resistor and a second resistor respectively; a third resistor is directly arranged on the drain electrode of the first PMOS tube and the non-inverting input end of the first comparator, the grid electrode of the first PMOS tube is grounded, and the source electrode of the first PMOS tube is the second input end of the current sampling and PWM comparison circuit; the inverting input end of the first comparator is connected with the voltage output end through a fourth resistor, and the connection point of the fourth resistor and the voltage output end is the third output end.
The current sampling and PWM comparison circuit is connected with the power driving circuit through a fixed TON control circuit, the input end of the fixed TON control circuit is connected with the output end of the current sampling and PWM comparison circuit, the output end of the fixed TON control circuit is connected with the input end of the power driving circuit, and a duty ratio control signal is generated at the output end of the fixed TON control circuit according to a PWM signal and the input voltage of the voltage input end.
The duty ratio control signal is a square wave signal and can be divided into on time and off time, the on time is only controlled by the input voltage of the voltage input end and is unrelated to the PWM signal, and the off time is controlled by the PWM signal.
At the on-time of the duty ratio control signal, the switch NMOS tube is switched on, the synchronous PMOS tube is switched off, and the energy storage inductor stores energy; and at the turn-off time of the duty ratio control signal, the switch NMOS tube is closed, the synchronous PMOS tube is opened, and the energy storage inductor discharges to the load of the voltage output end.
The fixed TON control circuit comprises an operational amplifier, a second comparator, an SR trigger, a second Schmidt inverter, a fifth resistor, a sixth resistor, a seventh resistor, a charging capacitor, a third NMOS (N-channel metal oxide semiconductor) tube, a fourth NMOS tube, a second PMOS tube and a third PMOS tube; the non-inverting input end of the operational amplifier is connected with the voltage input end through the fifth resistor and is grounded through the sixth resistor, the output end of the operational amplifier is connected with the grid electrode of the third NMOS tube, the inverting input end of the operational amplifier and the source electrode of the third NMOS tube are grounded together through the seventh resistor, the drain electrode of the third NMOS tube is in short circuit with the grid electrode and the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube, and the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are both connected with the voltage input end; the drain electrode of the third PMOS tube is connected with the inverting input end of the second comparator and is grounded through the charging capacitor, the non-inverting input end of the second comparator is connected with a second reference voltage, the output end of the second comparator is connected with the input end of the second Schmitt phase inverter, the output end of the second Schmitt phase inverter is connected with the set end of the SR trigger, and the reset end of the SR trigger is connected with the PWM signal; the Q output end of the SR trigger is connected with the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected with the inverted input end of the second comparator; and the Qn output end of the SR trigger is the output end of the fixed TON control circuit so as to output the duty ratio control signal VDR.
The second Schmitt phase inverter comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; the grid electrode of the fifth NMOS tube, the grid electrode of the seventh NMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube are connected together in a short-circuit mode to serve as the input end of the second Schmidt phase inverter; the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected together in a short circuit; the grid electrode of the sixth NMOS tube, the drain electrode of the seventh NMOS tube, the grid electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube are connected together in a short circuit mode and serve as the output end of the second Schmidt inverter; the drain electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected together in a short circuit manner; the drain electrode of the fifth PMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the voltage input end.
An output voltage stabilizing capacitor is arranged between the voltage output end and the ground so as to stabilize the voltage of the voltage output end.
And a loop stability compensation circuit is arranged between the output end of the error amplifier and the ground.
The loop stability compensation circuit is arranged to compensate the boost DC-DC control circuit according to the small signal working characteristics of the loop, and the loop phase margin of the boost DC-DC control circuit is increased and ranges from 60 degrees to 90 degrees.
The boost DC-DC control circuit realizes current sampling of the synchronous tube through the current sampling and PWM comparison circuit, and compares the sampling signal with the output VEA of the error amplifier to generate the PWM control signal so as to integrate the current sampling circuit and the PWM comparator circuit, thereby simplifying the control circuit and reducing the direct current consumption of the control circuit. In addition, the boost DC-DC control circuit of the invention adopts a fixed TON control circuit to output a duty ratio control signal VDR with adjustable pulse width according to the input PWM signal and the input VIN signal, and the conduction time of the duty ratio control signal VDR is fixed, so that the internal circuit does not need slope compensation, and the control loop can respond quickly under the condition that the load size changes suddenly or the input VIN voltage changes suddenly.
Drawings
Fig. 1 is a schematic diagram of a boost DC-DC control circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a current sampling and PWM comparing circuit of the boost DC-DC control circuit shown in fig. 1.
Fig. 3 is a circuit diagram of a fixed TON control circuit of the boost DC-DC control circuit shown in fig. 1.
Fig. 4 is a circuit diagram of a schmitt inverter.
Detailed Description
An embodiment of the present invention will be described below in conjunction with the accompanying drawings, and the aspects of the present invention will be explained and explained in further detail.
Fig. 1 shows a boost DC-DC control circuit according to an embodiment of the present invention, which includes a switch NMOS transistor M1, a synchronous PMOS transistor M2, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, an error comparator EA, a loop stability compensation circuit 1, a current sampling and PWM comparing circuit 2, a fixed TON control circuit 3, and a power driving circuit 4.
The source of the synchronous PMOS transistor M2 is connected to a voltage input terminal VIN through an energy storage inductor L, the drain thereof is connected to a voltage output terminal VOUT, and the energy storage inductor L is an energy storage element for system operation.
The drain and the source of the switch NMOS transistor M1 are connected in parallel between the source of the synchronous PMOS transistor M2 and the ground.
An output voltage stabilizing capacitor C L is disposed between the voltage output terminal VOUT and ground to stabilize the voltage of the voltage output terminal VOUT, and the magnitude of the output voltage stabilizing capacitor C L can be set according to the requirement of the voltage ripple of the voltage output terminal VOUT.
A first voltage-dividing resistor R1 and a second voltage-dividing resistor R2 which are connected in series with each other are arranged between the voltage output end VOUT and the ground. A voltage division connection end is arranged between the first voltage division resistor R1 and the second voltage division resistor R2, the voltage division connection end is connected with the inverting input end of the error amplifier EA so as to output a sampling voltage VFB, the non-inverting input end of the error amplifier EA is connected with a first reference voltage VREF, and the first reference voltage VREF is generated by an internal band gap reference voltage module. The error amplifier EA is arranged to compare and amplify the sampled voltage VFB and the first reference voltage VREF to generate a dc control signal VEA at its output.
The loop stability compensation circuit 1 is arranged between the output end of the error amplifier EA and the ground, and the loop stability compensation circuit 1 is arranged to compensate the boost DC-DC control circuit according to the small signal working characteristic of the loop, and increase the phase margin PM (phase margin) of the boost DC-DC control circuit, so that the purpose that the boost DC-DC control circuit can stably work is achieved. The loop stability compensation circuit can be implemented by a series-parallel network of passive capacitors and resistors inside the integrated circuit, such as a common frequency compensation scheme of the second type (a first resistor is connected in series with a first capacitor and then connected in parallel with a second capacitor), and two poles (an initial pole and a high-frequency pole) and a low-frequency zero are added to increase a loop phase margin pm (phase margin). PM is 0 and the loop oscillates. The loop phase margin is set at 60-90 degrees.
The current sampling and PWM comparing circuit 2 has 3 input terminals and an output terminal, the first input terminal is connected to the output terminal of the error amplifier EA to receive the dc control signal VEA, the first input terminal and the second input terminal are respectively connected to the source SW of the synchronous PMOS transistor M2 and the voltage output terminal VOUT to sample the operating current of the synchronous PMOS transistor M2, the current sampling and PWM comparing circuit 2 is configured to sample the operating current of the synchronous PMOS transistor M2 during the turn-on period of the synchronous PMOS transistor M2, and generate a PWM signal according to the operating current of the synchronous PMOS transistor M2 and the dc control signal VEA, the PWM signal is used to control the turn-off time of the switch NMOS transistor M1, the output terminal of the current sampling and PWM comparing circuit 2 is connected to the input terminal of the fixed TON control circuit 3, wherein the operating current of the synchronous PMOS transistor M2 is obtained by sampling M2 through the voltage difference between the source SW of the synchronous PMOS transistor M2 and the voltage output terminal VOUT, and the operating current of the PMOS sampling transistor M2 can achieve the purpose of sampling the operating current of the indirect energy storage inductor.
As shown in fig. 2, the current sampling and PWM comparing circuit 2 includes a first comparator 101 and a first Schmitt (SMIT) inverter 102, a first NMOS transistor M101 and a first PMOS transistor M103 having drains connected to a non-inverting input terminal of the first comparator 101, and a second NMOS transistor M102 having a drain connected to an inverting input terminal of the first comparator 101, which are connected in sequence.
The grid electrode of the first NMOS transistor M101 is in short circuit with the grid electrode of the second NMOS transistor M102, is a first input end of the current sampling and PWM comparison circuit 2, is connected with the output end of the error amplifier EA, and the source electrode of the first NMOS transistor M101 and the source electrode of the second NMOS transistor M102 are grounded through a first resistor R101 and a second resistor R102 respectively; a third resistor R103 is directly arranged on the drain of the first PMOS transistor M103 and the non-inverting input terminal of the first comparator 101, the gate of the first PMOS transistor M103 is grounded, and the source of the first PMOS transistor M103 is the second input terminal of the current sampling and PWM comparing circuit 2 and is connected to the source SW of the synchronous PMOS transistor M2; the inverting input terminal of the first comparator 101 is connected to the voltage output terminal VOUT through a fourth resistor R104, and a connection point of the fourth resistor R104 and the voltage output terminal VOUT is the third output terminal.
Therefore, the first NMOS transistor M101, the second NMOS transistor M102, the resistor R101 and the resistor R102 form a V-I conversion circuit, the DC control signal VEA output by the error amplifier is converted into a current signal, and the drain current Id of the first NMOS transistor M101M101And a drain current Id of the second NMOS transistor M102M101Respectively as follows:
wherein, VEA is a direct current control signal, Vthn is the starting threshold voltage of the NMOS tube; one of the basic parameters provided by the integrated circuit device process; r101 and R102 are resistance values of the first resistor and the second resistor, respectively.
When the synchronous PMOS transistor M2 is turned on, the inductor current I L of the energy storage inductor L flows from the source SW of the synchronous PMOS transistor M2 to the voltage output terminal VOUT (i.e., the drain of the synchronous PMOS transistor M2), the drain current of the PMOS transistor M2 is equal to the inductor current I L, and at this time, the voltage difference between the source SW of the synchronous PMOS transistor M2 and the voltage output terminal VOUT is:
VSW-VVOUT＝IL×RdsonM2(2)
wherein, VSWTo synchronize the voltage of the source SW of the PMOS transistor M2, VOUTThe voltage at the voltage output terminal VOUT, I L is the inductor current, RdsonM2Is the on-resistance of the PMOS transistor M2.
The magnitude of the voltage VA at the non-inverting input terminal and the voltage VB at the inverting input terminal of the first comparator 101 are calculated as:
Figure BDA0002513416750000071
where VA and VB are the voltages at the non-inverting input terminal and the inverting input terminal of the first comparator 101, respectively, and VSWTo synchronize the voltage of the source SW of the PMOS transistor M2, VOUTIs the voltage of the voltage output terminal VOUT, IdM101Is the drain current, Id, of the first NMOS transistor M101M101Is the drain current of the second NMOS transistor M102, RdsonM103The on resistance of the first PMOS transistor M103 is, and R103 and R104 are resistance values of the third resistor and the fourth resistor, respectively.
Substituting the formula (1) and the formula (2) into the formula (3), and finishing the formula (4):
Figure BDA0002513416750000072
where VA and VB are the voltages at the non-inverting input terminal and the inverting input terminal of the first comparator 101, respectively, and VSWFor synchronizing the voltage at the source SW of the PMOS transistor M2, I L isInductive current, RdsonM2Is the on-resistance of PMOS transistor M2, RdsonM103The on-resistance of the first PMOS transistor M103, VEA is a direct current control signal, Vthn is a turn-on threshold voltage of the NMOS transistor, and R101, R102, R103, and R104 are resistance values of the first resistor, the second resistor, the third resistor, and the fourth resistor, respectively.
The first comparator 101 compares the voltages VA and VB of the non-inverting input terminal and the inverting input terminal of the first comparator 101, and when the voltage VA of the non-inverting input terminal of the first comparator 101 is greater than the voltage VB of the inverting input terminal, the first comparator 101 outputs a high voltage; conversely, the output of the first comparator 101 is a low voltage. The first schmitt inverter 102 is used to prevent the output terminal of the comparator 101 from voltage jitter when the voltage changes (e.g. low voltage changes to high voltage), and generate false pulses to the back end. 102 will not respond to small voltage jitter and will not output false pulses to the back end. Thus, the first schmitt inverter 102 outputs a stable PWM signal.
At the output voltage flipping point of the first comparator 101, the voltage VA at the non-inverting input terminal of the first comparator 101 is equal to the voltage VB at the inverting input terminal. According to the relationship of the formula (4), if the resistances of the first resistor R101 and the second resistor R102 are set to be equal, the resistances of the third resistor R103 and the fourth resistor R104 are set to be equal, and the device sizes of the first NMOS transistor M101 and the second NMOS transistor M102 are set to be equal, the relationship of the formula (5) can be obtained:
Figure BDA0002513416750000081
according to the relation of the formula (5), the boost DC-DC control circuit can realize the control of the magnitude of the inductive current by adjusting the magnitude of the direct current control signal VEA during the starting period of the synchronous PMOS tube M2.
Referring to fig. 1 again, the input terminal of the fixed TON control circuit 3 is connected to the output terminal of the current sampling and PWM comparing circuit 2, and the output terminal thereof is connected to the input terminal of the power driving circuit 4, and is configured to generate a duty ratio control signal VDR at the output terminal thereof according to the PWM signal and the input voltage of the voltage input terminal VIN, thereby providing a fixed on-time TON and an off-time controlled by the PWM signal.
The duty ratio control signal VDR is a square wave signal and can be divided into on time TON and off time TOFF; the on-time TON is fixed, that is, the on-time TON is controlled only by the input voltage of the voltage input terminal VIN and is not related to the PWM signal, and the off-time TOFF is controlled by the PWM signal. Circuit control schemes are generally divided into two categories: the problem of inherent subharmonic oscillation of a Pulse Width Modulation (PWM) control scheme in a PWM mode with fixed working frequency and a Pulse Frequency Modulation (PFM) with unfixed working frequency needs to be solved by slope compensation. The invention fixes the on time TON by the fixed TON control circuit 3, and automatically adjusts the off time TOFF under the control of the PWM signal, thereby realizing the PFM mode, having no secondary slope oscillation problem in the working principle and needing no slope compensation.
As shown in fig. 3, the fixed TON control circuit 3 includes an operational amplifier 201, a second comparator 202, an SR flip-flop 203, a second schmitt inverter 204, a fifth resistor R201, a sixth resistor R202, a seventh resistor R203, a charging capacitor C201, a third NMOS transistor M201, a fourth NMOS transistor M204, a second PMOS transistor M202, and a third PMOS transistor M203. The SR flip-flop 203 may be replaced with other logic circuits such as an SR latch.
The non-inverting input end of the operational amplifier 201 is connected to the voltage input end VIN through the fifth resistor R201 and is grounded through the sixth resistor R202, the output end of the operational amplifier 201 is connected to the gate of the third NMOS transistor M201, the inverting input end of the operational amplifier 201 and the source of the third NMOS transistor M201 are grounded through the seventh resistor R203, the drain of the third NMOS transistor M201 is short-circuited with the gate and the drain of the second PMOS transistor M202, the gate of the second PMOS transistor M202 is connected to the gate of the third PMOS transistor M203, and the source of the second PMOS transistor M202 and the source of the third PMOS transistor M203 are both connected to the voltage input end VIN. The drain of the third PMOS transistor M203 is connected to the inverting input terminal of the second comparator 202 and grounded through the charging capacitor C201, the non-inverting input terminal of the second comparator 202 is connected to the second reference voltage VREF2, the output terminal of the second comparator 202 is connected to the input terminal of the second schmitt inverter 204, the output terminal of the second schmitt inverter 204 is connected to the set terminal S of the SR flip-flop 203, and the reset terminal R of the SR flip-flop 203 is connected to the PWM signal. The Q output end of the SR flip-flop 203 is connected to the gate of the fourth NMOS transistor M204, the source of the fourth NMOS transistor M204 is grounded, and the drain of the fourth NMOS transistor M204 is connected to the inverting input end of the second comparator 202. The Qn output terminal of the SR flip-flop 203 is the output terminal of the fixed TON control circuit 3 to output the duty ratio control signal VDR.
Therefore, the fifth resistor R201, the sixth resistor R202, the seventh resistor R203, the operational amplifier 201, the third NMOS transistor M201, and the second PMOS transistor M202 form a V-I conversion circuit, and the drain current of the second PMOS transistor M202 is as shown in formula (6):
Figure BDA0002513416750000091
the second PMOS tube M202 and the third PMOS tube M203 form a PMOS current mirror, the current mirror proportion is 1: N, the third PMOS tube M203 outputs the mirror output current of the current mirror, the device dimension parameter width and length ratio W/L of the third PMOS tube M203 is N times of the width-length ratio W/L of the second PMOS tube M202, and the value of the current mirror proportion is 1: N, and the value of N is a positive integer.
The second comparator 202 compares the second reference voltage VREF2 with the charging voltage VR across the charging capacitor C201, the second schmitt inverter 204 attenuates the erroneous signal pulses output by the second comparator 202, and the SR flip-flop 203 generates the system switch control signal VDR according to the second schmitt inverter 204 and the PWM signal output by the current sampling and PWM comparing circuit 2. The fourth NMOS transistor M204 controls the charging capacitor C201 to charge periodically. Specifically, the fourth NMOS transistor M204 is turned off, the charging capacitor C201 is charged by the drain current IdM203 (i.e., the current mirror output current) of the third PMOS transistor M203, and the charging voltage VR increases; when the charging voltage VR rises to the second reference voltage VREF2, the second comparator 202 is turned over, the Q output terminal of the SR flip-flop 203 is high, the fourth NMOS transistor M204 is turned on, and the charge of the charging capacitor C201 is discharged quickly. The on-time TON is the time when the charging voltage VR rises from 0 to the second reference voltage VREF 2.
The charging voltage VR across the charging capacitor C201 is:
Figure BDA0002513416750000092
wherein C201 is the capacitance of the charging capacitor, N is the current mirror ratio, IdM202Is the drain current of the second PMOS transistor M202.
Therefore, the on-time TON of the switch NMOS transistor M1 is:
Figure BDA0002513416750000101
the IdM203 is a current mirror output current, C201 is a capacitance value of a charging capacitor, VREF2 is a second reference voltage, N is a current mirror ratio, VIN is an input voltage of a voltage input terminal, and R201, R202, and R203 are a fifth resistor, a sixth resistor, and a seventh resistor, respectively.
In this embodiment, the on-time TON may be taken as the on-time of the switch NMOS transistor M1, as shown in formula (8), after the input voltage of the voltage input terminal VIN is determined, the on-time, i.e. the time for which the switch NMOS transistor M1 is turned on each time, is a fixed value.
The first schmitt inverter 102 and the second schmitt inverter 204 have the same structure, are both Schmitt (SMIT) inverters existing in the market, and are characterized in that input high and low flip levels are unequal, and have hysteresis characteristics, so that unstable input peaks of input can be eliminated.
As shown in fig. 4, taking the second schmitt inverter 204 as an example, the second schmitt inverter 204 includes a fifth NMOS transistor M301, a sixth NMOS transistor M302, a seventh NMOS transistor M303, a fourth PMOS transistor M304, a fifth PMOS transistor M305, and a sixth PMOS transistor M306.
The source electrode of the fifth NMOS transistor M301 is connected to ground, and the gate electrode of the fifth NMOS transistor M301, the gate electrode of the seventh NMOS transistor M303, the gate electrode of the fourth PMOS transistor M304, and the gate electrode of the sixth PMOS transistor M306 are shorted together to serve as the input end of the second schmitt inverter 204; the drain electrode of the fifth NMOS tube M301, the source electrode of the sixth NMOS tube M302 and the source electrode of the seventh NMOS tube M303 are connected together in a short circuit; the grid electrode of the sixth NMOS tube M302, the drain electrode of the seventh NMOS tube M303, the grid electrode of the fifth PMOS tube M305 and the drain electrode of the sixth PMOS tube M306 are connected together in short to serve as the output end of the second Schmidt inverter 204; the drain electrode of the fourth PMOS tube M304, the source electrode of the fifth PMOS tube M305 and the source electrode of the sixth PMOS tube M306 are short-circuited together; the drain of the fifth PMOS transistor M305 is grounded, and the drain of the sixth NMOS transistor M302 is connected to the voltage input terminal VIN.
The input end of the power driving circuit 4 is connected with the output end of the current sampling and PWM comparing circuit 2 through the fixed TON control circuit 3 (i.e. connected with the output end of the fixed TON control circuit 3), and has a first output end and a second output end, the first output end is connected with the gate of the switch NMOS transistor M1, the second output end is connected with the gate of the synchronous PMOS transistor M2, and the gate driving signals NG and PG with strong driving capability are generated at the two output ends according to the duty ratio control signal VDR, so as to control the switch NMOS transistor M1 and the synchronous PMOS transistor M2 to be alternately turned on, therefore, at the on time TON of the duty ratio control signal VDR, the switch NMOS transistor M1 is turned on, the synchronous PMOS transistor M2 is turned off, and the energy storage inductor L stores energy, at the off time TOFF of the duty ratio control signal VDR, the switch NMOS transistor M1 is turned off, the synchronous PMOS transistor M2 is turned on, and the energy storage inductor L discharges to.
In addition, in order to prevent the switching NMOS transistor M1 and the synchronous PMOS transistor M2 from passing through, there is a certain dead time between the gate driving signals NG and PG.
The boost DC-DC control circuit realizes the current sampling of the M2 tube through the current sampling and PWM comparison circuit 2, and compares the sampling signal with the DC control signal VEA output by the error amplifier to generate the PWM control signal, so as to integrate the current sampling circuit and the PWM comparator circuit, simplify the control circuit and reduce the DC consumption of the control circuit. In addition, the boost DC-DC control circuit of the invention adopts a fixed TON control circuit to output a duty ratio control signal VDR with adjustable pulse width according to the input PWM signal and the input VIN signal, and the on-time TON of the duty ratio control signal VDR is fixed, so that the internal circuit does not need slope compensation, and the control loop can respond quickly under the condition that the load size is suddenly changed or the input VIN voltage is suddenly changed.
The above embodiments are merely preferred embodiments of the present invention, which are not intended to limit the scope of the present invention, and various changes may be made in the above embodiments of the present invention. All simple and equivalent changes and modifications made according to the claims and the content of the specification of the present application fall within the scope of the claims of the present patent application. The invention has not been described in detail in order to practice the invention.

Claims (10)

1. A boost DC-DC control circuit, comprising:
a synchronous PMOS transistor (M2), the source of which is connected to a voltage input terminal (VIN) via an energy storage inductor (L), and the drain of which is connected to a voltage output terminal (VOUT);
a switch NMOS transistor (M1), the drain and source of which are connected in parallel between the source of the synchronous PMOS transistor (M2) and the ground;
a first voltage-dividing resistor (R1) and a second voltage-dividing resistor (R2) connected in series between the voltage output terminal (VOUT) and ground, and a sampling Voltage (VFB) is output between the first voltage-dividing resistor (R1) and the second voltage-dividing resistor (R2);
-the Error Amplifier (EA) is arranged to amplify the sampled Voltage (VFB) in comparison with a first reference Voltage (VREF) to generate a dc control signal (VEA) at its output;
the current sampling and PWM comparison circuit (2) is provided with a first input end connected with the output end of the Error Amplifier (EA), a first input end and a second input end respectively connected with a source electrode (SW) and a voltage output end (VOUT) of the synchronous PMOS tube (M2), is set to sample the working current of the synchronous PMOS tube (M2) during the starting period of the synchronous PMOS tube (M2), and generates a PWM signal according to the working current of the synchronous PMOS tube (M2) and the direct current control signal (VEA); and
and the input end of the power driving circuit (4) is connected with the output end of the current sampling and PWM comparison circuit (2), the first output end of the power driving circuit is connected with the grid electrode of the switch NMOS tube (M1), and the second output end of the power driving circuit is connected with the grid electrode of the synchronous PMOS tube (M2) so as to control the switch NMOS tube (M1) and the synchronous PMOS tube (M2) to be alternately conducted.
2. The boost DC-DC control circuit according to claim 1, wherein the current sampling and PWM comparing circuit (2) comprises a first comparator (101) and a first schmitt inverter (102) connected in sequence, a first NMOS transistor (M101) and a first PMOS transistor (M103) having drains connected to a non-inverting input terminal of the first comparator (101), and a second NMOS transistor (M102) having drains connected to an inverting input terminal of the first comparator (101); the grid electrode of the first NMOS tube (M101) is in short circuit with the grid electrode of the second NMOS tube (M102) and is a first input end of the current sampling and PWM comparison circuit (2), and the source electrode of the first NMOS tube (M101) and the source electrode of the second NMOS tube (M102) are grounded through a first resistor (R101) and a second resistor (R102) respectively; a third resistor (R103) is directly arranged at the drain electrode of the first PMOS tube (M103) and the non-inverting input end of the first comparator (101), the grid electrode of the first PMOS tube (M103) is grounded, and the source electrode of the first PMOS tube (M103) is the second input end of the current sampling and PWM comparison circuit (2); the inverting input end of the first comparator (101) is connected with the voltage output end (VOUT) through a fourth resistor (R104), and the connection point of the fourth resistor (R104) and the voltage output end (VOUT) is the third output end.
3. A boost DC-DC control circuit according to claim 1, characterized in that the current sampling and PWM comparison circuit (2) and the power driver circuit (4) are connected via a fixed TON control circuit (3), the input of the fixed TON control circuit (3) being connected to the output of the current sampling and PWM comparison circuit (2), the output of the fixed TON control circuit being connected to the input of the power driver circuit (4) and being arranged to generate a duty cycle magnitude control signal (VDR) at the output thereof in dependence on the PWM signal and the input voltage of the Voltage Input (VIN).
4. A boost DC-DC control circuit according to claim 3, characterized in that the duty cycle magnitude control signal (VDR) is a square wave signal, divided into an on-time controlled only by the input voltage at the Voltage Input (VIN) and independent of the PWM signal and an off-time controlled by the PWM signal.
5. The boost DC-DC control circuit according to claim 4, wherein the switch NMOS transistor (M1) is turned on and the synchronous PMOS transistor (M2) is turned off during the on-time of the duty ratio magnitude control signal (VDR), and the energy storage inductor (L) stores energy, and the switch NMOS transistor (M1) is turned off and the synchronous PMOS transistor (M2) is turned on during the off-time of the duty ratio magnitude control signal (VDR), and the energy storage inductor (L) discharges to the load of the voltage output terminal (VOUT).
6. The boost DC-DC control circuit according to claim 3, wherein the fixed TON control circuit (3) comprises an operational amplifier (201), a second comparator (202), an SR flip-flop (203), a second Schmitt inverter (204), a fifth resistor (R201), a sixth resistor (R202), a seventh resistor (R203), a charging capacitor (C201), a third NMOS transistor (M201), a fourth NMOS transistor (M204), a second PMOS transistor (M202), and a third PMOS transistor (M203);
the non-inverting input end of the operational amplifier (201) is connected with the voltage input end (VIN) through the fifth resistor (R201) and is grounded through the sixth resistor (R202), the output end of the operational amplifier (201) is connected with the grid electrode of the third NMOS tube (M201), the inverting input end of the operational amplifier (201) and the source electrode of the third NMOS tube (M201) are grounded through the seventh resistor (R203), the drain electrode of the third NMOS tube (M201) is in short circuit with the grid electrode and the drain electrode of the second PMOS tube (M202), the grid electrode of the second PMOS tube (M202) is connected with the grid electrode of the third PMOS tube (M203), and the source electrode of the second PMOS tube (M202) and the source electrode of the third PMOS tube (M203) are both connected with the voltage input end (VIN); the drain of the third PMOS tube (M203) is connected with the inverting input end of the second comparator (202) and is grounded through the charging capacitor (C201), the non-inverting input end of the second comparator (202) is connected with a second reference voltage (VREF2), the output end of the second comparator (202) is connected with the input end of the second Schmitt inverter (204), the output end of the second Schmitt inverter (204) is connected with the set end (S) of the SR trigger (203), and the reset end (R) of the SR trigger (203) is connected with the PWM signal; the Q output end of the SR trigger (203) is connected with the grid electrode of a fourth NMOS transistor (M204), the source electrode of the fourth NMOS transistor (M204) is grounded, and the drain electrode of the fourth NMOS transistor (M204) is connected with the inverting input end of the second comparator (202); and the Qn output end of the SR trigger (203) is the output end of the fixed TON control circuit (3) so as to output the duty ratio control signal VDR.
7. The boost DC-DC control circuit according to claim 6, wherein the second Schmitt inverter (204) comprises a fifth NMOS transistor (M301), a sixth NMOS transistor (M302), a seventh NMOS transistor (M303), a fourth PMOS transistor (M304), a fifth PMOS transistor (M305), and a sixth PMOS transistor (M306); the source electrode of the fifth NMOS tube (M301) is connected to the ground, and the grid electrode of the fifth NMOS tube (M301), the grid electrode of the seventh NMOS tube (M303), the grid electrode of the fourth PMOS tube (M304) and the grid electrode of the sixth PMOS tube (M306) are connected together in a short circuit mode to serve as the input end of the second Schmidt inverter (204); the drain electrode of the fifth NMOS tube (M301), the source electrode of the sixth NMOS tube (M302) and the source electrode of the seventh NMOS tube (M303) are connected together in a short circuit manner; the grid electrode of the sixth NMOS tube (M302), the drain electrode of the seventh NMOS tube (M303), the grid electrode of the fifth PMOS tube (M305) and the drain electrode of the sixth PMOS tube (M306) are connected in short to be used as the output end of the second Schmidt inverter (204); the drain electrode of the fourth PMOS tube (M304), the source electrode of the fifth PMOS tube (M305) and the source electrode of the sixth PMOS tube (M306) are connected together in a short circuit mode; the drain electrode of the fifth PMOS tube (M305) is grounded, and the drain electrode of the sixth NMOS tube (M302) is connected with the voltage input end (VIN).
8. The boost DC-DC control circuit of claim 1, wherein an output stabilization capacitor (C L) is provided between the voltage output terminal (VOUT) and ground to stabilize the voltage at the voltage output terminal (VOUT).
9. A boost DC-DC control circuit according to claim 1, characterized in that a loop stability compensation circuit (1) is provided between the output of the Error Amplifier (EA) and ground.
10. The boost DC-DC control circuit according to claim 9, wherein the loop stability compensation circuit (1) is configured to compensate the boost DC-DC control circuit according to a small signal operation characteristic of a loop, and to increase a loop phase margin of the boost DC-DC control circuit, the loop phase margin being 60-90 degrees.
CN202010468360.XA 2020-05-28 2020-05-28 Boost DC-DC control circuit Pending CN111490679A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542939A (en) * 2020-12-22 2021-03-23 成都启臣微电子股份有限公司 Primary side feedback synchronous response circuit
CN113517814A (en) * 2021-08-26 2021-10-19 上海泰矽微电子有限公司 BOOST switch converter and minimum closing time control circuit
CN114726208A (en) * 2022-05-07 2022-07-08 电子科技大学 PWM control circuit of peak current mode buck converter
CN114785127A (en) * 2022-04-15 2022-07-22 西安电子科技大学重庆集成电路创新研究院 Multi-mode smooth-transition wide-input-range DC-DC converter
WO2023034191A1 (en) * 2021-08-30 2023-03-09 Texas Instruments Incorporated Type-2 compensation with reduced quiescent current
CN115955221A (en) * 2023-03-14 2023-04-11 昂赛微电子（上海）有限公司 High-side voltage comparison circuit and control method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542939A (en) * 2020-12-22 2021-03-23 成都启臣微电子股份有限公司 Primary side feedback synchronous response circuit
CN113517814A (en) * 2021-08-26 2021-10-19 上海泰矽微电子有限公司 BOOST switch converter and minimum closing time control circuit
CN113517814B (en) * 2021-08-26 2022-05-20 上海泰矽微电子有限公司 BOOST switch converter and minimum closing time control circuit
WO2023034191A1 (en) * 2021-08-30 2023-03-09 Texas Instruments Incorporated Type-2 compensation with reduced quiescent current
US11916486B2 (en) 2021-08-30 2024-02-27 Texas Instruments Incorporated Type-2 compensation with reduced quiescent current
CN114785127A (en) * 2022-04-15 2022-07-22 西安电子科技大学重庆集成电路创新研究院 Multi-mode smooth-transition wide-input-range DC-DC converter
CN114785127B (en) * 2022-04-15 2024-04-02 西安电子科技大学重庆集成电路创新研究院 Multi-mode smooth transition wide-input-range DC-DC converter
CN114726208A (en) * 2022-05-07 2022-07-08 电子科技大学 PWM control circuit of peak current mode buck converter
CN114726208B (en) * 2022-05-07 2023-04-28 电子科技大学 PWM control circuit of peak current mode buck converter
CN115955221A (en) * 2023-03-14 2023-04-11 昂赛微电子（上海）有限公司 High-side voltage comparison circuit and control method thereof

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