CN108572274B - Zero-crossing detection circuit and DC-DC converter - Google Patents
Zero-crossing detection circuit and DC-DC converter Download PDFInfo
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- CN108572274B CN108572274B CN201710141109.0A CN201710141109A CN108572274B CN 108572274 B CN108572274 B CN 108572274B CN 201710141109 A CN201710141109 A CN 201710141109A CN 108572274 B CN108572274 B CN 108572274B
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Abstract
A zero-cross detection circuit and a DC-DC converter, the zero-cross detection circuit comprising: the device comprises a first level translation unit, a second level translation unit and a comparison unit; the first level translation unit is suitable for performing forward translation on a level to be detected to obtain a first translation signal, and the first translation signal is a positive level; the second level shift unit is suitable for carrying out forward shift on the ground level to obtain a second shift signal, and the shift amplitude of the second level shift unit is equal to the shift amplitude of the first level shift unit; the comparison unit compares the first and second translation signals to obtain a zero-crossing detection signal. The technical scheme of the invention can improve the accuracy.
Description
Technical Field
The invention relates to the field of circuits, in particular to a zero-crossing detection circuit and a DC-DC converter.
Background
The zero-crossing detection circuit is widely applied, generally, the zero-crossing detection circuit is realized by a comparator, the voltage to be compared and a zero level are compared by the comparator, and the output of the comparator is used as a detection result.
The zero-crossing detection circuit can be applied to a power supply, such as a synchronous rectification buck-type DC-DC converter. The DC-DC converter has two modes of operation: a Continuous Conduction Mode (CCM) and a Discontinuous Conduction Mode (DCM). In the inductor discharge stage in the DCM mode, if the inductor current drops below zero, a current backflow phenomenon occurs, which greatly consumes the energy provided to the output load, resulting in a reduction in the converter efficiency. Therefore, there is a need for an accurate Zero-cross detector (ZCD) that can rapidly turn off the low-side rectifier when the inductor current drops to Zero to minimize current back-flow.
The precision of the existing zero-crossing detection circuit needs to be improved. When the existing zero-crossing detection circuit is used for a synchronous rectification buck-type DC-DC converter, the detection effect needs to be improved.
Disclosure of Invention
The invention aims to improve the accuracy of a zero-crossing detection circuit.
To solve the above technical problem, an embodiment of the present invention provides a zero-cross detection circuit, including: the device comprises a first level translation unit, a second level translation unit and a comparison unit; the first level translation unit is suitable for performing forward translation on a level to be detected to obtain a first translation signal, and the first translation signal is a positive level; the second level shift unit is suitable for carrying out forward shift on the ground level to obtain a second shift signal, and the shift amplitude of the second level shift unit is equal to the shift amplitude of the first level shift unit; the comparison unit compares the first and second translation signals to obtain a zero-crossing detection signal.
Optionally, the first level shift unit includes: the grid electrode of the first PMOS tube is connected to the level to be detected, the source electrode of the first PMOS tube is connected to a current source, and a source electrode signal of the first PMOS tube is used as the first translation signal.
Optionally, the second level shift unit includes: and the grid electrode of the second PMOS tube is connected to the ground level, the source electrode of the second PMOS tube is connected to the current source, and the source electrode signal of the second PMOS tube is used as the second translation signal.
Optionally, the comparing unit includes a comparator, two input ends of the comparator respectively input the first and second translation signals, and the zero-crossing detection signal is obtained according to an output signal of the comparator.
Optionally, the comparing unit includes an amplifying circuit and a comparator, and the amplifying circuit includes a first amplifying sub-circuit and a second amplifying sub-circuit; the first amplification sub-circuit is suitable for amplifying the first translation signal to obtain a first amplification signal; the second amplification sub-circuit is suitable for amplifying the second translation signal to obtain a second amplified signal, and the amplification amplitude of the second amplification sub-circuit is equal to that of the first amplification sub-circuit; the two input ends of the comparator are respectively connected with the first amplification signal and the second amplification signal, and the zero-crossing detection signal is obtained according to the output signal of the comparator.
Optionally, the first amplifying sub-circuit includes: a first NMOS transistor and a third PMOS transistor; the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, and the grid electrode of the first NMOS tube is connected with a bias voltage; the source electrode of the third PMOS tube is connected to a current source, the grid electrode of the third PMOS tube is connected to the first translation signal, and the drain electrode signal of the third PMOS tube is used as the first amplification signal.
Optionally, the second amplifying sub-circuit includes: a second NMOS transistor and a fourth PMOS transistor; the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected to the drain electrode of the fourth PMOS tube, and the grid electrode of the second NMOS tube is connected with a bias voltage; the source electrode of the fourth PMOS tube is connected to a current source, the grid electrode of the fourth PMOS tube is connected to the second translation signal, and the drain electrode signal of the fourth PMOS tube is used as the second amplification signal.
Optionally, the comparator includes: a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor; the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected to the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded; the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected to the grid electrode of the fifth NMOS tube; the source electrode of the fifth NMOS tube is grounded, the drain electrode of the fifth NMOS tube is connected to a current source, and a drain electrode signal of the fifth NMOS tube is used as an output signal of the comparator; the grid electrode of the fifth PMOS tube is connected to one of the two input ends of the comparator, the source electrode of the fifth PMOS tube is connected to the current source, and the drain electrode of the fifth PMOS tube is connected to the drain electrode of the third NMOS tube; the grid electrode of the sixth PMOS tube is connected to the other input end of the two input ends of the comparator, the source electrode of the sixth PMOS tube is connected to the current source, and the drain electrode of the sixth PMOS tube is connected to the drain electrode of the fourth NMOS tube.
Optionally, the zero-crossing detection circuit further includes: and the waveform shaping unit is used for carrying out waveform shaping on the output signal of the comparator so as to obtain the zero-crossing detection signal.
Optionally, the waveform shaping unit includes an even number of inverters connected in series.
The embodiment of the invention also provides a synchronous rectification buck-type DC-DC converter, which comprises a zero-crossing detection end, the zero-crossing detection circuit and a synchronous rectifier tube, wherein a zero-crossing detection signal output by the zero-crossing detection circuit is used for controlling the working state of the synchronous rectifier tube, and the level to be detected is a signal of the zero-crossing detection end.
Optionally, when the level to be detected is lower than the ground level, the zero-crossing detection signal controls the synchronous rectifier tube to be turned off.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the first level translation unit carries out forward translation on the level to be detected to obtain a first translation signal, the second level translation unit carries out forward translation on the ground level to obtain a second translation signal, the translation amplitude of the first level translation unit is the same as that of the second level translation unit, and therefore the comparison unit compares the first translation signal with the second translation signal to obtain the relation between the level to be detected and the ground level. If a common comparator is used for directly comparing the negative level and the ground level, larger time delay occurs and the precision is insufficient. In the embodiment of the invention, the first translation signal is a positive level, the second level translation unit carries out forward translation on the ground level to obtain the second translation signal, so that the second translation signal is also a positive level, and the comparison unit is used for comparing the two positive levels, so that the accuracy is higher, the delay is smaller, and the comparison result between the to-be-detected level and the ground level with smaller delay and higher accuracy can be further obtained.
In addition, the synchronous rectification buck-type DC-DC converter in the embodiment of the present invention utilizes the zero-crossing detection circuit to detect the zero-crossing end, determines whether the inductor current drops below zero by detecting the level of the zero-crossing end, and controls the operating state of the synchronous rectification tube according to the zero-crossing detection signal output by the zero-crossing detection circuit. The normal output level of the zero-crossing detection end is negative, so that if the level of the zero-crossing detection end is directly judged by using the conventional comparator, the precision is low, the time delay is large, the rectifier tube cannot be turned off in time, and backflow is caused; the zero-crossing detection circuit in the embodiment of the invention can more accurately determine the zero point, and can timely turn off the rectifier tube when the inductive current is reduced to zero, thereby reducing the current back-flow.
Drawings
Fig. 1 is a schematic structural diagram of a zero-crossing detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another zero-crossing detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a partial structure of a zero-crossing detection circuit according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of an amplifier circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a comparator according to an embodiment of the present invention.
Detailed Description
As described above, the zero-cross detection circuit is generally implemented by a comparator, and the voltage to be compared and the zero level are compared by the comparator, and the output of the comparator is used as the detection result.
The inventor researches and finds that the comparator is usually supplied by a single power supply and cannot identify a voltage signal smaller than zero, so that when the zero point of a signal changing from negative to positive needs to be judged, a larger time delay occurs when the comparator is directly used for identification, and the accuracy is poor.
In the embodiment of the invention, the first level translation unit carries out forward translation on the level to be detected to obtain the first translation signal, the second level translation unit carries out forward translation on the ground level to obtain the second translation signal, the translation amplitude of the first level translation unit is the same as that of the second level translation unit, and therefore, the comparison unit compares the first translation signal with the second translation signal to obtain the relation between the level to be detected and the ground level.
If a common comparator is used for directly comparing the negative level and the ground level, larger time delay occurs and the precision is insufficient. In the embodiment of the invention, the first translation signal is a positive level, the second level translation unit carries out forward translation on the ground level to obtain the second translation signal, so that the second translation signal is also a positive level, and the comparison unit is used for comparing the two positive levels, so that the accuracy is higher, the delay is smaller, and the comparison result between the to-be-detected level and the ground level with smaller delay and higher accuracy can be further obtained.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic structural diagram of a zero-crossing detection circuit in an embodiment of the present invention, which may include:
the first level shifting unit 11 is adapted to perform forward shifting on a level to be detected to obtain a first shifted signal, where the first shifted signal is a positive level;
a second level shift unit 12, adapted to perform forward shift on the ground level to obtain a second shift signal, wherein a shift amplitude of the second level shift unit 12 is equal to a shift amplitude of the first level shift unit 11;
the comparison unit 13 compares the first and second shifted signals to obtain a zero-crossing detection signal.
The first level shift unit 11 and the second level shift unit 12 may be implemented in various forms, may be implemented in a MOS transistor circuit, or may also be implemented in a triode circuit. The forward shift can be to shift the gate-source voltage of the PMOS transistor operating in the saturation region, or to shift the gate-source voltage of a transistor or the gate-source voltages of a plurality of transistors.
In order to ensure that the shift amplitude of the first level shift unit 11 is the same as the shift amplitude of the second level shift unit 12, the first level shift unit 11 and the second level shift unit 12 may adopt the same circuit structure.
In a specific implementation, the comparing unit 13 may include a comparator, two input terminals of the comparator respectively input the first and second shifted signals, the comparator compares the first and second shifted signals, and the zero-crossing detection signal may be obtained according to an output signal of the comparator.
Referring to fig. 2, in another specific implementation, the comparing unit 13 may include an amplifying circuit 131 and a comparator 132, and the amplifying circuit 131 may include a first amplifying sub-circuit 1311 and a second amplifying sub-circuit 1312, wherein: the first amplification sub-circuit 1311 may be connected to the first level shift unit 11, and amplifies the first shifted signal to obtain a first amplified signal; the second amplification sub-circuit 1312 may be connected to the second level shifting unit 12, and amplifies the second shifted signal to obtain a second amplified signal. The amplification of the first amplification sub-circuit 1311 is equal to the amplification of the second amplification sub-circuit 1312.
Two input terminals of the comparator 132 may be respectively connected to the first amplification sub-circuit 1311 and the second amplification sub-circuit 1312 to respectively access the first amplification signal and the second amplification signal, and the zero crossing detection signal may be generated according to an output signal of the comparator 132.
To ensure that the amplification degree of the first amplification sub-circuit 1311 and the amplification degree of the second amplification sub-circuit 1312 are the same, the same circuit configuration may be adopted for both.
It is understood by those skilled in the art that "first" and "second" in the embodiments of the present invention are merely used to distinguish different objects, and do not represent specific limitations to the implementation manner thereof.
With reference to fig. 1, the zero crossing detection circuit in the embodiment of the present invention may further include a waveform shaping unit 14, which performs waveform shaping on an output signal of the comparator in the comparison unit 13, so as to obtain the zero crossing detection signal.
The waveform shaping unit 14 may be constructed based on an inverter, and may include an even number of inverters, for example. The waveform shaping unit 14 may have other configurations that can be realized by those skilled in the art.
To describe the zero crossing detection circuit in the present invention in more detail, the following description is further provided with reference to fig. 3 to 5.
Fig. 3 is a schematic diagram of a partial structure of a zero-crossing detection circuit in an embodiment of the present invention, where:
the first level shift unit 11 may include: a first PMOS transistor MP1, a gate of the first PMOS transistor MP1 is connected to the level SW to be detected, a source of the first PMOS transistor MP1 is connected to the current source 31, the current source 31 is connected to the voltage VDD to generate a current, and a source signal T1 of the first PMOS transistor MP1 is used as the first shift signal.
The second level shift unit 12 may employ the same circuit configuration as the first level shift unit 11. That is, the second level shift unit 12 may include: a second PMOS transistor MP2, a gate of the second PMOS transistor MP2 is connected to the ground GND, a source of the second PMOS transistor MP2 is connected to the current source 31, and a source signal T2 of the second PMOS transistor MP2 is used as the second shift signal.
The drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2 can be grounded. The current source 31 may be a mirror current source, and the currents input to the first level shift unit 11 and the second level shift unit 12 are equal. The current source 31 may be in other forms other than fig. 3, and may also have other branches, the bias voltage terminal CTR may be connected to the bias voltage provided by the tail current source 32, and since the bias voltage terminal CTR is simultaneously connected to the gate of the MOS transistor in the mirror current source, the voltage thereof may also control the current magnitude of each other branch of the mirror current source.
Fig. 4 is a schematic structural diagram of an amplifying circuit according to an embodiment of the present invention, which is further described below with reference to fig. 3 and 4.
The first amplifying sub-circuit 42 may include a first NMOS transistor MN1 and a third PMOS transistor MP 3; the source electrode of the first NMOS transistor MN1 is groundedGND, the drain of the first NMOS transistor MN1 is connected to the drain of the third PMOS transistor MP3, and the gate of the first NMOS transistor MN1 is connected to a bias voltage VBIASN(ii) a The source of the third PMOS transistor MP3 is connected to a current source 41, the current source 41 is connected to a voltage VDD to generate a current, the gate of the third PMOS transistor MP3 is connected to the first shift signal, for example, a source signal T1 of the first PMOS transistor MP1 can be connected, and a drain signal a1 of the third PMOS transistor MP3 is used as the first amplification signal. The current source 41 in fig. 4 may be the same current source as the current source 31 in fig. 3, and the bias voltage terminal CTR in fig. 4 may be connected to the bias voltage terminal CTR in fig. 3 and the bias voltage terminal CTR in fig. 5.
The second amplifying sub-circuit 43 may include a second NMOS transistor MN2 and a fourth PMOS transistor MP 4; a source of the second NMOS transistor MN2 is grounded GND, a drain of the second NMOS transistor MN2 is connected to a drain of the fourth PMOS transistor MP4, and a gate of the second NMOS transistor MN2 is connected to a bias voltage VBIASN(ii) a The source of the fourth PMOS transistor MP4 is connected to a current source 41, the gate of the fourth PMOS transistor MP4 is connected to the second shift signal, for example, the source signal T2 of the second PMOS transistor can be connected, and the drain signal a2 of the fourth PMOS transistor MP4 is used as the second amplified signal.
Fig. 5 is a schematic structural diagram of a comparator according to an embodiment of the present invention, which is described below with reference to fig. 3 to 5.
The comparator includes: a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP 6;
the grid electrode of the third NMOS transistor MN3 and the grid electrode of the fourth NMOS transistor MN4 are connected to the drain electrode of the third NMOS transistor MN3 in common, and the source electrode of the third NMOS transistor MN3 is grounded;
the source electrode of the fourth NMOS transistor MN4 is grounded, and the drain electrode of the fourth NMOS transistor MN4 is connected to the gate electrode of the fifth NMOS transistor MN 5;
the source of the fifth NMOS transistor MN5 is grounded, the drain of the fifth NMOS transistor MN5 is connected to the current source 51, the current source 31 is connected to the voltage VDD to generate a current, and the drain signal C1 of the fifth NMOS transistor MN5 serves as an output signal of the comparator;
a gate of the fifth PMOS transistor MP5 is connected to one of the two input terminals of the comparator, and can access a drain signal T2 of the fourth PMOS transistor, a source of the fifth PMOS transistor MP5 is connected to the current source 51, and a drain of the fifth PMOS transistor MP5 is connected to a drain of the third NMOS transistor MN 3;
the gate of the sixth PMOS transistor MP6 is connected to the other of the two input terminals of the comparator, and can be connected to the drain signal T1 of the third PMOS transistor, the source of the sixth PMOS transistor MP6 is connected to the current source 51, and the drain of the sixth PMOS transistor MP6 is connected to the drain of the fourth NMOS transistor MN 4.
The output signal of the comparator can pass through two inverters to obtain the output signal of the zero-crossing detection circuit.
In the implementation of the present invention, each of the blocks in fig. 1 may adopt a circuit structure as shown in fig. 3 to 5, or a part of the blocks in fig. 1 may adopt the circuit structures shown in fig. 3 to 5, and each of the blocks in fig. 1 may also adopt other circuit structures that can be implemented by those skilled in the art.
In the embodiment of the invention, the first level translation unit carries out forward translation on the level to be detected to obtain the first translation signal, the second level translation unit carries out forward translation on the ground level to obtain the second translation signal, the translation amplitude of the first level translation unit is the same as that of the second level translation unit, and therefore, the comparison unit compares the first translation signal with the second translation signal to obtain the relation between the level to be detected and the ground level. If a common comparator is used for directly comparing the negative level and the ground level, larger time delay occurs and the precision is insufficient. In the embodiment of the invention, the first translation signal is a positive level, the second level translation unit carries out forward translation on the ground level to obtain the second translation signal, so that the second translation signal is also a positive level, and the comparison unit is used for comparing the two positive levels, so that the accuracy is higher, the delay is smaller, and the comparison result between the to-be-detected level and the ground level with smaller delay and higher accuracy can be further obtained.
The embodiment of the invention also provides a synchronous rectification buck-type DC-DC converter, which comprises a zero-crossing detection end (SW end), the zero-crossing detection circuit and the synchronous rectifier tube, wherein the zero-crossing detection signal output by the zero-crossing detection circuit is used for controlling the working state of the synchronous rectifier tube, and the level to be detected is the signal of the zero-crossing detection end.
When the level to be detected is lower than the ground level, the zero-crossing detection signal can control the synchronous rectifier tube to be switched off.
The synchronous rectification buck-type DC-DC converter in the embodiment of the invention utilizes the zero-crossing detection circuit to detect the zero-crossing end, judges whether the inductive current drops below zero or not by detecting the level of the zero-crossing end, and controls the working state of the synchronous rectification tube according to the zero-crossing detection signal output by the zero-crossing detection circuit. The normal output level of the zero-crossing detection end is negative, so that if the level of the zero-crossing detection end is directly judged by using the conventional comparator, the precision is low, the time delay is large, the rectifier tube cannot be turned off in time, and backflow is caused; the zero-crossing detection circuit in the embodiment of the invention can more accurately determine the zero point, and can timely turn off the rectifier tube when the inductive current is reduced to zero, thereby reducing the current back-flow.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A zero-crossing detection circuit, comprising: the device comprises a first level translation unit, a second level translation unit and a comparison unit;
the first level translation unit is suitable for performing forward translation on a level to be detected to obtain a first translation signal, and the first translation signal is a positive level;
the second level shift unit is suitable for carrying out forward shift on the ground level to obtain a second shift signal, and the shift amplitude of the second level shift unit is equal to the shift amplitude of the first level shift unit;
the comparison unit compares the first and second translation signals to obtain a zero-crossing detection signal.
2. A zero-crossing detection circuit as claimed in claim 1, wherein the first level shifting unit comprises: the grid electrode of the first PMOS tube is connected to the level to be detected, the source electrode of the first PMOS tube is connected to a current source, and a source electrode signal of the first PMOS tube is used as the first translation signal.
3. A zero-crossing detection circuit as claimed in claim 2, wherein the second level shifting unit comprises: and the grid electrode of the second PMOS tube is connected to the ground level, the source electrode of the second PMOS tube is connected to the current source, and the source electrode signal of the second PMOS tube is used as the second translation signal.
4. A zero-crossing detection circuit as claimed in claim 1, wherein the comparison unit comprises a comparator, two input terminals of the comparator input the first and second translation signals, respectively, and the zero-crossing detection signal is obtained from an output signal of the comparator.
5. A zero-crossing detection circuit as claimed in claim 1, wherein the comparison unit comprises an amplification circuit and a comparator, the amplification circuit comprising a first amplification sub-circuit and a second amplification sub-circuit;
the first amplification sub-circuit is suitable for amplifying the first translation signal to obtain a first amplification signal;
the second amplification sub-circuit is suitable for amplifying the second translation signal to obtain a second amplified signal, and the amplification amplitude of the second amplification sub-circuit is equal to that of the first amplification sub-circuit;
the two input ends of the comparator are respectively connected with the first amplification signal and the second amplification signal, and the zero-crossing detection signal is obtained according to the output signal of the comparator.
6. A zero-crossing detection circuit as claimed in claim 5, wherein the first amplification sub-circuit comprises: a first NMOS transistor and a third PMOS transistor;
the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected to the drain electrode of the third PMOS tube, and the grid electrode of the first NMOS tube is connected with a bias voltage;
the source electrode of the third PMOS tube is connected to a current source, the grid electrode of the third PMOS tube is connected to the first translation signal, and the drain electrode signal of the third PMOS tube is used as the first amplification signal.
7. A zero-crossing detection circuit as claimed in claim 6, wherein the second amplification sub-circuit comprises: a second NMOS transistor and a fourth PMOS transistor;
the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected to the drain electrode of the fourth PMOS tube, and the grid electrode of the second NMOS tube is connected with a bias voltage;
the source electrode of the fourth PMOS tube is connected to a current source, the grid electrode of the fourth PMOS tube is connected to the second translation signal, and the drain electrode signal of the fourth PMOS tube is used as the second amplification signal.
8. A zero-crossing detection circuit as claimed in claim 4 or 5, wherein the comparator comprises:
a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor;
the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected to the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected to the grid electrode of the fifth NMOS tube;
the source electrode of the fifth NMOS tube is grounded, the drain electrode of the fifth NMOS tube is connected to a current source, and a drain electrode signal of the fifth NMOS tube is used as an output signal of the comparator;
the grid electrode of the fifth PMOS tube is connected to one of the two input ends of the comparator, the source electrode of the fifth PMOS tube is connected to the current source, and the drain electrode of the fifth PMOS tube is connected to the drain electrode of the third NMOS tube;
the grid electrode of the sixth PMOS tube is connected to the other input end of the two input ends of the comparator, the source electrode of the sixth PMOS tube is connected to the current source, and the drain electrode of the sixth PMOS tube is connected to the drain electrode of the fourth NMOS tube.
9. A zero-crossing detection circuit as claimed in claim 4 or 5, further comprising: and the waveform shaping unit is used for carrying out waveform shaping on the output signal of the comparator so as to obtain the zero-crossing detection signal.
10. A zero-crossing detection circuit as claimed in claim 9, wherein the waveform shaping unit comprises an even number of inverters connected in series.
11. A synchronous rectification buck-type DC-DC converter, comprising a zero-crossing detection terminal, the zero-crossing detection circuit according to any one of claims 1 to 10 and a synchronous rectifier, wherein the zero-crossing detection signal output by the zero-crossing detection circuit is used to control the operating state of the synchronous rectifier, and the level to be detected is the signal of the zero-crossing detection terminal.
12. The synchronous rectification buck-type DC-DC converter according to claim 11, wherein the zero-crossing detection signal controls the synchronous rectification transistor to turn off when the level to be detected is less than a ground level.
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