CN113917972B - Voltage stabilizer and chip for floating negative voltage domain - Google Patents
Voltage stabilizer and chip for floating negative voltage domain Download PDFInfo
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- CN113917972B CN113917972B CN202111272842.9A CN202111272842A CN113917972B CN 113917972 B CN113917972 B CN 113917972B CN 202111272842 A CN202111272842 A CN 202111272842A CN 113917972 B CN113917972 B CN 113917972B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The invention discloses a voltage stabilizer and a chip for a floating negative voltage domain, wherein the voltage stabilizer comprises a clamping circuit and a source electrode follower M0. The clamping circuit is connected between a first voltage VDD and a second voltage VSS of the floating voltage domain, and generates a clamping voltage V _ BIAS according to a BIAS current I _ BIAS generated by an external circuit; the source follower M0 is connected to the clamp voltage V _ BIAS, and is configured to output a voltage VCC. According to the voltage stabilizer for the floating negative voltage domain, the voltage stabilizer can work in the floating negative voltage domain by adopting the clamping circuit formed by the first voltage division elements, and the process deviation compensation unit is used for compensating the process deviation of the clamping circuit, so that the source follower can output expected stable voltage, and the risk of chip damage is prevented.
Description
Technical Field
The present invention relates to the field of voltage regulators, and more particularly, to a voltage regulator and a chip for a floating negative voltage domain.
Background
A Regulator (Regulator) is one of the circuit structures commonly used in analog chips. When the variation amplitude of the external power supply VDD of the chip is too large or the voltage is too high, the performance of a circuit inside the chip can be influenced; the standard working voltage of the CMOS device used by the mainstream analog circuit is about 5V, and if the working voltage is too high, the reliability of a chip is influenced and even internal devices are damaged. Therefore, a voltage regulator circuit is often integrated in the chip to provide a relatively stable and safe operating voltage VCC for the internal circuits of the chip.
As shown in fig. 1, one solution in the prior art is to integrate a low dropout regulator LDO inside a chip to convert an external input voltage of the chip into a relatively stable internal voltage. According to the scheme, the operational amplifier is introduced into the circuit, so that the circuit complexity is higher, and meanwhile, due to the introduction of the feedback loop of the operational amplifier, when the voltage inside the circuit is suddenly changed, the response speed of the circuit is limited by the bandwidth of the loop.
Another solution in the prior art is to use a voltage-withstanding NMOS transistor with its gate clamped by a zener diode as a source follower, as shown in fig. 2. One disadvantage of this solution is that the resulting voltage VCC is greatly affected by the process corner variations, and the value of the internal voltage VCC may be too high or too low for different batches of chips. In addition, due to the clamping effect of the zener diode, when the zener diode needs to work in a floating voltage domain of negative voltage, the PSUB potential of the chip is pulled negative, so that huge leakage occurs and the chip is burnt. Therefore, voltage regulators obtained with conventional zener diode-clamped source followers cannot handle negative floating domain applications. Some voltage regulators need to operate in a floating voltage domain, for example, VDD and VSS have a voltage difference of 20V, but VDD =100v, VSS =80v, and neither VDD = 0V. The floating voltage domain may be a negative voltage domain, such as VDD =10v, vss = -10V. Although the voltage domain is floating, the die's PSUB will still be tied to absolute ground (0V). Therefore, conventional regulator structures operating in the floating voltage domain are often unable to handle the negative voltage domain.
Fig. 3 is a schematic diagram of a conventional Zener diode structure (assuming that BV _ Zener =6V thereof). Wherein, anode is connected to VSS in fig. 2, and Cathode is connected to V _ BIAS point in fig. 2, i.e. the gate terminal of the source follower NMOS. The PSUB in FIG. 3 is connected to absolute ground 0V, and the ISO terminal may be connected to either the anti terminal or the Catho terminal according to different usage methods. If VSS is in a negative voltage domain of-10V, then Anode = -10V, and Cathode = -4V, and no matter ISO is connected to the Anode end or the Cathode end, the voltage of NSINK is less than 0V, and forms a forward biased PN junction with the grounded PSUB, and at this time, a huge current flows from PSUB to ISO end, which brings a risk of chip damage. In the structure, the voltage VCC = BV _ Zener-V GS ，V GS For the voltage between the gate and the source of the source follower, since the reverse bias breakdown voltage BV _ Zener of the Zener diode is greatly influenced by the process, the VCC obtained by chips of different production batches may be distributed from 3V to 6V, so that the performance difference of the chips is large.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a voltage regulator and a chip for a floating negative voltage domain, which can work in the floating negative voltage domain and can compensate performance influence caused by process deviation.
To achieve the above object, an embodiment of the present invention provides a voltage regulator for a floating negative voltage domain, which includes a clamping circuit and a source follower M0.
The clamping circuit is connected between a first voltage VDD and a second voltage VSS of a floating voltage domain, comprises a plurality of first voltage division elements which are connected in series and generates a clamping voltage V _ BIAS according to a BIAS current I _ BIAS generated by an external circuit; the source follower M0 is connected to the clamp voltage V _ BIAS, and is configured to output a voltage VCC.
In one or more embodiments of the present invention, the voltage regulator further includes a process deviation compensation unit for adjusting the clamping voltage V _ BIAS to control the voltage VCC.
In one or more embodiments of the present invention, the voltage regulator further includes a process deviation compensation unit for adjusting and controlling the first voltage division element to control the magnitude of the voltage VCC.
In one or more embodiments of the present invention, the process deviation compensating unit includes:
the acquisition circuit is connected between a first voltage VDD and a second voltage VSS of the floating voltage domain, and generates a mirror current I _ BIAS' through a mirror BIAS current I _ BIAS so as to generate a sampling voltage Vsense;
one or more comparators comparing the sampled voltage Vsense with a corresponding reference voltage to generate a corresponding output signal; and
and the control circuit is connected with the output signal and is used for short-circuiting the first voltage division element or restoring the short-circuited first voltage division element.
In one or more embodiments of the present invention, the acquisition circuit includes one or more second voltage dividing elements connected in series, and the second voltage dividing elements and the first voltage dividing elements are the same devices.
In one or more embodiments of the invention, the control circuit includes a digital logic circuit for outputting one or more control signals and one or more control switches controlled to open or close by the control signals.
In one or more embodiments of the present invention, the first voltage dividing element is an NMOS transistor, and a gate and a drain of the NMOS transistor are shorted and are simultaneously connected to a source of another NMOS transistor.
In one or more embodiments of the invention, the voltage VCC = n × V GSO -V GS1O Wherein V is GSO Is the voltage between the gate and the source of the first voltage division element; n is the number of the first voltage dividing elements; v GS1O Is the voltage between the gate and source of the source follower M0.
In one or more embodiments of the present invention, the first voltage dividing element is a resistor.
In one or more embodiments of the invention, the voltage VCC = I _ BIAS' × n × R0-V GS10 Wherein R0 is the resistance value of the resistors, and n is the number of the resistors; v GS1O Is the voltage between the gate and source of the source follower M0.
The invention also provides a chip comprising the voltage stabilizer.
Compared with the prior art, according to the voltage stabilizer for the floating negative voltage domain, the voltage stabilizer can work in the floating negative voltage domain through the clamping circuit formed by the first voltage division elements, process deviation compensation is carried out on the clamping circuit through the process deviation compensation unit, the source electrode follower can output expected stable voltage, and the risk of chip damage is prevented.
Drawings
FIG. 1 is a schematic diagram of a prior art voltage regulator circuit;
FIG. 2 is a schematic diagram of another prior art voltage regulator circuit;
FIG. 3 is a schematic diagram of a conventional Zener diode structure;
FIG. 4 is a circuit schematic of a voltage regulator for a floating negative voltage domain according to an embodiment of the present invention;
fig. 5 is a circuit schematic of a voltage regulator for a floating negative voltage domain according to another embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations such as "comprises" or "comprising", etc., will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Example 1
As shown in fig. 4, a voltage regulator for a floating negative voltage domain includes a clamp circuit 10, a source follower M0, and a process variation compensation unit 20.
The clamp circuit 10 is connected between a first voltage VDD and a second voltage VSS of the floating voltage domain, and generates a clamp voltage V _ BIAS according to a BIAS current I _ BIAS generated by an external circuit. It is to be noted that, in the present embodiment, the second voltage VSS can be a positive potential (> 0V), a ground potential (0V), or a negative potential (less than 0V). When the second voltage VSS is a negative potential (less than 0V), a floating negative voltage domain is formed between the first voltage VDD and the second voltage VSS.
Specifically, the clamp circuit 10 includes a plurality of first voltage dividing elements connected in series. The first voltage dividing element in this embodiment is an NMOS transistor, which is an NMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M7. And the NMOS tubes adopt a full-isolation process, so that the NMOS tubes can work in a floating negative voltage domain and simultaneously keep reverse bias of a PSUB potential and an isolation ring voltage. And the grid electrode and the drain electrode of each NMOS tube are all in short circuit. The grid electrode and drain electrode short-circuit end of the NMOS tube M1 is connected with a first voltage VDD; the source electrode of the NMOS tube M1 is connected with the grid electrode and the drain electrode short-circuit end of the NMOS tube M2; the source electrode of the NMOS tube M2 is connected with the grid electrode and the drain electrode short-circuit end of the NMOS tube M3. The NMOS tube M1, the NMOS tube M2 and the NMOS tube M7 are connected in series in sequence in the connection mode. Finally, the source of the NMOS transistor M7 is connected to the second voltage VSS. In other embodiments, the number of the first voltage dividing elements is not limited thereto, and may be reduced or increased.
In addition, the source follower M0 is connected to the clamping voltage V _ BIAS and the first voltage VDD of the floating voltage domain, for outputting the voltage VCC.
Specifically, in this embodiment, the gate of the source follower M0 is used to connect to the clamping voltage V _ BIAS, and the gate of the source follower M0 is connected to the gate and the drain short-circuited end of the NMOS transistor M1; the source electrode of the source electrode follower M0 is used for outputting voltage VCC; the drain of the source follower M0 is used for connection with the first voltage VDD of the floating voltage domain. A capacitor C is connected between the gate of the source follower M0 and the second voltage VSS of the floating voltage domain.
In this embodiment, the voltage VCC = n × V GSO -V GS1O Wherein V is GSO Is the voltage between the gate and the source of the first voltage dividing element; n is the number of first voltage dividing elements; v GS1O Is the voltage between the gate and source of the source follower M0.
As shown in fig. 4, the process deviation compensation unit 20 is used to adjust the clamping voltage V _ BIAS to control the voltage VCC. In this embodiment, the process deviation compensation unit 20 includes: acquisition circuitry 21, one or more comparators, and control circuitry.
The sampling circuit 21 is connected between the first voltage VDD and the second voltage VSS of the floating voltage domain, and generates a mirror current I _ BIAS' by a mirror BIAS current I _ BIAS to generate a sampling voltage Vsense.
Specifically, the acquisition circuit 21 includes one or more second voltage dividing elements connected in series, and the second voltage dividing element and the first voltage dividing element are the same kind of device. Since the first voltage dividing element in this embodiment is an NMOS transistor, the second voltage dividing element is also an NMOS transistor, and the gate and the drain of each NMOS transistor are shorted, respectively, which are an NMOS transistor M8, an NMOS transistor M9, and an NMOS transistor M10. In this embodiment, the gate and drain short-circuited end of the NMOS transistor M8 is connected to a first voltage VDD; the source electrode of the NMOS tube M8 is connected with the grid electrode and the drain electrode short-circuit end of the NMOS tube M9; the source electrode of the NMOS tube M9 is connected with the grid electrode and the drain electrode short-circuit end of the NMOS tube M10; the source of the NMOS transistor M10 is connected to a second voltage VSS. In other embodiments, the number of the second voltage dividing elements is not limited thereto, and may be decreased or increased.
The comparator compares the sampled voltage Vsense with a corresponding reference voltage to generate a corresponding output signal. The number of comparators can be selected as needed, one or more of which may be used. In this embodiment, two comparators COMP1 and COMP2 are adopted, one input ends of the two comparators COMP1 and COMP2 are both connected to the gate and drain short-circuited end of the NMOS transistor M8 to obtain a sampling voltage Vsense, and the other input ends are respectively and correspondingly connected to the reference voltages VREF1 and VREF2.
The control circuit is connected to the output signal for short-circuiting the first voltage-dividing element or restoring the short-circuited first voltage-dividing element.
Specifically, the control circuit includes a digital Logic circuit Logic for outputting one or more control signals and one or more control switches controlled to be closed by the corresponding control signals. The number of control switches corresponds to the number of comparators. Each control switch is correspondingly connected with one of the first voltage division elements.
In this embodiment, two control switches SW1 and SW2 are adopted, two ends of the control switch SW1 are connected to the drain and the source of the NMOS transistor M3, and two ends of the control switch SW2 are connected to the drain and the source of the NMOS transistor M4. The two comparators COMP1 and COMP2 obtain the sampling voltage Vsense and then compare the sampled voltage Vsense with the set reference voltages VREF1 and VREF2 to output two output signals. The digital Logic circuit Logic is connected to output terminals of the two comparators COMP1, COMP2 to receive two output signals. The digital Logic circuit Logic receives and processes the two output signals and outputs two control signals signal1 and signal2, thereby correspondingly controlling the opening or closing of the two control switches SW1 and SW 2.
In the present embodiment, the first voltage dividing element will have a voltage V when affected by the process variation GSO The variation is large. The mirror current I _ BIAS' flows through the acquisition circuit 21, and the sampled voltage Vsense is obtained. The process deviation of the batch of chips can be represented by the high and low of the sampling voltage Vsense.
When the control switch SW1 or the control switch SW2 is closed, n in the expression of the voltage VCC is reduced by one; on the contrary, when the circuit is switched off, n in the expression of the voltage VCC is increased by one. When the control switch SW1 and the control switch SW2 are both closed, n in the expression of the voltage VCC is decreased by two, and when the control switch SW is opened, n in the expression of the voltage VCC is increased by two. In this way, when the clamp voltage V _ BIAS is higher due to process variation, the comparison result between the sampling voltage Vsense and the reference voltages VREF1 and VREF2 turns on the control switch SW1 or the control switch SW2, thereby reducing the voltage VCC; conversely, when off, the voltage VCC is increased. Thereby realizing the compensation of the process deviation.
The more comparators that are used, the higher the process variation accuracy of the sampling. For example, using two comparators, three results of low, medium and high can be obtained, and the two corresponding control switches have three combinations of (OFF ), (OFF, ON) and (ON, ON); if more comparators are used, more digital logic combinations are obtained. Therefore, in other embodiments, the number of the comparators and the corresponding control switches is not limited to the number mentioned in this embodiment, and can be increased or decreased accordingly; the number of first voltage dividing elements controlled by a single control switch is also not limited to one.
Example 2
As shown in fig. 5, the present embodiment is different from embodiment 1 in that the first voltage dividing element is selected from resistors R4, R5, and R6 to R10. The second voltage divider is the same type of device as the first voltage divider, and therefore is also a resistor, and is resistors R1, R2, and R3, respectively. It should be noted that, in other embodiments, the number of the first voltage dividing element and the second voltage dividing element is not limited, and may be reduced or increased.
In this embodiment, the voltage VCC = I _ BIAS' × n × R 0 -V GS10 Wherein, the resistances of the resistors R4, R5 and R6-R10 are the same and are all R 0 N is the number of resistors; v GS1O Is the voltage between the gate and source of the source follower M0. The resistance value of the first voltage dividing element is also susceptible to process variations, so that the process variations are compensated for using the principle in embodiment 1.
Example 3
The present embodiment also provides a chip including the voltage regulator in embodiment 1 or embodiment 2.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (8)
1. A voltage regulator for a floating negative voltage domain, comprising:
the clamp circuit is connected between a first voltage VDD and a second voltage VSS of a floating voltage domain, comprises a plurality of first voltage division elements which are connected in series and generates a clamp voltage V _ BIAS according to a BIAS current I _ BIAS generated by an external circuit; and
the source electrode follower M0 is connected with the clamping voltage V _ BIAS and the first voltage VDD of the floating voltage domain and used for outputting a voltage VCC;
the voltage stabilizer further comprises a process deviation compensation unit for adjusting the clamping voltage V _ BIAS to control the voltage VCC;
the process deviation compensation unit includes:
the acquisition circuit is connected between a first voltage VDD and a second voltage VSS of the floating voltage domain, and generates a mirror current I _ BIAS' through a mirror BIAS current I _ BIAS so as to generate a sampling voltage Vsense;
one or more comparators comparing the sampled voltage Vsense with a corresponding reference voltage to generate a corresponding output signal; and
and the control circuit is connected with the output signal and is used for short-circuiting the first voltage division element or restoring the short-circuited first voltage division element.
2. The voltage regulator of claim 1, wherein the acquisition circuit comprises one or more second voltage-dividing elements connected in series, the second voltage-dividing element being the same device as the first voltage-dividing element.
3. The voltage regulator of claim 2, wherein the control circuit comprises digital logic circuitry to output one or more control signals and one or more control switches controlled by the control signals to open or close.
4. The voltage regulator of claim 1, wherein the first voltage divider component is an NMOS transistor having its gate and drain shorted together and simultaneously connected to the source of another of the NMOS transistors.
5. The voltage regulator of claim 4, wherein the voltage VCC = n x V GSO -V GS1O Wherein V is GSO Is the voltage between the gate and the source of the first voltage division element; n is the number of the first voltage dividing elements; v GS1O Is the voltage between the gate and source of the source follower M0.
6. The voltage regulator of claim 1, wherein the first voltage dividing element is a resistor.
7. The voltage regulator of claim 6, wherein the voltage VCC = I _ BIAS'. N.R 0-V GS10 Wherein R0 is the resistance of the resistors, n is the number of the resistors, and V GS1O Is the voltage between the gate and source of the source follower M0.
8. A chip comprising the voltage regulator according to any one of claims 1 to 7.
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