CN117214514A

CN117214514A - Zero-crossing detection circuit

Info

Publication number: CN117214514A
Application number: CN202311084454.7A
Authority: CN
Inventors: 陈成; 魏荣臣
Original assignee: Zhuhai Jieli Technology Co Ltd
Current assignee: Zhuhai Jieli Technology Co Ltd
Priority date: 2023-08-25
Filing date: 2023-08-25
Publication date: 2023-12-12

Abstract

The application relates to a zero-crossing detection circuit, which comprises an offset voltage adjustable comparator, wherein two input ends are respectively connected with a zero-crossing detection point and a ground end and are used for outputting a zero-crossing detection signal which indicates whether the voltage of the zero-crossing detection point is zero or not; the two input ends of the dynamic latch comparator are respectively connected with a zero-crossing detection point and a ground end, and the clock trigger end is connected with the output end of the offset voltage adjustable comparator and is used for outputting an adjusting signal under the triggering of a zero-crossing detection signal; the control module is provided with two input ends which are respectively and correspondingly connected with the two output ends of the dynamic latching comparator, and a first output end which is connected with the first input end of the offset voltage adjustable comparator and is used for outputting a first voltage adjusting code value from the first output end according to an adjusting signal; the offset voltage adjustable comparator is also used for adjusting the zero crossing detection signal according to the first voltage adjusting code value. By adopting the circuit, the voltage of the zero-crossing detection point can be accurately detected, and the grounded switching tube in the buck conversion circuit can be timely closed.

Description

Zero-crossing detection circuit

Technical Field

The application relates to the technical field of circuits, in particular to a zero-crossing detection circuit.

Background

With the development of the technical field of electronic information, the use of BUCK circuits (BUCK conversion circuits) is becoming more and more widespread. Conventional BUCK circuits typically include two switching tubes, an inductor, and an off-chip voltage regulator capacitor in series, and when the BUCK circuit needs to operate in DCM (discontinuous conduction mode, discontinuous conduction) mode, the grounded switching tube needs to be turned off when the inductor current drops to 0 (i.e., zero voltage at the zero crossing point).

However, the detection of the zero crossing detection point is inaccurate at present, and the problem that a grounded switching tube in a BUCK circuit is too late or too early to close exists.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a zero-crossing detection circuit capable of accurately detecting a zero-crossing detection point voltage and timely closing a grounded switching tube in a buck conversion circuit.

In a first aspect, the present application provides a zero-crossing detection circuit comprising:

the first input end of the offset voltage adjustable comparator is used for being connected with a zero crossing detection point, and the second input end of the offset voltage adjustable comparator is used for being grounded; the offset voltage adjustable comparator is used for outputting a zero-crossing detection signal, and the zero-crossing detection signal is used for representing whether the voltage of the zero-crossing detection point is zero or not;

The first input end of the dynamic latch comparator is used for being connected with a zero crossing detection point, the second input end of the dynamic latch comparator is used for being grounded, and the clock trigger end of the dynamic latch comparator is connected with the output end of the offset voltage adjustable comparator; the dynamic latch comparator is used for outputting an adjusting signal under the triggering of the zero-crossing detection signal;

the first input end of the control module is connected with the first output end of the dynamic latching comparator, the second input end of the control module is connected with the second output end of the dynamic latching comparator, and the first output end of the control module is connected with the first input end of the offset voltage adjustable comparator; the control module is used for outputting a first voltage regulation code value from a first output end according to the regulation signal;

the offset voltage adjustable comparator is also used for adjusting the zero crossing detection signal according to the first voltage adjusting code value.

In one embodiment, the second output of the control module is connected to the first input of the dynamic latching comparator, and the circuit further comprises:

the first end of the first switch is connected with the zero-crossing detection point, and the second end of the first switch is connected with the second input end of the dynamic latch comparator;

The first end of the second switch is connected with the clock trigger end of the dynamic latch comparator, the second end of the second switch is connected with the output end of the offset voltage adjustable comparator, and the third end of the second switch is connected with the third output end of the control module;

when the first switch is disconnected and the first end and the second end of the second switch are connected, the control module is used for outputting a first voltage regulation code value from the first output end according to the regulation signal;

when the first switch is closed and the first end and the third end of the second switch are conducted, the control module is used for outputting a second voltage regulation code value from the second output end according to the regulation signal.

In one embodiment, the offset voltage adjustable comparator comprises:

the input end of the current mirror module is used for accessing a current source, and the power supply end of the current mirror module is used for connecting a power supply voltage;

the first input end of the first comparison module is connected with the first output end of the current mirror module, the second input end of the first comparison module is connected with the second output end of the current mirror module, and the output end of the first comparison module is connected with the clock end of the dynamic latch comparator;

the control end of the input control module is used for accessing control signals, the first output end of the input control module is connected with the third input end of the first comparison module, and the second output end of the input control module is connected with the fourth input end of the first comparison module;

The first input end of the first adjusting module is used for being connected with a zero crossing detection point, the second input end of the first adjusting module is used for being grounded, the first output end of the first adjusting module is connected with the first input end of the input control module, and the second output end of the first adjusting module is connected with the second input end of the input control module; the first adjusting module is used for changing the resistance value of the first adjusting module according to the first voltage adjusting code value so as to adjust the zero-crossing detection signal.

In one embodiment, the first adjustment module comprises:

the input end of the adjustable resistor is connected with the first input end of the input control module; the adjustable resistor is used for changing the resistance value of the adjustable resistor according to the first voltage adjusting code value so as to adjust the zero-crossing detection signal;

the input end of the fixed value resistor is used for grounding, and the output end of the fixed value resistor is connected with the second input end of the input control module.

In one embodiment, the offset voltage adjustable comparator further comprises:

the input end of the noise reduction module is connected with the output end of the first comparison module, and the output end of the noise reduction module is connected with the clock end of the dynamic latch comparator.

In one embodiment, the offset voltage adjustable comparator further comprises:

the input end of the amplifying module is connected with the output end of the noise reduction module, and the output end of the amplifying module is connected with the clock end of the dynamic latch comparator.

In one embodiment, the amplifying module comprises at least two cascaded inverters.

In one embodiment, a dynamic latching comparator includes:

the power supply end of the first reset module is used for being connected with a power supply voltage, and the control end of the first reset module is used for being connected with a zero-crossing detection signal;

the power supply end of the latch module is used for being connected with power supply voltage, the reset end of the latch module is connected with the output end of the first reset module, the first output end of the latch module is connected with the first input end of the control module, and the second output end of the latch module is connected with the second input end of the control module;

the first output end of the second adjusting module is connected with the first input end of the latch module, and the second output end of the second adjusting module is connected with the second input end of the latch module; the second adjusting module is used for outputting an adjusting signal under the triggering of the zero-crossing detection signal;

The first output end of the second comparison module is connected with the first input end of the latch module, the second output end of the second comparison module is connected with the second input end of the latch module, and the control end of the second comparison module is used for accessing bias voltage;

the first output end of the second reset module is connected with the first input end of the second comparison module, the second output end of the second reset module is connected with the second input end of the second comparison module, the second input end of the second reset module is used for being connected with a zero-crossing detection point, the first input end of the second reset module is used for being grounded, and the control end of the second reset module is used for being connected with a zero-crossing detection signal.

In one embodiment, the second adjustment module comprises:

the output end of the first adjustable capacitor is connected with the first input end of the latch module;

and the output end of the second adjustable capacitor is connected with the second input end of the latch module.

In one embodiment, the dynamic latching comparator further comprises:

the first input end of the input limiting module is used for being grounded, the second input end of the input limiting module is used for being connected with a zero-crossing detection point, the first output end of the input limiting module is connected with the first input end of the second resetting module, and the second output end of the input limiting module is connected with the second input end of the second resetting module.

In one embodiment, the latch module includes:

the power supply end of the first inverter is used for being connected with a power supply voltage, the first input end of the first inverter is connected with the first output end of the second comparison module, and the first output end of the first inverter is connected with the first input end of the control module;

the power supply end of the second inverter is used for being connected with a power supply voltage, the first input end of the second inverter is connected with the second output end of the second comparison module, the second input end of the second inverter is connected with the second output end of the first inverter, the first output end of the second inverter is connected with the second input end of the control module, and the second output end of the second inverter is connected with the second input end of the first inverter.

In a second aspect, the present application provides a drive control circuit of a voltage conversion circuit, comprising:

the zero-crossing detection circuit as in the above embodiment;

the first input end of the driving module is used for being connected with a pulse width modulation signal, and the second input end of the driving module is connected with the output end of the offset voltage adjustable comparator; the driving module is used for generating a driving signal according to the pulse width modulation signal and the zero crossing detection signal; the driving signal is used for controlling the on-off state of a switching tube in the voltage conversion circuit.

In one embodiment, the voltage conversion circuit comprises a first switching tube and a second switching tube which are connected in series, an inductor connected with the connection midpoint of the first switching tube and the second switching tube, and a capacitor, wherein one end of the inductor, which is not connected with the first switching tube, is grounded through the capacitor; the driving module includes:

the first output end of the first driving module is connected with the control end of the first switching tube, the first driving module is used for generating a first driving signal and a second driving signal according to the pulse width modulation signal, and the first driving signal is used for controlling the on-off of the first switching tube;

the first input end of the second driving module is connected with the second output end of the first driving module, the second input end of the second driving module is connected with the output end of the offset voltage adjustable comparator, the output end of the second driving module is connected with the control end of the second switching tube, the second driving module is used for generating a third driving signal according to the second driving signal and the zero crossing detection signal, and the third driving signal is used for controlling the on-off of the second switching tube.

In a third aspect, the present application provides a power conversion circuit comprising:

The driving control circuit in the above embodiment is used for generating a driving signal, and the driving signal is used for controlling the on-off state of the switching tube in the voltage conversion circuit;

and the voltage conversion circuit is used for receiving the driving signal.

In a fourth aspect, an electronic device is provided comprising a power conversion circuit as in the above embodiments.

The zero-crossing detection circuit has at least the following beneficial effects:

the zero-crossing detection circuit comprises an offset voltage adjustable comparator, a dynamic latch comparator and a control module. Simultaneously, two input ends of the offset voltage adjustable comparator and the dynamic latch comparator are respectively connected with a zero crossing detection point and a ground end so as to acquire a voltage signal of the zero crossing detection point and a zero voltage signal of a ground point. The offset voltage adjustable comparator compares the voltage signal of the zero crossing detection point with the zero voltage signal of the grounding point and outputs a zero crossing detection signal representing whether the voltage of the zero crossing detection point is zero or not based on a comparison result. The clock trigger end of the dynamic latch comparator is connected with the output end of the offset voltage adjustable comparator to acquire a zero-crossing detection signal and use the zero-crossing detection signal as a clock signal, the voltage signal of the zero-crossing detection point and the zero-crossing voltage signal of the grounding point are continuously compared under the control of the zero-crossing detection signal, and the adjusting signal output by the dynamic latch comparator is updated in each clock period. After receiving the adjusting signal, the control module outputs a first voltage adjusting code value to the offset voltage adjustable comparator according to the adjusting signal, so that the offset voltage adjustable comparator adjusts the output zero-crossing detection signal according to the first voltage adjusting code value, the zero-crossing detection signal can more accurately represent whether the voltage of the zero-crossing detection point is zero, and the grounded switching tube in the BUCK circuit is turned off timely based on the adjusted zero-crossing detection signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a BUCK circuit in an embodiment;

FIG. 2 is a schematic diagram of a zero crossing detection circuit in one embodiment;

FIG. 3 is a timing and effect diagram of the zero crossing detection circuit when the second switching transistor MN is turned off too late in one embodiment;

FIG. 4 is a timing and effect diagram of the operation of the zero crossing detection circuit when the second switching transistor MN is turned off too early in one embodiment;

FIG. 5 is a schematic diagram of a zero crossing detection circuit in another embodiment;

FIG. 6 is a circuit diagram of an offset voltage adjustable comparator in one embodiment;

FIG. 7 is a circuit diagram of a dynamic latching comparator in one embodiment;

FIG. 8 is a schematic diagram of a driving control circuit of the voltage converting circuit according to an embodiment;

fig. 9 is a schematic diagram of a driving control circuit of a voltage conversion circuit according to another embodiment.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

As described in the background art, in the field of electronic information, a BUCK circuit is an indispensable circuit as a power supply power conversion module. As shown in fig. 1, the BUCK circuit generally includes a first switching tube MP, a second switching tube MN, an inductance L, and an off-chip voltage stabilizing capacitor COUT. At low load currents, the BUCK circuit operates in DCM (discontinuous conduction mode, discontinuous conduction) mode. A BUCK circuit operating in DCM mode requires that the second switching transistor MN is turned off when the inductor current IL drops to 0 (i.e. the voltage of the switching node LX is zero). If the second switching tube MN is turned off too late (i.e. the second switching tube MN is turned off when the inductance current IL is smaller than 0), the reverse inductance current is output to the capacitor COUT to discharge, and the on-resistance of the second switching tube MN has a voltage drop, and the voltage of the switching node LX is positive. If the second switching tube MN is turned off too early (i.e. the second switching tube MN is turned off when the inductor current IL is greater than 0), the substrate parasitic diode of the second switching tube MN will freewheel the inductor L, and the voltage of the switching node LX is negative. If the second switching tube MN is turned off when the inductor current IL is exactly equal to 0, there is no energy loss due to the reverse current and the body diode conduction. Therefore, a zero-crossing detection circuit is required to detect whether the inductor current crosses zero (i.e., to detect whether the zero-crossing point—the voltage of the switching node LX is zero), and to realize the turn-off control of the second switching transistor MN based on the detection result. However, most of the current zero-crossing detection circuits are zero-crossing comparators, which are affected by manufacturing deviation, and the offset voltage of the zero-crossing comparator is not 0, so that the existence of the offset voltage can lead to inaccurate detection results of the zero-crossing detection point, and still lead to early or late closing of the second switching tube MN, thereby causing additional energy loss.

For the above reasons, as shown in fig. 2, the present application provides a zero-crossing detection circuit 2 including: offset voltage adjustable comparator 22, dynamic latch comparator 24, and control module 26. The first input end of the offset voltage adjustable comparator 22 is used for connecting with a zero crossing detection point, and the second input end of the offset voltage adjustable comparator 22 is used for grounding; the offset voltage adjustable comparator 22 is configured to output a zero-crossing detection signal, where the zero-crossing detection signal is used to characterize whether the voltage at the zero-crossing detection point is zero; a first input end of the dynamic latch comparator 24 is used for connecting a zero crossing detection point, a second input end of the dynamic latch comparator 24 is used for grounding, and a clock trigger end of the dynamic latch comparator 24 is connected with an output end of the offset voltage adjustable comparator 22; the dynamic latch comparator 24 is used for outputting an adjusting signal under the triggering of the zero-crossing detection signal; a first input end of the control module 26 is connected with a first output end of the dynamic latch comparator 24, a second input end of the control module 26 is connected with a second output end of the dynamic latch comparator 24, and a first output end of the control module 26 is connected with a first input end of the offset voltage adjustable comparator 22; the control module 26 is configured to output a first voltage adjustment code value from the first output terminal according to the adjustment signal; the offset voltage adjustable comparator 22 is further configured to adjust the zero crossing detection signal according to the first voltage adjustment code value.

The offset voltage adjustable comparator 22 may be one of comparators, and may change a comparison threshold value by adjusting an offset voltage, for example, may refer to a zero-crossing comparator. The zero-crossing detection point may refer to a signal source or a detection point in a circuit to be tested, for example, may refer to an inductor current detection point in a BUCK circuit (i.e., a switching node LX in the BUCK circuit). A second input of offset voltage adjustable comparator 22 is connected to ground, indicating that its reference level is ground. Based on this, offset voltage adjustable comparator 22 may compare the difference between the voltage at the zero crossing point and ground. The zero-crossing detection signal is used for representing whether the voltage of the zero-crossing detection point is zero, for example, when the difference between the voltage of the zero-crossing detection point and the ground is zero, the output of the comparator becomes high level, and the zero-crossing detection signal is 1; when the difference is not zero, the output is low, and the zero-crossing detection signal is 0. The dynamic latch comparator 24 may be one of the comparators and has a latch function. The dynamic latching comparator 24 has a first input connected to the zero crossing detection point and a second input grounded indicating that its reference level is ground. The clock trigger end of the dynamic latch comparator 24 is connected to the output end of the offset voltage adjustable comparator 22, and when the zero crossing detection signal output by the offset voltage adjustable comparator 22 changes, the latch operation of the dynamic latch comparator 24 is triggered. The adjustment signal may refer to a voltage signal or a digital signal for adjusting an output parameter of the control module 26, such as a first voltage adjustment code value output by the control module 26, where the first voltage adjustment code value may be an digital code or an analog voltage, and may be, for example, an offset voltage adjustment code value a for adjusting an offset voltage of the offset voltage adjustable comparator 22.

Specifically, in order to describe the detection process of the above zero-crossing detection circuit 2 more clearly, description will be given by taking as an example the application to the BUCK circuit as shown in fig. 1. As shown in fig. 2, the first input terminal ("+" input terminal) of the offset voltage adjustable comparator 22 is connected to a zero detection point (switching node LX of the BUCK circuit), the second input terminal ("-" input terminal) is connected to the power ground PGND, the output terminal VZCD is connected to the clock terminal CLK of the dynamic latch comparator 24, i.e., the clock signal of the dynamic latch comparator 24 is derived from the zero detection signal outputted from the offset voltage adjustable comparator 22, the first input terminal ("+" input terminal) of the dynamic latch comparator 24 is connected to the zero detection point (joint point LX) and is opened, the second input terminal ("-" input terminal) is connected to the power ground PGND, and the first output terminal ("+" output terminal VOUTP) and the second output terminal (- "output terminal VOUTN) are connected to the input terminal of the control module 26 for outputting the adjustment signal to the control module 26. Upon receiving the adjustment signal, the control module 26 outputs a first voltage adjustment code value (offset voltage adjustment code value a) to the offset voltage adjustable comparator 22, and the offset voltage adjustable comparator 22 adjusts its offset voltage according to the offset voltage adjustment code value a to adjust the output zero crossing detection signal (output signal VZCD).

For example, when the BUCK circuit is operating in DCM, if the second switching transistor MN is turned off too late, i.e. the inductor current IL is smaller than 0, the output signal VZCD of the offset voltage adjustable comparator 22 changes from high level to low level, and the voltage of the switching node LX is positive. The dynamic latch comparator 24 is triggered by a falling edge, and the output VOUTP has a rising edge. The control module 26 detects that the VOUTP has a rising edge, and will increase the offset voltage adjustment code value a, so that the offset voltage of the offset voltage adjustable comparator 22 is reduced, thereby adjusting the output signal VZCD of the output end, so that the output signal VZCD more accurately reflects the real state of whether the voltage of the switching node LX in the BUCK circuit is zero, so that the driving control module 4 can adjust the closing timing of the second switching tube according to the adjusted detection result, that is, close the second switching tube MN in advance for a certain time in the next period based on the zero crossing detection signal. The timing diagrams of the signals and the effects finally achieved are shown in fig. 3, and the implementation process and effects can be known from the diagrams by those skilled in the art, and are not described herein. Further, if the second switching transistor MN is turned off too early, that is, the inductor current IL is greater than 0, the output signal VZCD of the offset voltage adjustable comparator 22 changes from high level to low level, and the voltage of the switching node LX is negative. The dynamic latch comparator 24 is triggered by a falling edge, and the output VOUTN has a rising edge. The control module 26 detects that the output terminal VOUTN has a rising edge, and will reduce the offset voltage adjustment code value a, so that the offset voltage of the offset voltage adjustable comparator 22 is increased, thereby adjusting the output signal VZCD of the output terminal, so as to more accurately reflect the real state of whether the voltage of the switch node LX in the BUCK circuit is zero, so that the driving control module 4 can adjust the closing timing of the second switching tube according to the adjusted detection result, that is, delay for a certain time to close the second switching tube MN in the next period based on the zero-crossing detection signal. The timing diagrams of the signals and the effects finally achieved are shown in fig. 4, and those skilled in the art can know the implementation process and effects from the diagrams, and are not described herein.

The zero crossing detection circuit 2 includes an offset voltage adjustable comparator 22, a dynamic latch comparator 24, and a control module 26. Simultaneously, two input ends of the offset voltage adjustable comparator 22 and the dynamic latch comparator 24 are respectively connected with a zero crossing detection point and a ground end to acquire a voltage signal of the zero crossing detection point and a zero voltage signal of a ground point. The offset voltage adjustable comparator 22 compares the voltage signal at the zero-crossing point with the zero-crossing voltage signal at the ground point, and outputs a zero-crossing detection signal indicating whether the voltage at the zero-crossing point is zero or not based on the comparison result. The clock trigger end of the dynamic latch comparator 24 is connected with the output end of the offset voltage adjustable comparator 22 to obtain a zero-crossing detection signal and use the zero-crossing detection signal as a clock signal, continuously compares the voltage signal of the zero-crossing detection point with the zero-crossing voltage signal of the grounding point under the control of the zero-crossing detection signal, and updates the adjustment signal output by the dynamic latch comparator 24 in each clock period. After receiving the adjustment signal, the control module 26 outputs a first voltage adjustment code value to the offset voltage adjustable comparator 22 according to the adjustment signal, so that the offset voltage adjustable comparator 22 adjusts the output zero-crossing detection signal according to the adjustment signal, and the zero-crossing detection signal can more accurately represent whether the voltage of the zero-crossing detection point is zero, and further the drive control module 4 can more timely close the grounded switching tube in the buck conversion circuit based on the adjusted zero-crossing detection signal.

In one embodiment, as shown in fig. 5, the second output terminal of the control module 26 is connected to the first input terminal of the dynamic latch comparator 24, and the zero-crossing detection circuit 2 further includes a first switch S1 and a second switch S2. A first end of the first switch S1 is connected with a zero crossing detection point, and a second end of the first switch S1 is connected with a second input end of the dynamic latch comparator 24; a first end of the second switch S2 is connected to the clock trigger end of the dynamic latch comparator 24, a second end of the second switch S2 is connected to the output end of the offset voltage adjustable comparator 22, and a third end of the second switch S2 is connected to the third output end of the control module 26; when the first switch S1 is turned off and the first end and the second end of the second switch S2 are turned on, the control module 26 is configured to output a first voltage adjustment code value from the first output end according to the adjustment signal; when the first switch S1 is closed and the first end and the third end of the second switch S2 are turned on, the control module 26 is configured to output a second voltage adjustment code value from the second output end according to the adjustment signal.

Wherein, the first end of the first switch S1 is connected to the zero crossing detection point, the second end of the first switch S1 is connected to the second input end of the dynamic latch comparator 24, and whether the voltage signal of the zero crossing detection point is input to the dynamic latch comparator 24 can be controlled by the first switch S1. For example, when the first switch S1 is turned off, the voltage signal at the zero crossing point is input to the dynamic latch comparator 24; when the first switch S1 is closed, the voltage signal of the zero crossing point is not input to the dynamic latch comparator 24. The first terminal of the second switch S2 is connected to the clock trigger terminal of the dynamic latch comparator 24, the second terminal is connected to the output terminal of the offset voltage adjustable comparator 22, and the third terminal is connected to the third output terminal of the control module 26, and different input signals can be selected as clock signals of the clock trigger terminal based on the second switch S2. For example, as shown in fig. 5, taking the example that the zero crossing detection circuit 2 is applied to the BUCK circuit shown in fig. 1 as an illustration, the clock terminal CLK of the dynamic latch comparator 24 is connected to the first terminal of the second switch S2, the output terminal VZCD of the offset voltage adjustable comparator 22 is connected to the second terminal of the second switch S2, and the third output terminal of the control module 26 is connected to the third terminal of the second switch S2, that is, the clock signal of the dynamic latch comparator 24 is from the output of the offset voltage adjustable comparator 22 or the control module 26. The two ends of the first switch S1 are respectively connected to the switching node LX and the power ground PGND. Offset voltage adjustment code value a and offset voltage adjustment code value B output by control module 26 are provided to offset voltage adjustable comparator 22 and dynamic latch comparator 24, respectively.

Specifically, as shown in fig. 5, before the BUCK circuit operates, the first switch S1 is closed, the switching node LX is shorted to the power ground PGND, and then the dynamic latch comparator 24 is enabled, and the first terminal of the second switch S2 is turned on to the third terminal, so that the clock terminal CLK is connected to the control module 26. The control module 26 outputs a clock signal to the dynamic latch comparator 24 to cause the dynamic latch comparator 24 to perform a latch operation, and outputs adjustment signals to the control module 26 from output terminals (VOUTP and VOUTN) of the dynamic latch comparator 24. After receiving the adjustment signal, the control module 26 adjusts the output offset voltage adjustment code value B, and the dynamic latch comparator 24 adjusts the offset voltage of itself after receiving the offset voltage adjustment code value B, thereby further adjusting the output VOUTP and VOUTN signals. For example, the offset voltage adjusting code value B may be gradually increased from the minimum value to a certain code value X according to the adjusting signal, after the dynamic latch comparator 24 receives the offset voltage adjusting code value B, the offset voltage of itself is adjusted, so as to adjust the output VOUTP and VOUTN signals, when the VOUTP or VOUTN state output by the dynamic latch comparator 24 changes, trimming of the offset voltage of the dynamic latch comparator 24 is completed, so that the offset voltage of the trimmed dynamic latch comparator 24 is almost 0, and based on the trimmed dynamic latch comparator 24 in combination with the zero-crossing detection mode in the above embodiment, zero-crossing detection of the zero-crossing detection point may be completed.

In the above embodiment, the offset voltage of the trimmed dynamic latch comparator 24 is almost 0, so that the influence of the offset voltage can be minimized, thereby improving the precision and accuracy of the comparator. By reducing offset voltage, the performance of the comparator is improved, and the stability and reliability of the comparator in the working process are ensured.

In one embodiment, as shown in fig. 6, offset voltage adjustable comparator 22 includes a current mirror module 222, a first comparison module 224, an input control module 226, and a first adjustment module 228. The input end of the current mirror module 222 is used for accessing a current source, and the power supply end of the current mirror module 222 is used for connecting a power supply voltage; a first input terminal of the first comparison module 224 is connected to a first output terminal of the current mirror module 222, a second input terminal of the first comparison module 224 is connected to a second output terminal of the current mirror module 222, and an output terminal of the first comparison module 224 is connected to a clock terminal of the dynamic latch comparator 24; the control end of the input control module 226 is used for accessing a control signal, the first output end of the input control module 226 is connected with the third input end of the first comparison module 224, and the second output end of the input control module 226 is connected with the fourth input end of the first comparison module 224; a first input end of the first adjusting module 228 is used for connecting a zero crossing detection point, a second input end of the first adjusting module 228 is used for grounding, a first output end of the first adjusting module 228 is connected with a first input end of the input control module 226, and a second output end of the first adjusting module 228 is connected with a second input end of the input control module 226; the first adjusting module 228 is configured to change the resistance of the first adjusting module 228 according to the first voltage adjusting code value to adjust the zero-crossing detection signal.

The current mirror module 222 may be a circuit module for providing a stable bias current to the offset voltage adjustable comparator 22 to ensure that the offset voltage adjustable comparator 22 operates normally. When the current mirror module 222 receives a constant reference current (e.g., the current of the current source), it copies the reference current to the output terminal through its own operating characteristics so that other parts of the comparator (e.g., the input pair of tubes) requiring the bias current can obtain the same and stable bias current through the output terminal connected to the current mirror module 222. The first comparison module 224 may refer to an input pair of tubes in the offset voltage adjustable comparator 22 for amplifying and comparing an input signal. The input control module 226 may be a circuit module for controlling the signal to be compared to be input to the first comparing module 224 according to the control signal, and the first adjusting module 228 is a circuit module for adjusting the property of the zero-crossing detection signal according to the resistance value according to the first voltage adjusting code value.

Specifically, when the input control module 226 receives the control signal, the input control module 226 is in a conductive state, the voltage signal and the ground signal of the zero crossing detection point are input through the first adjusting module 228 and the input control module 226 is input to the first comparing module 224, the first comparing module 224 obtains the bias current from the output end of the current mirror module 222, and based on the bias current and the conductive characteristic of the first comparing module 224, the comparison of the voltage signal and the ground signal of the zero crossing detection point is achieved, so as to output the comparison result, that is, the zero crossing detection signal is output. For example, when the voltage at the zero crossing point is greater than the voltage at the ground terminal, the first comparison module 224 outputs a high level.

In the above embodiment, the offset voltage adjustable comparator 22 provides a stable current source through the current mirror module 222, performs the comparison of the input signals through the first comparison module 224, and adjusts the zero crossing detection signal according to the first voltage adjustment code value through the first adjustment module 228. This allows the offset voltage of the offset voltage adjustable comparator 22 to be adjusted and controlled to improve the performance and accuracy of the comparator.

In one embodiment, as shown in FIG. 6, the first adjustment module 228 includes an adjustable resistor and a fixed resistor. The input end of the adjustable resistor is connected with a zero crossing detection point, and the output end of the adjustable resistor is connected with the first input end of the input control module 226; the adjustable resistor is used for changing the resistance value of the adjustable resistor according to the first voltage adjusting code value so as to adjust the zero-crossing detection signal; the input of the fixed resistor is connected to ground, and the output of the fixed resistor is connected to the second input of the input control module 226.

The adjustable resistor is used for changing the resistance value according to the first voltage adjusting code value so as to adjust the property of the zero-crossing detection signal. The amplitude or phase of the zero-crossing detection signal can be adjusted by changing the resistance value of the adjustable resistor, so that the offset voltage is adjusted. The fixed resistor provides a fixed resistance for participating in the regulation process of the input control module 226. The fixed value resistor can be used together for adjusting the zero crossing detection signal by combining with the adjustable resistor.

Specifically, when the adjustable resistor receives the first voltage adjustment code value, the resistance value of the adjustable resistor is changed, so that the voltage or current in the offset voltage adjustable comparator 22 is changed, and the zero-crossing detection signal is changed.

In the above embodiment, the offset voltage of the offset voltage adjustable comparator 22 is adjusted based on the adjustable resistor and the first voltage adjustment code value, so as to ensure the accuracy of the output zero-crossing detection signal.

In a specific embodiment, as shown in fig. 6, the current mirror module 222 is composed of three PMOS transistors (MP 1, MP2 and MP 3), and specific connection relationships and implementation manners can be known by those skilled in the art directly from the drawings, and are not described herein.

Compared with the basic two-stage current mirror module 222, by introducing an additional PMOS tube to increase the output impedance, the current fluctuation of the output end can be reduced to a certain extent, the stability of the output current can be improved, and the dependence of the output current on the input voltage can be reduced based on the high output impedance, so that the linearity of the current mirror module 222 can be improved. In addition, the additional PMOS transistor of the three-stage current mirror module 222 may provide a higher gain-bandwidth product, thereby enabling the current mirror module 222 to have better performance in the high frequency range. It should be noted that the three-stage current mirror module 222 increases the complexity and power consumption of the circuit relative to the basic two-stage current mirror. Therefore, in practical applications, the choice of whether to use the three-stage current mirror module 222 or the basic two-stage current mirror requires trade-offs and choices according to specific design requirements and performance requirements, which are not illustrated herein.

In one embodiment, as shown in fig. 6, the first comparison module 224 is an input pair of transistors (MN 1 and MN 2) consisting of two NMOS transistors.

For the double NMOS input pair tube, the connection mode that the drain electrode is connected to the output end of the current mirror and the source electrode is connected to the input end of the comparator can realize differential amplification and improve the performance of the comparator, so that better anti-interference capability and common mode rejection ratio can be provided. Differential amplification of the input signal can be achieved by connecting the input signal to the sources of the two NMOS transistors, respectively. When the difference of the input signals is large, the differential amplifier can provide a large gain, thereby enhancing the sensitivity of the comparator to the input signals. The drain electrode is connected to the output end of the current mirror, so that the drain voltage of the input pair tube can be kept stable, and the working stability of the input pair tube is improved. When the voltage of the input signal is higher than the reference voltage, the conduction degree of one NMOS tube is increased, and the conduction degree of the other NMOS tube is reduced. This causes the current at the output of the current mirror to increase, producing a high level output. By connecting the drain to the current mirror output, it is ensured that the drain voltage of the input pair is stable, thus maintaining a constant operating state.

In one embodiment, as shown in fig. 6, offset voltage adjustable comparator 22 further includes:

the input end of the noise reduction module 2210 is connected with the output end of the first comparison module 224, and the output end of the noise reduction module 2210 is connected with the clock end of the dynamic latch comparator 24.

The noise reduction module 2210 may be a schmitt trigger, and is configured to remove noise of the output signal.

Specifically, the noise reduction module 2210 plays a role of de-jittering when the offset voltage adjustable comparator 22 is used to detect whether the signal passes through the zero point (i.e., the positive and negative alternation of the signal). When the signal passes through zero, the input signal may have some noise or oscillations, which may cause the comparator output to switch multiple times. By using the noise reduction module 2210, it is ensured that the comparator outputs a stable high/low level signal only when the signal stably crosses the zero point, thereby eliminating jitter caused by noise and further ensuring the accuracy of the zero crossing detection signal.

the input end of the amplifying module 2212 is connected with the output end of the noise reducing module 2210, and the output end of the amplifying module 2212 is connected with the clock end of the dynamic latch comparator 24.

The amplification module 2212 may refer to a buffer or the like.

Specifically, the zero crossing detection signal may have a low amplitude or high impedance after passing through the noise reduction module 2210, so that the signal is distorted or cannot be correctly transmitted, and by using the buffer amplification module 2212, the input signal may be amplified to a proper amplitude and provide sufficient driving capability to ensure that the signal can be accurately transmitted to a subsequent circuit or logic gate, so that the subsequent circuit or logic gate can be driven.

In one embodiment, the amplification module 2212 includes at least two cascaded inverters.

Specifically, by cascading the amplification module 2212 composed of at least two inverters, the input signal can be amplified to a higher amplitude. Second, the stability of the overall buffer can also be improved. Each inverter has a certain gain and bandwidth, which can be further increased by cascading, thereby improving the performance of the buffer. In addition to this, some delay compensation may be provided to ensure that the time of arrival of the signal at the target circuit is accurate in the timing related circuits.

In the above embodiment, the buffer is formed by cascading at least two inverters, so that various functions such as signal amplification, stability enhancement, delay compensation and the like can be realized, and the buffer can adapt to different application requirements and provide reliable signal transmission and processing.

In one embodiment, to describe in more detail how the offset voltage adjustable comparator 22 of the present application can adjust the offset voltage and detect zero crossing, the specific circuit configuration of the offset voltage adjustable comparator 22 shown in fig. 6 is described with reference to fig. 2.

The connection relationship between the electronic components in the circuit can be directly known from the drawings by those skilled in the art, and will not be described herein.

Specifically, as shown in fig. 6, PMOS transistors MP1, MP2, and MP3 are current mirrors, and are connected to a current source to provide bias current for a comparator; NMOS tube MN1 and NMOS tube MN2 are input pair tubes of comparator with good layout matching. The grid electrode of the MN3 is connected with a power supply and is in a switch mode; the gate of MN4 is connected to the vc_n signal, when vc_n is low, the second switching tube MN is turned off and MN4 works in the cut-off region, the offset voltage adjustable comparator 22 outputs a high level, when vc_n is high, the second switching tube MN is turned on and MN4 is turned on, and the offset voltage adjustable comparator 22 starts to compare the voltages of PGND and LX. The gate voltages of the NMOS transistor MN1 and the NMOS transistor MN2 are the same, and the driving current capability of the NMOS transistor MN1 is I2 (i2=i3). When the switching node LX voltage is higher than the PGND voltage, the gate-source voltage vgs1 of the NMOS transistor MN1 is higher than the gate-source voltage of the NMOS transistor MN2, so that the driving current capability of the NMOS transistor MN1 is stronger than that of the NMOS transistor MN2, so that the driving current capability of the NMOS transistor MN2 is weaker than I3, the input node of the schmitt trigger ism is pulled up, and the VZCD outputs a high level. R1 is a fixed resistor, and R2 is an adjustable resistor regulated by the offset voltage regulating code value A shown in FIG. 2. IBUF is a buffer consisting of two cascaded inverters. If the threshold voltage difference between MN1 and MN2 is Δvth, and assuming that the current source i2=i3=i, the offset voltage VOS of the comparator can be expressed as: vos= [ delta ] vth+ (R2-R1) ×i the resistance of resistor R2 can be adjusted by adjusting the offset voltage adjustment code value a, so as to change the offset voltage VOS.

Specifically, on control is performed on the NMOS transistor MN3 and the NMOS transistor MN4 based on the control signals (the power supply voltage signal IOVDD and the first pulse signal V-CN), for example, the second switching transistor MN is turned off and MN4 operates in the off-region when vc_n is low level, the offset voltage adjustable comparator 22 outputs high level, the second switching transistor MN is turned on and MN4 is turned on when vc_n is high level, and the offset voltage adjustable comparator 22 starts comparing the voltage magnitudes of PGND and LX. If the threshold voltage difference between the NMOS transistor MN1 and the NMOS transistor MN2 is Δvth, and assuming that the current source i2=i3=i, the offset voltage VOS of the comparator may be expressed as: vos= [ delta ] vth+ (R2-R1) ×i. The resistance value of the resistor R2 can be adjusted by adjusting the offset voltage adjusting code value A, so that the size of the offset voltage VOS is changed, and the output zero-crossing detection signal can be adjusted based on the offset voltage.

In one embodiment, as shown in FIG. 7, dynamic latching comparator 24 includes a first reset module 242, a latching module 244, a second adjustment module 246, a second comparison module 248, and a second reset module 2410. The power supply end of the first reset module 242 is used for connecting with a power supply voltage, and the control end of the first reset module 242 is used for accessing a zero crossing detection signal; the power supply end of the latch module 244 is used for connecting power supply voltage, the reset end of the latch module 244 is connected with the output end of the first reset module 242, the first output end of the latch module 244 is connected with the first input end of the control module 26, and the second output end of the latch module 244 is connected with the second input end of the control module 26; a first output of the second adjustment module 246 is connected to a first input of the latch module 244, and a second output of the second adjustment module 246 is connected to a second input of the latch module 244; the second adjusting module 246 is configured to output an adjusting signal triggered by the zero crossing detection signal; a first output end of the second comparison module 248 is connected with a first input end of the latch module 244, a second output end of the second comparison module 248 is connected with a second input end of the latch module 244, and a control end of the second comparison module 248 is used for accessing bias voltage; the first output end of the second reset module 2410 is connected with the first input end of the second comparison module 248, the second output end of the second reset module 2410 is connected with the second input end of the second comparison module 248, the second input end of the second reset module 2410 is used for connecting a zero crossing detection point, the first input end of the second reset module 2410 is used for grounding, and the control end of the second reset module 2410 is used for accessing a zero crossing detection signal.

The first reset module 242 is configured to perform a reset operation when the zero-crossing detection signal triggers. The latch module 244 is used for latching the input signal after triggering the reset signal and outputting the latched result to the control module 26. The second adjusting module 246 is configured to output an adjusting signal triggered by the zero-crossing detection signal, and control the working state of the latch module 244 through the adjusting signal. The second comparison module 248 may be referred to as an input pair of transistors for comparing an input signal with a bias voltage and outputting the comparison result to the latch module 244. The second reset module 2410 is configured to perform a reset operation in cooperation with the first reset module 242 when the zero crossing detection signal triggers.

Specifically, the first reset module 242 and the second reset module 2410 reset the dynamic latch comparator 24 or switch between operating states under control of a clock signal at a clock terminal. When the switch is in the working state, the voltage signal of the zero-crossing detection point and the ground signal are input to the second comparison module 248, the second comparison module 248 starts to compare the voltage of the zero-crossing detection point and the ground, and inputs the comparison result to the latch module 244, the latch module 244 latches the comparison result and simultaneously outputs the adjusting signal from the output end of the latch module 244 to the control module 26, and the control module 26 outputs the first voltage adjusting code value to the offset voltage adjustable comparison module according to the received adjusting signal, so as to adjust the zero-crossing detection signal. Second, when the control module 26 receives the adjustment signal, it may also output a second voltage adjustment code value to the second adjustment module 246 to adjust the capacitance of the second adjustment module 246, so as to offset the deviation caused by the process, and further make the offset voltage of the dynamic latch comparator 24 zero, so as to eliminate the influence of the deviation of the device on the zero-crossing detection accuracy.

In the above embodiment, the dynamic latching comparator 24 achieves the functions of performing a reset operation when the zero-crossing detection signal is triggered, latching and outputting an input signal, outputting an adjustment signal according to a comparison result, and the like, by combining the above modules, so as to improve the performance and accuracy of the comparator.

In one embodiment, as shown in fig. 7, the second adjustment module 246 includes:

the output end of the first adjustable capacitor C1 is connected with the first input end of the latch module 244;

the output terminal of the second adjustable capacitor C2 is connected to the second input terminal of the latch module 244.

Specifically, as shown in fig. 7, the first adjustable capacitor C1 and the second adjustable capacitor C2 are variable capacitors, and the capacitance value is controlled by the offset voltage adjustment code value B. In the process of manufacturing, offset voltage can be introduced by factors such as mismatch of threshold voltages of the NMOS transistor MN7 and the NMOS transistor MN8 in the second comparison module 248, and deviation of manufacturing can be offset by adjusting capacitance difference of the first adjustable capacitor C1 and the second adjustable capacitor C2, so that offset voltage of the dynamic latch comparator 24 is zero, and performance and precision of the comparator are improved.

In one embodiment, as shown in fig. 7, the two output terminals of the latch module 244 are also connected with the not gates, respectively.

Specifically, in some applications, the output of the latch module 244 may need to be connected to other logic circuits that may need to have opposite logic levels than the output of the latch module 244. To achieve such an inverted output, the output of the latch may be connected to an not gate.

In one embodiment, as shown in FIG. 7, the dynamic latching comparator 24 further comprises:

the input limiting module 2412, a first input terminal of the input limiting module 2412 is used for grounding, a second input terminal of the input limiting module 2412 is used for connecting a zero crossing detection point, a first output terminal of the input limiting module 2412 is connected with a first input terminal of the second reset module 2410, and a second output terminal of the input limiting module 2412 is connected with a second input terminal of the second reset module 2410.

The input limiting module 2412 may refer to an input resistance.

Specifically, by providing the input limiting module 2412 at the input of the dynamic latching comparator 24, the magnitude of the input current can be limited, preventing excessive current from flowing into the comparator, and thus protecting the comparator from damage due to excessive current. Second, the set input limit module 2412 may prevent voltage offset of the input signal. When the input signal is connected to other circuits or devices, there may be voltage offsets, and the input limiting module 2412 may direct these offset currents to ground or other reference points by providing a path to maintain the accuracy of the input signal. In addition, in some cases, the output impedance of the input signal source is high, which can result in signal distortion when connected to the input of the comparator. By setting the input limiting module 2412, the influence of the input signal source can be reduced, and the working performance of the comparator can be improved. It should be noted that the selection of the specific input limiting module 2412 needs to be properly selected according to the specific application scenario and design requirements, and different comparators and applications may need different types of input limiting modules 2412 to meet the performance requirements.

In one embodiment, as shown in fig. 7, the latch module 244 includes a first inverter and a second inverter. The power supply end of the first inverter is used for connecting the power supply voltage, the first input end of the first inverter is connected with the first output end of the second comparison module 248, and the first output end of the first inverter is connected with the first input end of the control module 26; the power supply terminal of the second inverter is used for connecting the power supply voltage, the first input terminal of the second inverter is connected with the second output terminal of the second comparing module 248, the second input terminal of the second inverter is connected with the second output terminal of the first inverter, the first output terminal of the second inverter is connected with the second input terminal of the control module 26, and the second output terminal of the second inverter is connected with the second input terminal of the first inverter.

The latch formed by the inverters connected end to end can be specifically a ring latch or a ring buffer.

Specifically, as the delay of each inverter is basically equal, the latch formed by the inverters connected end to end can realize delay equalization, and the delay of an input signal passing through each inverter is ensured to be the same, thereby avoiding the misalignment and instability of the signal. Secondly, the latch formed by the inverters connected end to end is compact in structure and simple in wiring. Only one transmission line with equal delay is connected between adjacent inverters, and no additional control signal line is needed, so that the complexity and the power consumption of wiring are reduced.

In the above embodiment, the latch formed by the inverters connected end to end has the advantages of balanced delay, low power consumption, high speed, simplified wiring and the like, and is applicable to some application scenes with higher requirements on delay, power consumption and speed.

In a specific embodiment, in order to better describe the adjustment process of the offset voltage of the dynamic latch comparator 24 in the embodiment of the present application, the following description is made with reference to the specific circuit structure in fig. 7, and the connection relationship between specific electronic components can be directly known by those skilled in the art from the drawings, which is not repeated herein.

As shown in fig. 7, the clock signal CLK of the dynamic latch comparator 24 is connected to the zero crossing detection signal VZCD, when VZCD is at a high level, the first reset module 242 formed by the PMOS transistors MP1 and MP4 and the second reset module 2410 formed by the NMOS transistors MN9 and MN10 are in a reset state, and VOUTP and VOUTN output low levels, at this time, no static power consumption is generated. The second comparing module 248 of the comparator is composed of NMOS tubes MN7 and MN8, namely the input pair tube of the comparator adopts a common gate connection method, and the grid electrode is connected with a fixed bias voltage VCM. The first adjustable capacitor C1 and the second adjustable capacitor C2 are variable capacitors, and the capacitance value is controlled by the offset voltage adjusting code value B. In the process of manufacturing, offset voltage is introduced to factors such as mismatch of threshold voltages of the pair transistors MN7 and MN8, and deviation of manufacturing can be offset by adjusting capacitance difference of the first adjustable capacitor C1 and the second adjustable capacitor C2, so that offset voltage of the dynamic latch comparator 24 is zero. When VZCD is at low level, MP1 and MP4 are turned off, MN9 and MN10 are turned on, the dynamic latch comparator 24 starts to compare the voltages PGND and LX, the latch latches the comparison result, and the latch latches the result without static power consumption. By utilizing the characteristics of high precision, high speed and no static power consumption of the dynamic latching comparator 24, the defects of low precision and low speed of the zero crossing comparator are overcome, the second switching tube MN is accurately closed when the inductance current IL crosses zero, and the energy loss caused by reverse current and body diode conduction is avoided, so that the BUCK efficiency is improved.

In one embodiment, as shown in fig. 8, the present application provides a driving control circuit of a voltage conversion circuit, comprising:

the zero-crossing detection circuit 2 as in the above embodiment;

the first input end of the driving module is used for being connected with a pulse width modulation signal, and the second input end of the driving module is connected with the output end of the offset voltage adjustable comparator 22; the driving module is used for generating a driving signal according to the pulse width modulation signal and the zero crossing detection signal; the driving signal is used for controlling the on-off state of a switching tube in the voltage conversion circuit.

The driving module may refer to a driving circuit for controlling the on-off state of a switching tube in the voltage conversion circuit, and is configured to generate a driving signal according to the pulse width modulation signal and the zero crossing detection signal. The driving signal may refer to an on-off state for controlling a switching tube in the voltage converting circuit. For example, when the driving signal is at a high level, the switching tube is closed, the voltage conversion circuit is opened, and the voltage can be normally transmitted. When the driving signal is at a low level, the switching tube is disconnected, the voltage conversion circuit is closed, and the voltage cannot be transmitted.

In the above embodiment, the drive control circuit generates the drive signal based on the zero-crossing detection signal output by the zero-crossing detection circuit 2 and the pulse width modulation signal in the above embodiment, so as to control the on-off state of the switching tube in the voltage conversion circuit, thereby realizing accurate conversion and control of the voltage.

In one embodiment, as shown in fig. 9, the voltage conversion circuit includes a first switching tube MP and a second switching tube MN connected in series, an inductor L connected to a midpoint of connection between the first switching tube MP and the second switching tube MN, and a capacitor COUT, where one end of the inductor L, which is not connected to the first switching tube MP, is grounded through the capacitor COUT; the driving module includes:

the first driving module 42, the input end of the first driving module 42 is used for accessing the pulse width modulation signal, the first output end of the first driving module 42 is connected with the control end of the first switching tube MP, the first driving module 42 is used for generating a first driving signal and a second driving signal according to the pulse width modulation signal, and the first driving signal is used for controlling the on-off of the first switching tube MP;

the first input end of the second driving module 44 is connected with the second output end of the first driving module 42, the second input end of the second driving module 44 is connected with the output end of the offset voltage adjustable comparator 22, the output end of the second driving module 44 is connected with the control end of the second switching tube MN, the second driving module 44 is used for generating a third driving signal according to the second driving signal and the zero crossing detection signal, and the third driving signal is used for controlling the on-off state of the second switching tube MN.

The first driving control module 4 may be referred to as a dead time control module, and is configured to modulate a pulse width modulation signal to introduce dead time. The first driving signal refers to a driving signal after the dead time is introduced by the dead time control module and is used for controlling the on-off of the first switching tube MP; the second driving signal refers to a driving signal after the dead time control module introduces the dead time. The second driving module 44 may be referred to as a power tube driving module, and is configured to control on/off of the second switching tube MN. The third driving signal is used for controlling the on-off of the second switch tube MN.

Specifically, the first driving module 42 and the second driving module 44 are used for modulating the pulse width modulation signal and the zero crossing detection signal, such as introducing dead time, so as to make the driving control of the voltage conversion circuit more accurate.

In one embodiment, the present application provides a power conversion circuit comprising:

and the voltage conversion circuit is used for receiving the driving signal.

In one embodiment, an electronic device is provided that includes a power conversion circuit as in the above embodiments.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A zero-crossing detection circuit, comprising:

the first input end of the dynamic latch comparator is used for being connected with the zero crossing detection point, the second input end of the dynamic latch comparator is used for being grounded, and the clock trigger end of the dynamic latch comparator is connected with the output end of the offset voltage adjustable comparator; the dynamic latch comparator is used for outputting an adjusting signal under the triggering of the zero crossing detection signal;

the first input end of the control module is connected with the first output end of the dynamic latch comparator, the second input end of the control module is connected with the second output end of the dynamic latch comparator, and the first output end of the control module is connected with the first input end of the offset voltage adjustable comparator; the control module is used for outputting a first voltage regulation code value from the first output end according to the regulation signal;

The offset voltage adjustable comparator is further used for adjusting the zero crossing detection signal according to the first voltage adjusting code value.

2. The circuit of claim 1, wherein the second output of the control module is connected to the first input of the dynamic latching comparator, the circuit further comprising:

3. The circuit of claim 1, wherein the offset voltage adjustable comparator comprises:

the input end of the current mirror module is used for being connected with a current source, and the power supply end of the current mirror module is used for being connected with a power supply voltage;

the first input end of the first adjusting module is used for being connected with the zero crossing detection point, the second input end of the first adjusting module is used for being grounded, the first output end of the first adjusting module is connected with the first input end of the input control module, and the second output end of the first adjusting module is connected with the second input end of the input control module; the first adjusting module is used for changing the resistance value of the first adjusting module according to the first voltage adjusting code value so as to adjust the zero-crossing detection signal.

4. A circuit according to claim 3, wherein the first adjustment module comprises:

the input end of the adjustable resistor is connected with the first input end of the input control module, and the output end of the adjustable resistor is connected with the first input end of the input control module; the adjustable resistor is used for changing the resistance value of the adjustable resistor according to the first voltage adjusting code value so as to adjust the zero-crossing detection signal;

the input end of the fixed value resistor is used for being grounded, and the output end of the fixed value resistor is connected with the second input end of the input control module.

5. The circuit of claim 3, wherein the offset voltage adjustable comparator further comprises:

6. The circuit of claim 5, wherein the offset voltage adjustable comparator further comprises:

7. The circuit of claim 6, wherein the amplification module comprises at least two cascaded inverters.

8. The circuit of claim 2, wherein the dynamic latching comparator comprises:

the power supply end of the first reset module is used for being connected with a power supply voltage, and the control end of the first reset module is used for being connected with the zero-crossing detection signal;

the power supply end of the latch module is used for being connected with the power supply voltage, the reset end of the latch module is connected with the output end of the first reset module, the first output end of the latch module is connected with the first input end of the control module, and the second output end of the latch module is connected with the second input end of the control module;

the first output end of the second adjusting module is connected with the first input end of the latch module, and the second output end of the second adjusting module is connected with the second input end of the latch module; the second adjusting module is used for outputting the adjusting signal under the triggering of the zero-crossing detection signal;

The first output end of the second reset module is connected with the first input end of the second comparison module, the second output end of the second reset module is connected with the second input end of the second comparison module, the second input end of the second reset module is used for being connected with the zero-crossing detection point, the first input end of the second reset module is used for being grounded, and the control end of the second reset module is used for being connected with the zero-crossing detection signal.

9. The circuit of claim 8, wherein the second adjustment module comprises:

10. The circuit of claim 8, wherein the dynamic latching comparator further comprises:

the first input end of the input limiting module is used for being grounded, the second input end of the input limiting module is used for being connected with the zero-crossing detection point, the first output end of the input limiting module is connected with the first input end of the second resetting module, and the second output end of the input limiting module is connected with the second input end of the second resetting module.

11. The circuit of claim 8, wherein the latch module comprises:

12. A drive control circuit of a voltage conversion circuit, comprising:

a zero crossing detection circuit as claimed in any one of claims 1 to 11;

13. The circuit of claim 12, wherein the voltage conversion circuit comprises a first switching tube and a second switching tube connected in series, an inductor connected to the midpoint of the connection between the first switching tube and the second switching tube, and a capacitor, wherein one end of the inductor, which is not connected to the first switching tube, is grounded through the capacitor; the driving module includes:

the input end of the first driving module is used for being connected with the pulse width modulation signal, the first output end of the first driving module is connected with the control end of the first switching tube, the first driving module is used for generating a first driving signal and a second driving signal according to the pulse width modulation signal, and the first driving signal is used for controlling the on-off of the first switching tube;

14. A power conversion circuit, comprising:

the drive control circuit according to any one of claims 12-13, wherein the drive control circuit is configured to generate the drive signal, and the drive signal is configured to control an on-off state of a switching tube in the voltage conversion circuit;

and the voltage conversion circuit is used for receiving the driving signal.

15. An electronic device comprising the power conversion circuit of claim 14.