CN111857229B - Dynamic zero compensation circuit with protection circuit and linear voltage stabilizing circuit thereof - Google Patents
Dynamic zero compensation circuit with protection circuit and linear voltage stabilizing circuit thereof Download PDFInfo
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- CN111857229B CN111857229B CN202010542810.5A CN202010542810A CN111857229B CN 111857229 B CN111857229 B CN 111857229B CN 202010542810 A CN202010542810 A CN 202010542810A CN 111857229 B CN111857229 B CN 111857229B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The invention discloses a dynamic zero compensation circuit with a protection circuit and a linear voltage stabilizing circuit thereof, wherein the dynamic zero compensation circuit comprises: the current detection circuit, the NMOS current mirror composed of a first NMOS tube and a second NMOS tube, the variable voltage generation PMOS tube, the MOS variable resistor, the current limiting resistor, the diode active device and the compensation capacitor. The invention can reliably protect the linear voltage stabilizer from the problem of unstable loop caused by the fact that the dynamic zero shifts along with the dynamic change of the load, has simple structure and smaller circuit area, and has lower realization cost and reliable function.
Description
Technical Field
The invention relates to the field of integrated circuits related to linear voltage regulators, in particular to a dynamic zero compensation circuit with a protection circuit and a linear voltage stabilizing circuit thereof.
Background
In linear voltage regulator circuit design, the design of feedback loop stability is crucial. Zero compensation is a common loop compensation method, and the adverse effect of a secondary dominant pole on the stability of a loop is counteracted by arranging the position of a zero near the secondary dominant pole of the loop, so that a certain phase margin is obtained by a feedback loop, and the loop is stabilized. In a linear voltage regulator circuit, since the load current varies over a wide range, generally having a variation of at least 3 orders of magnitude, and the output resistance of the linear voltage regulator is generally inversely proportional to the load current, the sub-dominant pole of the linear voltage regulator also has a variation of at least 3 orders of magnitude. The compensation method of the fixed zero point generally cannot meet the stability requirement under all load conditions, so the compensation method of the dynamic zero point following the load current change is commonly used. At present, the most used dynamic zero point compensation method is realized by connecting a fixed capacitor in series with a variable resistor, and the variable resistor is generally realized by using an MOS resistor. The MOS resistor has no static bias current in a steady state because the MOS resistor is connected with the capacitor in series, and the MOS resistor works in a deep linear region in the steady state, and the resistance of the MOS resistor is inversely proportional to the difference (Vgs-Vth) between the gate-source voltage and the threshold voltage. The pass-through circuit implementation (Vgs-Vth) is proportional to the square of the load current of the linear regulator, such that the position of the compensation zero increases with increasing load current and decreases with decreasing load current.
Although the existing dynamic zero compensation circuit can well compensate the stability of a loop in a steady state, when a load dynamically changes, for example, when the load current is suddenly increased, a compensation capacitor has a discharging current, and an MOS resistor also has a current, so that the current cannot be ensured to work in a linear region. Therefore, there is a need for a protection circuit that ensures that the MOS resistor cannot enter the saturation region and that the deviation of the resistance value of the MOS resistor is within an acceptable range as much as possible when the load of the linear regulator varies.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a dynamic zero compensation circuit with a protection circuit and a linear voltage stabilizing circuit thereof, which can reliably protect the linear voltage stabilizer from the problem of unstable loop caused by the fact that the dynamic zero shifts along with the dynamic change of a load.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a dynamic zero compensation circuit with protection circuitry, comprising: the current detection circuit comprises an NMOS current mirror consisting of a first NMOS tube and a second NMOS tube, a variable voltage generation PMOS tube, an MOS variable resistor, a current limiting resistor, a diode active device and a compensation capacitor;
the output end of the current detection circuit is connected with the drain electrode of the first NMOS tube, the grid electrode and the drain electrode of the first NMOS tube are in short circuit connection and are respectively connected with the grid electrode of the second NMOS tube and the output end of the current detection circuit, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the variable voltage generation POMS tube, and the source electrode of the second NMOS tube is grounded; the grid electrode and the drain electrode of the variable voltage generation PMOS tube are in short circuit and are respectively connected with the drain electrode of the second NMOS tube and the grid electrode of the MOS variable resistor, and the source electrode is connected with the power supply; the grid electrode of the MOS variable resistor is connected with the grid electrode of the variable voltage generation PMOS tube, the drain electrode of the MOS variable resistor is connected with the upper end of the current-limiting resistor and the cathode of the diode active device, the source electrode of the MOS variable resistor is connected with the power supply, the anode of the diode active device is connected with the power supply, the lower end of the current-limiting resistor is connected with the upper end of the compensation capacitor, and the lower end of the compensation capacitor is connected with the output end of an error amplifier in a main voltage feedback loop;
the current detection circuit is used for outputting a mirror current of the load current generated according to a mirror proportion.
Further, according to the dynamic zero compensation circuit with the protection circuit, the diode active device is a schottky diode.
Further, according to the dynamic zero compensation circuit with the protection circuit, the diode active device is a diode PMOS.
Further, in the dynamic zero compensation circuit with a protection circuit as described above, the MOS variable resistor is PMOS or NMOS.
The embodiment of the present invention further provides a linear voltage stabilizing circuit, including: the main voltage feedback loop and the dynamic zero compensation circuit with the protection circuit are arranged;
the primary voltage feedback loop includes: the output PMOS transistor comprises an error amplifier, an output PMOS transistor, a first voltage-dividing resistor, a second voltage-dividing resistor and an output node;
the positive input end of the error amplifier is connected with the lower end of the first voltage-dividing resistor and the upper end of the second voltage-dividing resistor, the negative input end of the error amplifier is connected with reference voltage, and the output end of the error amplifier is connected with a node B at the grid of the output PMOS tube; the source electrode of the output PMOS tube is connected with a power supply, and the drain electrode of the output PMOS tube is connected with the output node; the upper end of the first divider resistor is connected with the output node; the lower end of the second voltage-dividing resistor is grounded; the load current and the load capacitance outside the output node connecting sheet;
the dynamic zero compensation circuit includes: the current detection circuit comprises an NMOS current mirror consisting of a first NMOS tube and a second NMOS tube, a variable voltage generation PMOS tube, an MOS variable resistor, a current limiting resistor, a diode active device and a compensation capacitor;
the output end of the current detection circuit is connected with the drain electrode of the first NMOS tube, the grid electrode and the drain electrode of the first NMOS tube are in short circuit connection and are respectively connected with the grid electrode of the second NMOS tube and the output end of the current detection circuit, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the variable voltage generation POMS tube, and the source electrode of the second NMOS tube is grounded; the grid electrode and the drain electrode of the variable voltage generation PMOS tube are in short circuit and are respectively connected with the drain electrode of the second NMOS tube and the grid electrode of the MOS variable resistor, and the source electrode is connected with the power supply; the grid electrode of the MOS variable resistor is connected with the grid electrode of the variable voltage generation PMOS tube, the drain electrode of the MOS variable resistor is connected with the upper end of the current limiting resistor and the cathode of the diode active device, the source electrode of the MOS variable resistor is connected with the power supply, the anode of the diode active device is connected with the power supply, the lower end of the current limiting resistor is connected with a node A at the upper end of the compensation capacitor, and the lower end of the compensation capacitor is connected with the output end of the error amplifier and a node B at the grid electrode of the output PMOS tube;
the power saving A is a node connecting the upper end of the compensation capacitor and the lower end of the current limiting resistor; and the node B is a node at which the lower end of the compensation capacitor is connected with the grid electrode of the output PMOS tube and the output end of the error amplifier.
Further, according to the above linear voltage stabilizing circuit, under the action of the main voltage feedback loop, the voltage value V of the output node is:
V＝Vref/R2*(R1+R2)，
wherein Vref is a voltage value of the reference voltage, R1 is a resistance value of the first voltage-dividing resistor, and R2 is a resistance value of the second voltage-dividing resistor.
Further, according to the linear voltage stabilizing circuit, the diode active device is a schottky diode.
Further, according to the linear voltage stabilizing circuit, the diode active device is a diode PMOS.
Further, in the above linear voltage stabilizing circuit, the diode active device is a low threshold voltage PMOS transistor or a triode with a diode function.
Further, in the above linear voltage stabilizing circuit, the MOS variable resistor is a PMOS or NMOS.
The invention has the beneficial effects that: the invention has simple structure and smaller circuit area, can reliably protect the linear voltage stabilizer, and can effectively avoid loop oscillation caused by overlarge change of the zero position of the feedback loop under the condition that the load of the linear voltage stabilizer is suddenly increased.
Drawings
Fig. 1 is a circuit diagram of a dynamic zero compensation circuit in a conventional linear regulator according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a linear regulator according to an embodiment of the present invention;
FIG. 3 is a diagram of an implementation example of the diode active device D _ clamp in FIG. 2;
fig. 4 is a voltage-current curve diagram of the dynamic zero compensation circuit provided in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1, a dynamic zero compensation circuit in a conventional linear regulator includes: the load current generates mirror phase current K x Iload of the load current according to mirror proportion K through the output current mirror circuit. Through the NMOS current mirror, the mirror current of the load current generates the gate control voltage VGS of the MOS variable circuit Rcomp through the PMOS transistor Mctl. The absolute value of the VGS voltage is proportional to the square of the load current. The resistance value of Rcomp is inversely proportional to the absolute value of VGS. The position of the compensation zero point is Zcomp 1/(Rcomp Ccomp). The node a represents a node at which the upper end of the dynamic zero compensation capacitor Ccomp is connected to the drain of the dynamic zero compensation MOS variable resistor Rcomp. Node B represents a node at which the lower end of the dynamic zero compensation capacitor Ccomp is connected to the gate of the output PMOS and the output of the error amplifier EA. The problems with this circuit are:
when the load current suddenly becomes large, the Vout voltage drops. The voltage feedback loop of the linear voltage regulator can enable the voltage of the node B to rapidly drop so as to improve the driving capability of the output PMOS, and enable Vout to rise and recover to the target voltage. Since the voltage across the capacitor Ccomp cannot abruptly change, the voltage at node a also drops rapidly. When the source-drain voltage of the Rcomp is larger than the difference between the gate-source voltage and the threshold voltage (VDS > VGS-Vth), the Rcomp is out of the linear region and enters the saturation region, and the resistance value of the Rcomp can be increased remarkably. At this time, the frequency of the zero point position determined by Rcomp and Ccomp is significantly reduced, the zero point position is far away from the secondary dominant pole, the phase margin of the loop of the linear regulator is significantly reduced, the stability of the loop is damaged, the loop oscillation phenomenon occurs, and the oscillation state is kept to be unable to exit.
In order to solve the above problems of the dynamic zero compensation circuit in the conventional linear regulator, as shown in fig. 2, the present invention provides a linear voltage regulator circuit, including: the main voltage feedback loop and the dynamic zero compensation circuit with the protection circuit are arranged;
the primary voltage feedback loop includes: the error amplifier EA, an output PMOS tube, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2 and an output node Vout;
the positive input end of the error amplifier EA is connected with the lower end of the first divider resistor R1 and the upper end of the second divider resistor R2, the negative input end of the error amplifier EA is connected with the reference voltage Vref, and the output end of the error amplifier EA is connected with a node B at the grid of the output PMOS tube; the source electrode of the output PMOS tube is connected with a power supply, and the drain electrode of the output PMOS tube is connected with an output node Vout; the upper end of the first voltage-dividing resistor R1 is connected with an output node Vout; the lower end of the second voltage-dividing resistor R2 is grounded; the off-chip load current Iload and the load capacitor Cload at the output node Vout are used to provide them with current and voltage.
Under the action of the main voltage feedback loop, the voltage of the output node Vout is Vref/R2 (R1+ R2), where Vref is the voltage value of the reference voltage Vref, R1 is the resistance value of the first voltage-dividing resistor, and R2 is the resistance value of the second voltage-dividing resistor.
The dynamic zero compensation circuit includes: the current detection circuit, the NMOS current mirror formed by a first NMOS tube M1 and a second NMOS tube M2, a variable voltage generation PMOS tube Mctl, a MOS variable resistor Rcomp, a current limiting resistor Rlimit, a diode active device D _ clamp and a compensation capacitor Ccomp;
the output end of the current detection circuit is connected with the drain electrode of the first NMOS transistor M1, and is used for outputting the mirror current Isense ═ K × Iload of the load current generated according to the mirror proportion K, and the mirror current Isense ═ K × Iload is the current value of the load current.
The grid electrode and the drain electrode of the first NMOS tube M1 are in short circuit and are respectively connected with the grid electrode of the second NMOS tube M2 and the output end of the current detection circuit, and the source electrode of the first NMOS tube M1 is grounded; the drain electrode of the second NMOS tube M2 is connected with the drain electrode of the variable voltage generation POMS tube Mctl, and the source electrode is grounded;
the grid electrode and the drain electrode of the variable voltage generation PMOS tube Mctl are in short circuit and are respectively connected with the drain electrode of the second NMOS tube M2 and the grid electrode of the MOS variable resistor Rcomp, and the source electrode is connected with a power supply;
the grid electrode of the MOS variable resistor Rcomp is connected with the grid electrode of the variable voltage generation PMOS tube Mctl, the drain electrode is connected with the upper end of the current limiting resistor Rlimit and the negative electrode of the diode active device D _ clamp, the source electrode is connected with the power supply, the positive electrode of the diode active device D _ clamp is connected with the power supply, the lower end of the current limiting resistor Rlimit is connected with a node A at the upper end of the compensation capacitor Ccomp, and the lower end of the compensation capacitor Ccomp is connected with the output end of the error amplifier EA and a node B at the grid electrode of the output PMOS tube.
The electricity saving A is a node connecting the upper end of the compensation capacitor Ccomp with the lower end of the current limiting resistor Rlimit; and the node B is a node at which the lower end of the compensation capacitor Ccomp is connected with the grid electrode of the output PMOS tube and the output end of the error amplifier EA.
The working principle is as follows:
when the load current Iload suddenly becomes large, the Vout voltage drops. Node a drops as the voltage at node B drops and a current appears through MOS resistor Rcomp to charge node a. At this time, because the Rlimit is connected in series with the current path, the resistance of the current path increases, the current on the current path decreases, and simultaneously, the Rlimit itself has a voltage drop, and the voltage difference between the source and the drain of the MOS resistor Rcomp decreases. When the drain-source voltage of the MOS resistor Rcomp exceeds the threshold voltage of the diode active device D _ clamp, the diode active device D _ clamp is started, the drain-source voltage of the MOS resistor Rcomp is clamped at the starting voltage Vth _ D of the diode active device D _ clamp, meanwhile, the current is limited to the state that Vth _ D/Rcomp cannot be increased continuously, and the current larger than the Vth _ D/Rcomp is shunted to the current path of the diode active device D _ clamp. D _ clamp not only limits the drain-source voltage protection of the MOS resistor Rcomp from entering the deep saturation region, but it also provides a low impedance path in parallel to Rcomp during transient state of load change, thereby ensuring that the frequency of zero compensation does not become too low due to the resistance of Rcomp becoming large, thereby causing the linear regulator loop to be unstable.
There are many ways to implement the diode active device D _ clamp in fig. 2, and two ways are listed in this embodiment, as shown in fig. 3.
(1) The diode active device is implemented with a schottky diode. The schottky diode has the advantages of very low turn-on voltage, usually around 300mV, and very small on-resistance, and can reliably limit the drain-source voltage of the MOS resistor Rcomp to operate in the linear region. When current flows through the circuit, the instantaneous low parallel resistance can protect the series resistance forming the zero point from changing from low resistance to high resistance in the instantaneous state of load change, so that the loop is unstable. However, the schottky diode has disadvantages that its reverse leakage is large and its turn-off resistance is relatively low under the conditions of high temperature and ff process angle. This disadvantage can severely affect the frequency variation range of the dynamic zero compensation.
(2) The diode active device is realized by using a PMOS (P-channel metal oxide semiconductor) with a short-circuited grid and drain, namely a diode PMOS, and the width-to-length ratio of the diode active device is far greater than that of the MOS resistor Rcomp. Although the clamp voltage of the drain-source voltage of the Rcomp of the MOS resistor is larger than that of the schottky diode in this implementation, and the effect of protecting the MOS resistor Rcomp from the saturation region is not as good as that of the schottky diode, the diode PMOS still provides a low resistance path when the transient conduction current flows due to the large width-to-length ratio, thereby protecting the zero point from becoming low frequency due to the sudden increase of the series resistance. And when the PMOS is switched off, the PMOS can have very high resistance even under the conditions of high temperature and ff process angle, so that the effect and the compensation range of the dynamic zero compensation circuit are not influenced.
The method for realizing the diode active device comprises the Schottky diode and the PMOS tube with the large-size grid-drain short circuit, and also comprises the active devices which can realize the diode function, such as a low-threshold voltage PMOS tube, a triode and the like. In the implementation form of the circuit, besides the implementation of the MOS resistor and the protection circuit by using PMOS, the MOS resistor and the protection circuit can be implemented by using NMOS devices.
Fig. 4 is an I-V diagram of the MOS resistor Rcomp. The abscissa is the drain-source voltage Vds — Rcomp of the MOS resistor Rcomp. The ordinate is the current Ids _ Rcomp through the MOS resistor Rcomp. The curve is a curve of Ids _ Rcomp versus Vds _ Rcomp given the gate-source voltage Vgs of the MOS resistor Rcomp.
Operating point a is the operating point at which Rcomp is steady state. At this time, the current of Rcomp is 0 and the drain-source voltage is also zero. Rcomp operates in the deep linear region with an output resistance that is the inverse of the slope of the curve at operating point a.
The operating point B is the operating point of Rcomp during a transient when the load suddenly becomes large and the dynamic zero compensation circuit has no protection circuit. At this time node a drops as the voltage at node B drops, there is current to charge node a through Rcomp, and the drain-source of Rcomp creates a voltage difference because Rcomp has current through it. When the voltage difference is large, for example, the drain-source voltage is greater than the difference between the gate-source voltage and the threshold voltage, Rcomp deviates from the linear region and enters the saturation region. The resistance of the saturation region of a MOS device is much greater than the linear region. It can be seen that the inverse of the slope of operating point B is much greater than the inverse of the slope of operating point a. The resistance at point B is much greater than the resistance at point a. At the moment, the zero position of the linear voltage regulator is far away from the designed value, and the loop is unstable and easy to oscillate.
The operating point C is the operating point of Rcomp when the load suddenly increases in the transient process, the dynamic zero compensation circuit is provided with a protection circuit, and a diode active device D _ clamp of the protection circuit is realized by a Schottky diode. The Schottky diode clamps the drain-source voltage of the Rcomp at a relatively low voltage, and meanwhile, the current limiting resistor Rlimit and the Schottky diode D _ clamp reduce the current passing through the Rcomp, the working point of the Rcomp is at the position C, the slope of the point C is close to that of the point A, so that the resistance of the Schottky diode is not greatly different from that of the Schottky diode in a steady state, and the position of a zero point and the stability of a loop do not greatly deviate from the working point A.
The working point D is the working point of Rcomp when the transient process of sudden load increase occurs and the dynamic zero compensation circuit is provided with a protection circuit, and a diode active device D _ clamp of the protection circuit is realized by a PMOS (P-channel metal oxide semiconductor), namely a diode PMOS, with a large-size grid-drain short circuit. The diode PMOS clamps the drain-source voltage of Rcomp at a voltage slightly higher than that of the schottky diode and closer to the saturation region than the schottky diode, but the current limiting resistor Rlimit and the PMOS diode D _ clamp reduce the current passing through Rcomp, and at this time, the operating point of Rcomp is at the position D, the slope of the point D is slightly reduced compared with the slope of the point a, but the difference is not large, and the zero point position is shifted but not to such an extent that the loop is unstable, so it is sufficient to ensure the effect that the zero point position and the loop stability are not greatly shifted compared with the operating point a.
From the position of the operating points a, B, C, D of the I-V curve in fig. 4, it can be seen that:
when the protection circuit is not provided, the resistance value (operating point B) of the variable resistor Rcomp of the dynamic zero point compensation circuit is much larger than the resistance value (operating point a) of Rcomp in the static state during a transient state in which the load suddenly increases, so that the zero point position has a large variation and the loop is liable to be unstable. After the dynamic zero compensation circuit is added, no matter the scheme (working point C) of a Schottky diode or the scheme (working point D) of a large-size grid-drain short-circuit PMOS, in the transient process that the load is suddenly increased, the resistance value (working points C and D) of the variable resistor Rcomp of the dynamic zero compensation circuit is close to the resistance value (working point A) of the Rcomp in a static state, so that the change of the zero position is small and the loop can keep a stable state. Therefore, the dynamic zero compensation protection circuit realizes the purpose of protecting the linear voltage regulator with reliable function by using fewer devices, smaller area and lower cost, and avoids the problem of unstable loop caused by the deviation of the dynamic zero along with the dynamic change of the load.
The invention adopts simple resistance current limiting, and the diode voltage limiting resistance protects the dynamic zero compensation current to avoid entering unstable oscillation state in transient change. The purpose of protection is achieved through a simple circuit, the area cost is minimum, and the reliability of the circuit is higher.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. A dynamic zero compensation circuit with a protection circuit, comprising: the current detection circuit comprises an NMOS current mirror consisting of a first NMOS tube and a second NMOS tube, a variable voltage generation PMOS tube, an MOS variable resistor, a current limiting resistor, a diode active device and a compensation capacitor;
the output end of the current detection circuit is connected with the drain electrode of the first NMOS tube, the grid electrode and the drain electrode of the first NMOS tube are in short circuit connection and are respectively connected with the grid electrode of the second NMOS tube and the output end of the current detection circuit, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the variable voltage generation POMS tube, and the source electrode of the second NMOS tube is grounded; the grid electrode and the drain electrode of the variable voltage generation PMOS tube are in short circuit and are respectively connected with the drain electrode of the second NMOS tube and the grid electrode of the MOS variable resistor, and the source electrode is connected with a power supply; the grid electrode of the MOS variable resistor is connected with the grid electrode of the variable voltage generation PMOS tube, the drain electrode of the MOS variable resistor is connected with the upper end of the current-limiting resistor and the cathode of the diode active device, the source electrode of the MOS variable resistor is connected with the power supply, the anode of the diode active device is connected with the power supply, the lower end of the current-limiting resistor is connected with the upper end of the compensation capacitor, and the lower end of the compensation capacitor is connected with the output end of an error amplifier in a main voltage feedback loop;
the current detection circuit is used for outputting a mirror current of the load current generated according to the mirror proportion.
2. The dynamic zero compensation circuit with protection circuit of claim 1, wherein the diode active device is a schottky diode.
3. The dynamic zero compensation circuit with the protection circuit of claim 1, wherein the diode active device is a diode PMOS.
4. The dynamic zero compensation circuit with the protection circuit of claim 1, wherein the MOS variable resistor is PMOS or NMOS.
5. A linear voltage regulator circuit, comprising: the main voltage feedback loop and the dynamic zero compensation circuit with the protection circuit are arranged;
the primary voltage feedback loop includes: the output PMOS transistor comprises an error amplifier, an output PMOS transistor, a first voltage-dividing resistor, a second voltage-dividing resistor and an output node;
the positive input end of the error amplifier is connected with the lower end of the first voltage-dividing resistor and the upper end of the second voltage-dividing resistor, the negative input end of the error amplifier is connected with reference voltage, and the output end of the error amplifier is connected with a node B at the grid of the output PMOS tube; the source electrode of the output PMOS tube is connected with a power supply, and the drain electrode of the output PMOS tube is connected with the output node; the upper end of the first divider resistor is connected with the output node; the lower end of the second voltage-dividing resistor is grounded; the load current and the load capacitance outside the output node connecting sheet;
the dynamic zero compensation circuit includes: the current detection circuit comprises an NMOS current mirror consisting of a first NMOS tube and a second NMOS tube, a variable voltage generation PMOS tube, an MOS variable resistor, a current limiting resistor, a diode active device and a compensation capacitor;
the output end of the current detection circuit is connected with the drain electrode of the first NMOS tube, the grid electrode and the drain electrode of the first NMOS tube are in short circuit connection and are respectively connected with the grid electrode of the second NMOS tube and the output end of the current detection circuit, and the source electrode of the first NMOS tube is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the variable voltage generation POMS tube, and the source electrode of the second NMOS tube is grounded; the grid electrode and the drain electrode of the variable voltage generation PMOS tube are in short circuit and are respectively connected with the drain electrode of the second NMOS tube and the grid electrode of the MOS variable resistor, and the source electrode is connected with the power supply; the grid electrode of the MOS variable resistor is connected with the grid electrode of the variable voltage generation PMOS tube, the drain electrode of the MOS variable resistor is connected with the upper end of the current limiting resistor and the cathode of the diode active device, the source electrode of the MOS variable resistor is connected with the power supply, the anode of the diode active device is connected with the power supply, the lower end of the current limiting resistor is connected with a node A at the upper end of the compensation capacitor, and the lower end of the compensation capacitor is connected with the output end of the error amplifier and a node B at the grid electrode of the output PMOS tube;
the node A is a node connecting the upper end of the compensation capacitor and the lower end of the current-limiting resistor; and the node B is a node at which the lower end of the compensation capacitor is connected with the grid electrode of the output PMOS tube and the output end of the error amplifier.
6. The linear voltage regulator circuit of claim 5 wherein the voltage value V at the output node under the influence of the primary voltage feedback loop is:
V＝Vref/R2*(R1+R2)，
wherein Vref is a voltage value of the reference voltage, R1 is a resistance value of the first voltage-dividing resistor, and R2 is a resistance value of the second voltage-dividing resistor.
7. The linear voltage regulator circuit of claim 5, wherein the diode active device is a Schottky diode.
8. The linear voltage regulator circuit of claim 5, wherein the diode active device is a diode PMOS.
9. The linear voltage regulator circuit of claim 5, wherein the diode active device is a low threshold voltage PMOS transistor or a triode with diode function.
10. The linear voltage regulator circuit of claim 5, wherein the MOS variable resistor is either PMOS or NMOS.
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| CN113885649B (en) * | 2021-09-24 | 2023-06-30 | 圣邦微电子（北京）股份有限公司 | Low-dropout linear voltage regulator |
| CN114879794B (en) * | 2022-05-25 | 2023-07-07 | 西安微电子技术研究所 | On-chip capacitor implementation circuit for LDO frequency compensation and LDO circuit |
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| US8169203B1 (en) * | 2010-11-19 | 2012-05-01 | Nxp B.V. | Low dropout regulator |
| CN103105883A (en) * | 2011-11-11 | 2013-05-15 | 中国科学院微电子研究所 | Linear voltage regulator with load detection circuit and dynamic zero compensation circuit |
| CN106940579A (en) * | 2017-03-27 | 2017-07-11 | 北京松果电子有限公司 | Low pressure difference linear voltage regulator and its frequency compensation method |
| CN108469759A (en) * | 2018-02-09 | 2018-08-31 | 福建睿能科技股份有限公司 | A kind of air valve control system |
-
2020
- 2020-06-15 CN CN202010542810.5A patent/CN111857229B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8169203B1 (en) * | 2010-11-19 | 2012-05-01 | Nxp B.V. | Low dropout regulator |
| CN103105883A (en) * | 2011-11-11 | 2013-05-15 | 中国科学院微电子研究所 | Linear voltage regulator with load detection circuit and dynamic zero compensation circuit |
| CN106940579A (en) * | 2017-03-27 | 2017-07-11 | 北京松果电子有限公司 | Low pressure difference linear voltage regulator and its frequency compensation method |
| CN108469759A (en) * | 2018-02-09 | 2018-08-31 | 福建睿能科技股份有限公司 | A kind of air valve control system |
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