JP2018098849A - Power module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce initial variations in switching loss and surge voltage, and further, to reduce a surge voltage generated when a power semiconductor element is turned off in an overcurrent state.SOLUTION: A power MOS 43 is turned on by injection of a control drive current I41 supplied from a constant current circuit 20 and a switch 41 to its input capacitance of a gate, and turned off by discharge of stored electric charge in the input capacitance and by emission of a control drive current I42 via a switch 42 and a constant current circuit 30-1. In a case of an overcurrent state when the power MOS 43 is turned off, the overcurrent state is detected by a surge voltage suppression circuit 50, and the control drive current I42 is reduced, and the reduced control drive current I43 is emitted to turn off the power MOS 43.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power module in which power elements and the like are accommodated in one package.

  Examples of power semiconductor elements constituting the power module include a power MOSFET (hereinafter simply referred to as “power MOS”), an insulation-controlled bipolar transistor (hereinafter referred to as “IGBT”), a gallium nitride (GaN) power device, and carbonized carbon. Power transistors such as silicon (SiC) power devices are known.

Patent Document 1 describes a technology of a semiconductor device with a current detection function that can accurately detect a current flowing through an inductive load in a semiconductor device that uses an IGBT to drive and control an inductive load such as an AC motor. ing.
Patent Document 2 discloses a constant current source, a switching circuit, and a current mode selection circuit that use a current mirror to reduce current consumption in a drive circuit as a power module using, for example, an IGBT as an insulated gate switching element. The technology of a drive circuit having

  In Patent Document 3, an input DC voltage is converted into an AC voltage by a MOSFET which is a power MOS on the primary side and an insulation transformer, and then converted into a DC voltage by a synchronous rectification MOSFET and a reflux MOSFET on the secondary side. An insulated direct current / direct current (DC / DC) converter that converts and outputs is described. In this DC / DC converter, in order to prevent an overvoltage generated in the secondary side synchronous rectification MOSFET and the freewheeling MOSFET when the operation is stopped, the controller stops the synchronous rectification MOSFET and The reflux MOSFET is stopped by a soft stop operation.

FIG. 8 is an equivalent circuit diagram showing an outline of a conventional N-channel power MOS.
The N-channel power MOS 1 has three electrodes: a gate G, a drain D, and a source S. For example, a load resistor Rl on the load circuit 6 side and a power supply E that outputs a power supply voltage Vdd are connected in series to the drain and source of the N-channel power MOS1. In this N-channel power MOS1, when the gate voltage Vg applied to the gate G rises and exceeds the threshold voltage Vth, the drain-source is turned on, and when the gate voltage Vg falls and falls below the threshold voltage Vth, The drain-source is turned off.

  The gate G, drain D, and source S have parasitic capacitance, parasitic inductance, and the like. For example, a parasitic capacitance Cgd exists between the gate and the drain, a parasitic capacitance Cgs exists between the gate and the source, and a parasitic capacitance Cds exists between the drain and the source. A parasitic inductance Ld exists on the drain D side, and a parasitic inductance Ls exists on the source S side.

It is the parasitic capacitance Cgd between the gate and the drain that greatly affects the switching characteristics. The parasitic capacitance Cgd between the gate and the drain rapidly increases, for example, about 10 times when the drain-source voltage Vds becomes equal to or lower than the gate-source voltage Vgs. A relational expression such as the following expression (1) is established for each capacitor of the power MOS 1.
Input capacitance Ciss≈Cgd + Cgs
Feedback capacity Crss≈Cgd
Output capacity Coss≈Cgd + Cds (1)

  Since the power MOS 1 is a voltage-controlled element, it does not require a drive current when it is kept in an on state or an off state. However, every time a switching operation is performed, a charge / discharge current is applied to the input capacitance Ciss. Flowing.

  FIG. 9 is a switching operation waveform diagram of the power MOS 1 with respect to the load resistor Rl of FIG.

  In the power MOS 1 of FIG. 8, when the drain-source voltage Vds falls from a high (hereinafter referred to as “H”) level to a low (hereinafter referred to as “L”) level (that is, the drain current Id changes from the L level to the H level). When the drain-source voltage Vds rises from the L level to the H level (that is, when the drain current Id falls from the H level to the L level), it turns off.

  Here, the turn-on time tr is the time between 90% of the falling waveform of the drain-source voltage Vds and the time of 10% before the falling end. Further, the turn-off time tf is a time between a time of 10% from the start of the rise and a time of 90% before the end of the rise in the rising waveform of the drain-source voltage Vds.

  The hatching region at the intersection of the falling of the drain-source voltage Vds and the rising of the drain current Id and the hatching region at the intersection of the rising of the drain-source voltage Vds and the falling of the drain current Id are on. This is a switching loss Sloss (= Vds × Id) that occurs at the time of switching off / off. When the drain-source voltage Vds rises, an overvoltage surge voltage Vdsg [= (Ld + Ls) × di / dt, where di / dt is a switching time] may occur due to the influence of the parasitic inductances Ld and Ls.

  FIG. 10 is a data sheet showing an example of electrical and thermal characteristics (case temperature Tc = 25 ° C.) of the power MOS 1 of FIG. The case temperature Tc is the temperature of a case that is a package that houses the power MOS 1.

  In FIG. 10, the drain-source on-resistance Ron has a standard value TYP = 6.9 mΩ and a maximum value MAX = 8.7 mΩ as standard values when the drain current Id = 25 A and the gate-source voltage Vgs = 10 V. is there. As for the gate threshold voltage Vth, when the drain current Id = 1 mA and the drain-source voltage Vds = 10 V, the standard value is the minimum value MIN = 2.0 V, the standard value TYP = 3.0 V, and the maximum value MAX = 4.0 V. It is.

  When the drain-source voltage Vds = 25 V, the gate-source voltage Vgs = 0 V, and the operating frequency f = 1 MHz, the input capacitance Ciss is the standard value TYP = 5880 pF, and the feedback capacitance Crss is the standard value. The standard value TYP = 250 pF, and the output capacitance Coss is the standard value TYP = 530 pF.

  Also, drain current Id = 25A, load resistance Rl = 2Ω, power supply voltage Vdd = 50V, gate resistance Rg = 0Ω, (+) side gate-source voltage Vgs (+) = 10V, and (−) side gate-source When the inter-voltage Vgs (−) = 0V, the turn-on time tr is a standard value TYP = 28 ns as a standard value, and the turn-off time tf is a standard value TYP = 49 ns as a standard value.

JP 2003-299363 A International Publication WO2012-153659 JP2015-43652A

  Conventional power modules using power semiconductor elements such as the power MOS 1 have the following problems (A) and (B).

  (A) When only the standard value TYP is defined as the standard value of the turn-on time tr and the turn-off time tf in the data sheet of FIG. 10 showing the electrical and thermal characteristics of the power MOS 1 (for example, the standard of the turn-on time tr) The value TYP is 28 ns, the standard value TYP of the turn-off time tf is 49 ns), and there is no standard value of the maximum value MAX / minimum value MIN in the device design, so the worst (worst) design of the power module cannot be performed. That is, in the switching operation waveform of FIG. 9, the worst values of the switching loss Sloss (= Vds × Id) and the surge voltage Vdsg [= (Ld + Ls) × di / dt] are not known.

  Even if the maximum value MAX / minimum value MIN of the turn-on time tr / turn-off time tf can be normalized, the standard value TYP (for example, tr = 28 ns, tf = 49 ns), the maximum value MAX / minimum value MIN is in the range of −50% / + 100%. If the value is used as it is in the design of the power module, the worst value of the switching loss Sloss becomes twice the standard value TYP, and the heat radiation design must be twice as much. Further, regarding the minimum value MIN of the turn-on time tr / turn-off time tf, the surge voltage Vdsg generated by the parasitic inductances Ld and Ls is twice as large as the standard value TYP. There is concern over the deterioration of (Electro-Magnetic Interference noise; EMI noise).

  (B) When the power MOS 1 is turned off by a current in an overcurrent state larger than normal, a large surge voltage Vdsg is generated due to a short switching time (di / dt) when the power MOS is off, and in some cases, the power MOS 1 There is a problem that the breakdown voltage is exceeded. However, Patent Document 3 does not disclose or suggest such a problem.

  The power module of the present invention includes a power semiconductor element, a first constant current circuit, a first switch, a second constant current circuit, a second switch, and a surge voltage suppression circuit.

  Here, the power semiconductor element includes a first electrode, a second electrode, and a control electrode that performs an on / off operation between the first electrode and the second electrode when a control voltage is applied, The switching element is turned on when a first control drive current is injected into an input capacitance composed of a parasitic capacitance generated in the control electrode, and is turned off when a stored charge of the input capacitance is discharged and a second control drive current is discharged. . The first constant current circuit is a circuit for supplying a constant first control drive current corresponding to an input first reference voltage. The first switch is an on / off operation according to a drive signal, and injects the first control drive current into the input capacitance when the first switch is in an on state.

  The second constant current circuit is a circuit for supplying a constant second control drive current corresponding to the input second reference voltage. The second switch is turned off when the first switch is turned on by the drive signal, and turned on when the first switch is turned off, and the second control drive current is grounded. It is a switch to release. Further, the surge voltage suppression circuit detects an overcurrent state of a conduction current flowing between the first electrode and the second electrode of the power semiconductor element, and based on the overcurrent detection result, the second reference voltage and In the circuit, the second control drive current is changed to suppress a surge voltage generated when the power semiconductor element is turned off.

  The surge voltage suppression circuit, for example, detects an overcurrent state of the conduction current and outputs the overcurrent detection result, and adjusts the second reference voltage based on the overcurrent detection result. And a voltage adjustment circuit for changing the second control drive current.

  In addition, the surge voltage suppression circuit receives, for example, a third reference voltage smaller than the second reference voltage, and a constant third smaller than the second control drive current corresponding to the third reference voltage. A third constant current circuit that discharges a control drive current from the input capacitance to the ground side through the second switch; and an overcurrent detection circuit that outputs the overcurrent detection result when an overcurrent state of the conduction current is detected. And a selection means for selecting and operating the third constant current circuit in place of the second constant current circuit when the overcurrent detection result is input.

For example, the power module further includes a reference voltage supply circuit that supplies the first reference voltage, the second reference voltage, and the third reference voltage.
The reference voltage supply circuit includes, for example, a reference power supply that outputs the first reference voltage, the second reference voltage, and the third reference voltage.

  The reference voltage supply circuit includes, for example, voltage dividing resistors that divide a power supply voltage and output the first reference voltage, the second reference voltage, and the third reference voltage, respectively.

  The first constant current circuit detects, for example, a first stage or a plurality of stages of a first current mirror circuit that passes the first control drive current proportional to the first drive current and detects the first drive current. And a first error amplification circuit that changes the first drive current by causing the first drive voltage to follow the first reference voltage. The second constant current circuit detects, for example, a first stage or a plurality of stages of a second current mirror circuit that passes the second control drive current proportional to the second drive current and detects the second drive current. And a second error amplification circuit that changes the second drive current by causing the second drive voltage to follow the second reference voltage. Further, the third constant current circuit detects, for example, a first stage or a plurality of stages of third current mirror circuits that flow the third control drive current proportional to the third drive current, and the third drive current. And a third error amplifying circuit that changes the third drive current by causing the third drive voltage to follow the third reference voltage.

  The power module is accommodated in a package, for example.

  The power module of the present invention has the following effects (a) to (c).

  (A) Since the first constant current circuit and the second constant current circuit are provided, the turn-on time and / or the second reference voltage can be adjusted by adjusting the first reference voltage and / or the second reference voltage according to variations in the power semiconductor elements. Alternatively, variation in the maximum value and / or the minimum value of the turn-off time can be improved. Thereby, a power module with little variation in switching loss and surge voltage can be realized.

  (B) Since the surge voltage suppression circuit is provided, when the conduction current of the power semiconductor element becomes an overcurrent state, the second control drive current changes, and the surge voltage generated when the power semiconductor element is turned off is suppressed. Is done. Thereby, it is possible to realize a power module in which a surge voltage generated when the power semiconductor element is turned off in an overcurrent state is reduced.

  (C) When the first constant current circuit, the second constant current circuit, and the third constant current circuit are configured by, for example, a current mirror circuit and an error amplification circuit, the current amplification circuit can have a current amplification factor by making the current mirror circuit multistage. Increase and stability of characteristics can be realized.

Schematic configuration diagram showing a power module in Embodiment 1 of the present invention Schematic configuration diagram showing a power module in Embodiment 2 of the present invention Circuit diagram showing a configuration example of the first constant current circuit in FIG. Circuit diagram showing a configuration example of the second and third constant current circuits in FIG. 2 is a circuit diagram showing a configuration example of the first and second switches in FIG. Voltage / current waveform diagram showing operation of the power module in FIG. Voltage / current waveform diagram showing details of short-circuit fault turn-off in FIG. The circuit diagram which shows the structural example of the reference voltage supply circuit in Example 3 of this invention. Equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element in Example 4 of the present invention Equivalent circuit diagram showing outline of conventional N-channel type power MOS Switching operation waveform diagram of the power MOS1 with respect to the load resistance Rl of FIG. Data sheet showing an example of the electrical and thermal characteristics (case temperature Tc = 25 ° C.) of the power MOS 1 in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram illustrating a power module according to a first embodiment of the present invention.
A gate drive power supply 55 is connected to the input side of the power module 10, and a load circuit 60 is connected to the output side of the power module 10.

  The power module 10 includes a package 10a that houses a power semiconductor element and the like. The package 10a is formed of a highly heat-resistant / insulating resin or ceramics. The package 10a has a (+) side power supply terminal 11a for inputting a DC power supply voltage VDD, a (−) side power supply terminal 11b on the ground side, a control terminal 12 for inputting a drive signal (for example, a gate pulse) Pg, A +) side output terminal 13a and a ground side (−) side output terminal 13b are provided.

  The package 10a includes a first constant current circuit 20, a second constant current circuit 30-1, a first reference power supply 23 for adjusting a turn-on time (tr) as a reference voltage supply circuit, and a turn-off time (tf1) adjustment. The second reference power supply 33-1, the first and second switches 41 and 42, the power semiconductor element (for example, N-channel power MOS) 43, and the surge voltage suppression circuit 50 are accommodated.

  The first constant current circuit 20, the first and second switches 41 and 42, and the second constant current circuit 30-1 are connected in series between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. Has been. A gate as a control electrode of the power MOS 43 is connected to a connection point between the first switch 41 and the second switch 42. The drain of the power MOS 43 as the first electrode is connected to the (+) side output terminal 13a, and the source of the power MOS 43 as the second electrode is connected to the (−) side output terminal 13b.

  The first constant current circuit 20 is a circuit for supplying a constant first control drive current I41 corresponding to the first reference voltage Vtr input from the first reference power supply 23 for adjusting the turn-on time (tr) to the first switch 41 side. It is. The second constant current circuit 30-1 includes a constant second control drive current I42 or a third control drive corresponding to the second reference voltage Vtf1 input from the second reference power supply 33-1 for adjusting the turn-off time (tf1). In this circuit, a current I43 (<I42) is supplied to the ground side.

  The first switch 41 is turned on / off by the gate pulse Pg input from the control terminal 12 (for example, turned on by the L level of the gate pulse Pg and turned off by the H level). The first control drive current I41 from the one constant current circuit 20 is injected through the gate of the power MOS 43 into the input capacitance Ciss composed of its parasitic capacitance. The second switch 42 is turned off by the gate pulse Pg input from the control terminal 12 when the first switch 41 is turned on (for example, turned off by the L level of the gate pulse Pg). When it is off, it is turned on (for example, turned on by the H level of the gate pulse Pg), and the second control drive current I42 or the third control drive current I43 from the gate of the power MOS 43 is supplied to the second constant current circuit 30- It releases to the 1 side.

  The power MOS 43 is turned on when the first control drive current I41 is injected into the input capacitance Ciss generated at the gate and the gate voltage Vg as the control voltage applied to the input capacitance Ciss rises and exceeds the threshold voltage Vth, and the input capacitance The switching element is turned off when the accumulated charge of Ciss is discharged and the second control driving current I42 or the third control driving current I43 is discharged and the gate voltage Vg applied to the input capacitance Ciss falls below the threshold voltage Vth. .

  A surge voltage suppression circuit 50 is connected to the drain side of the power MOS 43 and the second reference power source 33-1 side. The surge voltage suppression circuit 50 detects an overcurrent state of a conduction current (for example, drain current Id) flowing between the drain and source of the power MOS 43, and based on the overcurrent detection result, the second reference voltage Vtf1 and the second control voltage. This is a circuit that suppresses a surge voltage generated when the power MOS 43 is turned off by changing the drive current I42.

  The surge voltage suppression circuit 50 includes, for example, an overcurrent detection circuit 51 connected between the (+) side output terminal 13a and the drain side of the power MOS 43, the overcurrent detection circuit 51, and the second reference power supply 33-1. And a voltage adjusting circuit 52 connected between the two sides. The overcurrent detection circuit 51 is a circuit that detects an overcurrent state of the drain current Id in the power MOS 43 and outputs an overcurrent detection signal S51 as an overcurrent detection result to the voltage adjustment circuit 52. The voltage adjustment circuit 52 adjusts the second reference voltage Vtf1 of the second reference power supply 33-1 based on the overcurrent detection signal S51, and changes the second control drive current I42 to the third control drive current I43 (<I42). It is a circuit to change.

  A gate drive power supply 50 for applying the power supply voltage VDD is connected between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. Further, a load circuit 60 is connected to the (+) side output terminal 13a and the (−) side output terminal 13b. The load circuit 60 includes, for example, a load resistor 61, a DC drive power source 62, and the like, which are connected in series between the (+) side output terminal 13a and the (−) side output terminal 13b.

(Operation of Example 1)
In the normal state where the drain current Id of the power MOS 43 is not in an overcurrent state, the overcurrent detection signal S51 is not output from the overcurrent detection circuit 51 in the surge voltage suppression circuit 50, so the surge voltage suppression circuit 50 does not operate. When the gate pulse Pg applied to the control terminal 12 is L level, the first switch 41 is turned on and the second switch 42 is turned off. The first constant current circuit 20 operates to flow a constant first control drive current I41 based on the first reference voltage Vtr supplied from the first reference power supply 23 for adjusting the turn-on time (tr). The first control drive current I41 flows to the gate of the power MOS 43 through the first switch 41.

  When the first control drive current I41 flows to the gate of the power MOS 43, the first control drive current I41 is injected into the input capacitor Ciss of the power MOS 43, and the gate voltage Vg of the power MOS 43 rises. When the gate voltage Vg rises and exceeds the threshold voltage Vth of the power MOS 43, the power MOS 43 is turned on after a predetermined turn-on time tr. When the power MOS 43 is turned on, a drive current flows from the drive power source 62 in the load circuit 60 to the load resistor 61 to the power MOS 43 to operate the load circuit 60.

  When the gate pulse Pg applied to the control terminal 12 becomes H level, the first switch 41 is turned off and the second switch 42 is turned on. Then, the electric charge accumulated in the input capacitor Ciss of the power MOS 43 flows to the second constant current circuit 30-1 through the second switch 42. The second constant current circuit 30-1 operates to flow a constant second control drive current I42 based on the second reference voltage Vtf1 supplied from the second reference power supply 33-1 for adjusting the turn-off time (tf1). To do. Therefore, the second control drive current I42 is discharged to the (−) side power supply terminal 11b.

  When the electric charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged and the gate voltage Vg decreases and falls below the threshold voltage Vth, the power MOS 43 is turned off after a predetermined turn-off time tf. When the power MOS 43 is turned off, the drive current in the load circuit 60 is cut off and the operation stops.

Here, the variation of the power MOS 43 will be described.
Due to variations in the power MOS 43, the switching loss Sloss and the surge voltage Vdsg vary for each power module 10. Therefore, the first control drive current I41 is adjusted by the first reference voltage Vtr, and when the turn-on time tr of the power MOS 43 (that is, the fall time of the drain-source voltage Vds) is large, the first control drive current I41 is reduced and the turn-on time. If tr is small, increase it. Further, the second control drive current I42 is adjusted by the second reference voltage Vtf1, and when the turn-off time tf of the power MOS 43 (that is, the rise time of the drain-source voltage Vds) is large, the second control drive current I42 is decreased and the turn-on time tf. If is small, increase it. As described above, by setting the optimal first control drive current I41 and / or second control drive current I42 for each power module 10, it is possible to reduce variations in the switching loss Sloss and the surge voltage Vdsg.

Next, an operation when the drain current Id of the power MOS 43 is in an overcurrent state will be described.
For example, when the power MOS 43 is turned off with a larger current (overcurrent state) than usual when the power MOS 43 is short-circuited, a large surge voltage Vdsg is generated depending on the switching time at the time of turn-off. It may exceed. In order to solve such a conventional problem, the first embodiment operates as follows.

  When the drain current Id of the power MOS 43 is in an overcurrent state, this is detected by the overcurrent detection circuit 51 in the surge voltage suppression circuit 50, and an overcurrent detection signal S51 is output from the overcurrent detection circuit 51. Then, the second reference voltage Vtf1 supplied from the second reference power source 33-1 is lowered by the voltage adjusting circuit 52, and the second constant current circuit 30-1 is controlled by the third control smaller than the second control drive current I42. It operates so as to allow the drive current I43 to flow.

  When the first switch 41 is turned off and the second switch 42 is turned on by the H level of the gate pulse Pg, and the charge accumulated in the input capacitor Ciss of the power MOS 43 is discharged to the ground side, the accumulated charge is 2 flows through the second switch 42 and the second constant current circuit 30-1 to the (−) side power supply terminal 11b. At this time, the second constant current circuit 30-1 causes a third control drive current I43 smaller than the normal second control drive current I42 to flow to the (−) side power supply terminal 11b. Therefore, the falling time of the drain current Id when the power MOS 43 is turned off becomes gentle and the voltage change also becomes gentle, so that the surge voltage Vdsg is reduced.

(Effect of Example 1)
The power module 10 according to the first embodiment has the following effects (1) and (2).

  (1) Since the first constant current circuit 20 and the second constant current circuit 30-1 are provided, the first reference voltage Vtr and / or the second reference voltage Vtf1 is adjusted according to the variation of the power MOS 43, and the turn-on Initial variations in the maximum value MAX and / or the minimum value MIN of the time tr and / or the turn-off time tf are improved. Thereby, the power module 10 with little variation in the switching loss Sloss and the surge voltage Vdsg can be realized.

  (2) Since the surge voltage suppression circuit 50 is provided, when the drain current Id of the power MOS 43 is in an overcurrent state, a third control drive current smaller than the second control drive current I42 is generated from the gate of the power MOS 43. I43 is released, and the surge voltage Vdsg generated when the power MOS 43 is turned off is suppressed. Thereby, the power module 10 in which the surge voltage Vdsg generated when the power MOS 43 is turned off in the overcurrent state is reduced can be realized.

(Configuration of Example 2)
FIG. 2 is a schematic configuration diagram illustrating a power module according to the second embodiment of the present invention. Elements common to the elements in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  The power module 10A of the second embodiment has the same package 10a as that of the first embodiment. In the package 10a, the first constant current circuit 20, the second constant current circuit 30-1, and the first reference power supply 23 for adjusting the turn-on time (tr) as the reference voltage supply circuit and the turn-off time are the same as in the first embodiment. (Tf1) The second reference power source 33-1 for adjustment, the first and second switches 41 and 42, the power MOS 43, and the surge voltage suppression circuit 50A having a configuration different from that of the first embodiment are accommodated.

  The surge voltage suppression circuit 50A is connected between the drain side of the power MOS 43 and the output side of the second constant current circuit 30-1, and the overcurrent detection circuit 51 similar to the first embodiment and the first embodiment are configured. Selection circuit 53, third constant current circuit 30-2, third reference power supply 33-2 for adjusting a turn-off time (tf2) as a reference voltage supply circuit, and first and second switch elements 34-1, 34. -2.

  The first switch element 34-1 is connected between the output side of the second constant current circuit 30-1 and the (−) side power supply terminal 11b. The third constant current circuit 30-2 and the second switch element 34-2 are connected in series, and this series circuit is connected in parallel to the second constant current circuit 30-1 and the first switch element 34-1. Has been. The third constant current circuit 30-2 has a constant third control corresponding to the third reference voltage Vtf2 (<second reference voltage Vtf1) input from the third reference power supply 33-2 for adjusting the turn-off time (tf2). In this circuit, the drive current I43 (<second control drive current I42) is supplied to the ground side via the second switch element 34-2. The first and second switch elements 34-1 and 34-2 are composed of, for example, switching transistors.

  An overcurrent detection circuit 51 is connected between the (+) side output terminal 13 a and the drain side of the power MOS 43, and a selection circuit 53 is connected to the output side of the overcurrent detection circuit 51. The selection circuit 53 selects the first switch element 34-1 or the second switch element 34-2 based on the overcurrent detection signal S51 output from the overcurrent detection circuit 51, and shuts off the first switch element 34-1. This is a circuit for causing the second switch element 34-2 to conduct (that is, turn on) as well as causing (that is, turning off). That is, the selection circuit 53 turns on the first switch element 34-1 and turns off the second switch element 34-2 when the drain current Id flowing between the drain and source of the power MOS 43 is in the normal current state, and turns off the power. When the drain current Id flowing between the drain and source of the MOS 43 is in an overcurrent state, the first switch element 34-1 is turned off and the second switch element 34-2 is turned on.

  The selection circuit 53 and the first and second switch elements 34-1 and 34-2 constitute a selection unit. Other configurations are the same as those of the first embodiment.

3A is a circuit diagram showing a configuration example of the first constant current circuit 20 in FIG.
The first constant current circuit 20 includes a first stage first current mirror circuit 21 and a first error amplification circuit 22. The first current mirror circuit 21 is a circuit that flows a first control drive current I41 proportional to the first drive current I21a flowing to the input side to the output side. The first error amplifier circuit 22 detects the first drive current I21a flowing to the input side of the first current mirror circuit 21, generates a first drive voltage V22b corresponding to the first drive current I21a, and turns on the first drive voltage V22b. In this circuit, the first drive current I21a flowing on the input side of the first current mirror circuit 21 is changed in accordance with the first reference voltage Vtr input from the first reference power supply 23 for time (tr) adjustment.

  The first current mirror circuit 21 includes a pair of transistors (eg, P-channel MOSFETs, hereinafter referred to as “PMOS”) 21a and 21b having a transistor size of 1: x (eg, 1: 100). The pair of PMOSs 21a and 21b have their gates connected in common and their sources connected in parallel to the (+) side power supply terminal 11a. The drain of the PMOS 21a is connected to the gates of the PMOSs 21a and 21b.

  The first error amplification circuit 22 detects and responds to a transistor (for example, an N-channel MOSFET, hereinafter referred to as “NMOS”) 22a that changes the current value of the first drive current I21a and the first drive current I21a. And a resistor 22b for generating the first drive voltage V22b and an operational amplifier (hereinafter referred to as "op-amp") 22c. Between the drain of the PMOS 21a, the gates of the PMOS 21a and 21b, and the ground side, the drain / source of the NMOS 22a and the resistor 22b are connected in series. The source of the NMOS 22a is connected to the (−) side input terminal of the operational amplifier 22c, and the gate of the NMOS 22a is connected to the output terminal of the operational amplifier 22c. The operational amplifier 22c has a (+) side input terminal connected to the first reference power source 23, and a first drive voltage V22b input to the (−) side input terminal and a first reference input to the (+) side input terminal. It has a function of changing the first drive current I21a flowing through the NMOS 22a by following the voltage Vtr.

FIG. 3B is a circuit diagram showing a configuration example of the second and third constant current circuits 30-1 and 30-2 in FIG.
The third constant current circuit 30-2 in FIG. 2 has the same configuration as the second constant current circuit 30-1.

  The second constant current circuit 30-1 includes a second stage second current mirror circuit 31 and a second error amplification circuit 32. The second current mirror circuit 31 has a second control drive current I42 proportional to the second drive current I31a flowing on the input side (in the case of the third constant current circuit 30-2, proportional to the second drive current I31a flowing on the input side). The third control drive current I43) is sent to the output side. The second error amplifying circuit 32 detects the second driving current I31a flowing to the input side of the second current mirror circuit 31, and generates a second driving voltage V32b corresponding to the second driving current I31a. The second reference voltage Vtf1 input from the second reference power supply 33-1 (in the case of the third constant current circuit 30-2, the third reference voltage Vtf2 input from the third reference power supply 33-2) is followed. This circuit changes the second drive current I31a flowing to the input side of the second current mirror circuit 31.

  The second current mirror circuit 31 includes a pair of first-stage transistors (for example, PMOS) 31a and 31b having a transistor size of 1: 1 and a pair of second-stage transistors having a transistor size of 1: x (for example, 1: 100). Transistors (for example, NMOS) 31c and 31d.

  The PMOSs 31a and 31b on the front stage side have gates connected in common and their sources connected in parallel to the terminal on the power supply voltage VDD side. The drain of the PMOS 31a is connected to the gates of the PMOS 31a and 31b. The NMOSs 31c and 31d on the rear stage side are connected in common, and the gates are connected to the drain of the PMOS 31b and the drain of the NMOS 31c. The drain of the NMOS 31d is connected to the second switch 42 side terminal. Further, the sources of the NMOSs 31c and 31d are connected in parallel to the first switch element 34-1 side terminal (in the case of the third constant current circuit 30-2, the second switch element 34-2 side terminal). .

  The second error amplification circuit 32 detects a second drive current I31a by generating a transistor (for example, NMOS) 32a that changes the current value of the second drive current I31a and a second drive voltage V32b corresponding thereto. 32b and an operational amplifier 32c. Between the drain of the PMOS 31a and the gates of the PMOS 31a and 31b and the first switch element 34-1 side terminal (in the case of the third constant current circuit 30-2, the second switch element 34-2 side terminal), the NMOS 32a is connected. A drain / source and a resistor 32b are connected in series. The source of the NMOS 32a is connected to the (−) side input terminal of the operational amplifier 32c, and the gate of the NMOS 32a is connected to the output terminal of the operational amplifier 32c. The operational amplifier 32c has a (+) side input terminal connected to the second reference power source 33-1 (in the case of the third constant current circuit 30-2, the third reference power source 33-2) and a (−) side input terminal connected to the (−) side input terminal. The input second drive voltage V32b is made to follow the second reference voltage Vtf1 (in the case of the third constant current circuit 30-2, the third reference voltage Vtf2) input to the (+) side input terminal, and the NMOS 32a Has a function of changing the second drive current I31a flowing through the.

FIG. 3C is a circuit diagram showing a configuration example of the first and second switches 41 and 42 in FIG.
The first switch 41 and the second switch 42 are configured by complementary transistors (for example, CMOS transistors including a PMOS 41a and an NMOS 42a connected in series) that are complementarily turned on / off. The control terminal 12 is connected in common to the gates of the PMOS 41a and the NMOS 42a via the buffer 14. The drain of the PMOS 41 a and the drain of the NMOS 42 a are connected to each other, and this connection point is connected to the gate of the power MOS 43.

(Operation when drain current Id of power MOS 43 is in a normal state)
4 is a voltage / current waveform diagram showing the operation of the power module 10A of FIG.
4, the horizontal axis represents time t, and the vertical axis represents the voltage value of the source-drain voltage Vds waveform in the power MOS 43 and the current value of the drain current Id waveform in the power MOS 43.

  Since the electrical and thermal characteristics of the power MOS 43 vary depending on the element, for example, the minimum value tr_min of the turn-on time tr is 50 ns, the maximum value tr_max is 200 ns, and the standard value tr_typ is 100 ns. Similarly, the minimum value tf_min of the turn-off time tf is 50 ns, the maximum value tf_max is 200 ns, and the standard value tf_typ is 100 ns. The hatching region at the intersection of the falling of the drain-source voltage Vds and the rising of the drain current Id and the hatching region at the intersection of the rising of the drain-source voltage Vds and the falling of the drain current Id are on. This is a switching loss Sloss (= Vds × Id) that occurs at the time of switching off / off. When the drain-source voltage Vds rises, an overvoltage surge voltage Vdsg [= (Ld + Ls) × di / dt] may occur due to the influence of the parasitic inductances Ld and Ls.

  For example, when the turn-on time tr and the turn-off time tf are standard values tr_typ (= 50 ns) and tf_typ (= 50 ns) in the standard value of the power MOS 43, the operation is as follows.

  In the normal state where the drain current Id of the power MOS 43 is not an overcurrent state, the overcurrent detection signal S51 is not output from the overcurrent detection circuit 51, and therefore the first switch element 34-1 is turned on by the output signal of the selection circuit 53. Then, the second switch element 34-2 is turned off.

  When the gate pulse Pg applied to the control terminal 12 is at L level, it is driven by the buffer 14 in FIG. 3C and supplied to the gates of the PMOS 41a and NMOS 42a. Then, the PMOS 41a is turned on and the NMOS 42a is turned off.

  The operational amplifier 22c in the first constant current circuit 20 of FIG. 3A includes a first reference voltage Vtr supplied from a first reference power supply 23 for adjusting turn-on time (tr), and a first drive voltage V22b detected by a resistor 22b. And the gate of the NMOS 22a is controlled so that the error decreases (that is, the first drive voltage V22b follows the first reference voltage Vtr), and the (+) side power supply terminal 11a → The first drive current I21a flowing from the PMOS 21a → the NMOS 22a → the resistor 22b → the ground side is changed. The changed first drive current I21a is amplified, for example, 100 times by the first current mirror circuit 21 including a pair of PMOSs 21a and 21b, and the amplified first control drive current I41 is converted to the (+) side power supply terminal. 11a → source / drain of PMOS 21b → source / drain of PMOS 41a in FIG. 3C → gate of power MOS 43.

  When the first control drive current I41 flows to the gate of the power MOS 43, the first control drive current I41 is injected into the input capacitor Ciss of the power MOS 43, and the gate voltage Vg of the power MOS 43 rises. When the gate voltage Vg rises and exceeds the threshold voltage Vth of the power MOS 43, the power MOS 43 is turned on after a predetermined turn-on time (standard turn-on time tr_typ = 100 ns). When the power MOS 43 is turned on, a drive current flows from the drive power source 62 in the load circuit 60 to the load resistor 61 to the power MOS 43 to operate the load circuit 60.

  When the gate pulse Pg applied to the control terminal 12 becomes H level, it is driven by the buffer 14 in FIG. 3C, turning off the PMOS 41a and turning on the NMOS 42a.

  The operational amplifier 32c in the second constant current circuit 30-1 in FIG. 3B has the second reference voltage Vtf1 supplied from the second reference power supply 33-1 for adjusting the turn-off time (tf1) and the first reference voltage Vtf1 detected by the resistor 32b. The second drive voltage V32b is obtained, and the NMOS 32a is gated so that this error is reduced (that is, the second drive voltage V32b follows the second reference voltage Vtf1), and the power supply voltage VDD terminal The second drive current I31a flowing from the PMOS 31a, the NMOS 32a, the resistor 32b, the first switch element 34-1 to the (−) side power supply terminal 11b is changed.

  The changed second drive current I31a is converted to 1: 1 by the pair of preceding PMOSs 31a and 31b in the second current mirror circuit 31, and then amplified by, for example, 100 times by the pair of subsequent NMOSs 31c and 31d. The second control drive current I42 is changed from the gate of the power MOS 43 to the drain / source of the NMOS 42a in FIG. 3C → the drain / source of the NMOS 31d in the second constant current circuit 30-1 in FIG. 3B → the first switch element 34−. The charge flowing from the 1 → (−) side power supply terminal 11b and accumulated in the input capacitor Ciss of the power MOS 43 is discharged to the (−) side power supply terminal 11b.

  When the electric charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged and the gate voltage Vg drops below the threshold voltage Vth, the power MOS 43 has a predetermined turn-off time (standard turn-off time tf_typ = 100 ns). And turn off. When the power MOS 43 is turned off, the drive current in the load circuit 60 is cut off and the operation stops.

Next, variations in the power MOS 43 will be described.
Due to variations in the power MOS 43, the switching loss Sloss (= Vds × Id) and the surge voltage Vdsg [= (Ld + Ls) × di / dt)] vary for each power module 10A. Therefore, when the first control drive current I41 is adjusted by the first reference voltage Vtr, and the turn-on time tr of the power MOS 43 (that is, the fall time of the drain-source voltage Vds) is large as shown in FIG. If the turn-on time tr is small, increase it. Further, the second control drive current I42 is adjusted by the second reference voltage Vtf1, and when the turn-off time tf of the power MOS 43 (that is, the rise time of the drain-source voltage Vds) is large, the second control drive current I42 is decreased and the turn-on time tf. If is small, increase it.

  As described above, by setting the optimal first control drive current I41 and / or second control drive current I42 for each power module 10A, it is possible to reduce variations in the switching loss Sloss and the surge voltage Vdsg.

(Operation when drain current Id of power MOS 43 is in an overcurrent state)
FIG. 5 is a voltage / current waveform diagram showing details of the short-circuit fault turn-off in FIG.

  In FIG. 5, the horizontal axis represents time t, and the vertical axis represents voltage value and current value. In this voltage / current waveform diagram, for example, the time t of one division (div) is 200 ns, the voltage of one division (div) is 100 V / div, and the current of one division (div) is 20 A / div. As the waveform measurement conditions, the drain-source voltage Vds of the power MOS 43 is 400 V, and the power MOS temperature (Tg) is 125 ° C.

  When the power MOS 43 is turned off at the time of a short circuit failure, the surge voltage Vdsg rises greatly (for example, 100 V or less), and the drain current Id suddenly falls and is turned off (for example, within 2 μs). VdsSF is an overshoot surge voltage reduced by the surge voltage suppression action of the second embodiment (for example, about 30 to 50 V), and IdSF falls off slowly by the surge voltage suppression action of the second embodiment. This is the drain current.

  For example, when the power MOS 43 is turned off with a larger current (overcurrent state) than usual when the power MOS 43 is short-circuited, a large surge voltage Vdsg is generated depending on the switching time (di / dt) at the time of turn-off. The breakdown voltage of the power MOS 43 may be exceeded. In order to solve such a conventional problem, the second embodiment operates as follows.

  When the drain current Id of the power MOS 43 is in an overcurrent state, this is detected by the overcurrent detection circuit 51, and an overcurrent detection signal S51 is output from the overcurrent detection circuit 51. Then, the selection circuit 53 switches the first switch element 34-1 to the off state and switches the second switch element 34-2 to the on state.

  When the NMOS 42a in FIG. 3C is turned on by the H level of the gate pulse Pg and the charge accumulated in the input capacitor Ciss of the power MOS 43 is discharged to the ground side, the accumulated charge is converted into the third constant current circuit 30-2. And flows through the second switch element 34-2 to the (−) side power supply terminal 11b. At this time, in the third constant current circuit 30-2, the third reference voltage Vtf2 (<second reference voltage Vtf1) supplied from the third reference power supply 33-2 for adjusting the turn-off time (tf2) is used. The third control drive current I43 smaller than the 2 control drive current I42 is changed from the input capacitance Ciss of the power MOS 43 → the NMOS 42a → the third constant current circuit 30-2 → the second switch element 34-2 → the (−) side power supply terminal 11b, To flow.

  Therefore, the fall time (di / dt) of the drain current Id when the power MOS 43 is turned off becomes gentle (current waveform IdSF), and the voltage change (dv / dt) also becomes gentle, so that the surge voltage Vdsg has a waveform. It is reduced like VdsSF.

(Effect of Example 2)
The power module 10A according to the second embodiment has the following effects (i) to (iii).

  (I) Since the first constant current circuit 20 and the second constant current circuit 30-1 are included, the first reference voltage Vtr and / or the second reference is determined according to the variation of the power MOS 43, as in the first embodiment. The voltage Vtf1 is adjusted to improve the initial variation in the maximum value MAX and / or the minimum value MIN of the turn-on time tr and / or the turn-off time tf. Thereby, the power module 10A with little variation in the switching loss Sloss and the surge voltage Vdsg can be realized.

  (Ii) Since the surge voltage suppression circuit 50A is provided, when the drain current Id of the power MOS 43 is in an overcurrent state, a third control drive current smaller than the second control drive current I42 is generated from the gate of the power MOS 43. I43 is released, and the surge voltage Vdsg generated when the power MOS 43 is turned off is suppressed. Thereby, the power module 10A in which the surge voltage Vdsg generated when the power MOS 43 is turned off in the overcurrent state is reduced can be realized.

  (Iii) When the first, second, and third constant current circuits 20, 30-1, and 30-2 are configured by, for example, current mirror circuits 21 and 31 and error amplification circuits 22 and 32, their current mirrors. By making the circuits 21 and 31 multistage, an increase in current amplification factor and stability of characteristics can be realized.

(Configuration / Operation)
6A and 6B are circuit diagrams showing a configuration example of the reference voltage supply circuit according to the third embodiment of the present invention.

  In the second embodiment, the reference voltage supply circuit includes a first reference power source 23 for adjusting the turn-on time (tr), and second and third reference power sources 33-1 and 33-2 for adjusting the turn-off time (tf1, tf2). It consists of

  On the other hand, the reference voltage supply circuit 23B shown in FIG. 6A of the third embodiment is constituted by two fixed resistors 23a for voltage division and a variable resistor 23b. The two fixed resistors 23a and 23b for voltage division are connected in series between the power supply voltage VDD terminal and the ground side, and the first reference voltage Vtr is determined from the connection point of the fixed resistor 23a and the variable resistor 23b. Is output. The first reference voltage Vtr can be adjusted by changing the resistance value of the variable resistor 23b.

  Similarly, in the reference voltage supply circuits 33-1B and 33-2B shown in FIG. 6B of the third embodiment, each of the voltage dividing circuits is composed of two fixed resistors 33a and a variable resistor 33b. The two fixed resistors 33a and 33b for voltage division are connected in series between the power supply voltage VDD terminal and the ground side, and the second and third reference points are connected from the connection point of the fixed resistor 33a and the variable resistor 33b. Voltages Vtf1 and Vtf2 are output, respectively. The second and third reference voltages Vtf1 and Vtf2 can be adjusted by changing the resistance value of the variable resistor 33b.

(effect)
According to the third embodiment, since the first, second, and third reference voltages Vtr, Vtf1, and Vtf2 are generated by the voltage dividing resistors 23a, 23b, 33a, and 33b, an external circuit of the power module 10A is provided. Easy to do.

  FIG. 7 is an equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element in Embodiment 4 of the present invention.

  The IGBT 56 of the fourth embodiment has three electrodes of an emitter E, a collector C, and a gate G, and has substantially the same function and effect as the power MOS 43 of the first to third embodiments.

  In addition, as a power semiconductor element, you may use other power transistors, such as a gallium nitride (GaN) power device and a silicon carbide (SiC) power device.

(Other variations of Examples 1 to 4)
The present invention is not limited to the first to fourth embodiments described above, and other usage forms and modifications are possible. For example, the following forms (a) to (d) are used as the usage form and the modified examples.

  (A) In the power module 10A of FIG. 2, the second reference voltage Vtf1 for setting the discharge current in the normal state and the third reference voltage Vtf2 for setting the discharge current in the overcurrent state are individually However, the present invention is not limited to this. For example, the ratio of the second reference voltage Vtf1 / third reference voltage Vtf2 can be set to a predetermined value. In this case, when one of the second reference voltage Vtf1 and the third reference voltage Vtf2 is determined, the other voltage is automatically determined. Further, the second constant current circuit 30-1 and the third constant current circuit 30-2 may be configured by one common constant current circuit as in the first embodiment.

  (B) The first, second and third constant current circuits 20, 30-1 and 30-2 are other than the first and second current mirror circuits 21 and 31 and the first and second error amplification circuits 22 and 32. You may comprise with another circuit.

  (C) The first and second switches 41 and 42 may be configured using a semiconductor element other than the CMOS transistor including the PMOS 41a and the NMOS 42a.

  (D) The overcurrent detection circuit 51 may be configured using a resistor between the source side of the power MOS 43 and the (−) side output terminal 13b, or may be configured using a current transformer. Further, the power MOS 43 may be configured as a MOS with a current sensing function.

10, 10A power module 10a package 20, 30-1, 30-2 first, second, third constant current circuit 21, 31 first, second current mirror circuit 22, 32 first, second error amplification circuit 23 , 33-1 and 33-2 First, second and third reference power supplies 23B, 33-1B and 33-2B Reference voltage supply circuit 23a and 33a Voltage dividing fixed resistor 23b and 33b Voltage dividing variable resistor 34-1 and 34 -2 First and second switch elements 41 and 42 First and second switches 41a PMOS
42a NMOS
43 Power MOS
50, 50 A Surge voltage suppression circuit 51 Overcurrent detection circuit 52 Voltage adjustment circuit 53 Selection circuit 60 Load circuit

Claims (11)

A first electrode; a second electrode; and a control electrode that performs on / off operation between the first electrode and the second electrode when a control voltage is applied, and includes a parasitic capacitance generated in the control electrode. A power semiconductor device that is turned on when a first control drive current is injected into an input capacitor, and that is turned off when a charge stored in the input capacitor is discharged and a second control drive current is discharged;
A first constant current circuit for supplying a constant first control drive current corresponding to the input first reference voltage;
A first switch that is turned on / off by a drive signal and injects the first control drive current into the input capacitor when the drive signal is on;
A second constant current circuit for supplying a constant second control drive current corresponding to the input second reference voltage;
A second switch that is turned off when the first switch is turned on by the drive signal, and turned on when the first switch is turned off, and discharges the second control drive current to the ground side; ,
An overcurrent state of a conduction current flowing between the first electrode and the second electrode of the power semiconductor element is detected, and the second reference voltage and the second control drive current are changed based on the overcurrent detection result. A surge voltage suppressing circuit for suppressing a surge voltage generated at the time of turning off the power semiconductor element;
A power module comprising: The surge voltage suppression circuit is
An overcurrent detection circuit for detecting an overcurrent state of the conduction current and outputting the overcurrent detection result;
A voltage adjustment circuit that adjusts the second reference voltage to change the second control drive current based on the overcurrent detection result;
The power module according to claim 1, comprising: The surge voltage suppression circuit is
A third reference voltage smaller than the second reference voltage is input, and a constant third control drive current smaller than the second control drive current corresponding to the third reference voltage is supplied from the input capacitance to the first reference voltage. A third constant current circuit for discharging to the ground side through two switches;
When detecting an overcurrent state of the conduction current, an overcurrent detection circuit that outputs the overcurrent detection result;
When the overcurrent detection result is input, selection means for selecting and operating the third constant current circuit instead of the second constant current circuit;
The power module according to claim 1, comprising: The power module according to claim 3, further comprising:
A power module comprising a reference voltage supply circuit for supplying the first reference voltage, the second reference voltage, and the third reference voltage. The reference voltage supply circuit includes:
The reference power source is configured to output the first reference voltage, the second reference voltage, and the third reference voltage, respectively.
The power module according to claim 4. The reference voltage supply circuit includes:
A voltage dividing resistor configured to divide a power supply voltage and output the first reference voltage, the second reference voltage, and the third reference voltage, respectively;
The power module according to claim 4. The first constant current circuit includes:
A first stage or a plurality of stages of first current mirror circuits for passing the first control drive current proportional to the first drive current;
A first error amplifying circuit that detects the first drive current, generates a first drive voltage corresponding to the first drive current, and changes the first drive current by causing the first drive voltage to follow the first reference voltage; ,
Have
The second constant current circuit includes:
A one-stage or multiple-stage second current mirror circuit for flowing the second control drive current proportional to the second drive current;
A second error amplification circuit that detects the second drive current, generates a second drive voltage corresponding thereto, and changes the second drive current by causing the second drive voltage to follow the second reference voltage; ,
Have
The third constant current circuit includes:
One or more stages of third current mirror circuits for passing the third control drive current proportional to the third drive current;
A third error amplifying circuit that detects the third drive current, generates a third drive voltage corresponding to the third drive current, and changes the third drive current by causing the third drive voltage to follow the third reference voltage; ,
Having
The power module according to claim 3, wherein the power module is a power module. The selection means includes
A first switch element for conducting / cutting off an output current of the second constant current circuit;
A second switch element for conducting / cutting off an output current of the third constant current circuit;
A selection circuit that selects the first switch element or the second switch element based on the overcurrent detection result, interrupts the first switch element, and makes the second switch element conductive;
The power module according to any one of claims 3 to 7, wherein The first switch and the second switch are:
The power module according to any one of claims 1 to 8, wherein the power module is configured by a complementary transistor that is complementarily turned on / off by the drive signal. The power semiconductor element is
The power module according to claim 1, which is a power transistor including a power MOSFET, IGBT, GaN power device, or SiC power device. The power module according to any one of claims 1 to 10,
A power module that is housed in a package.

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