JP6706876B2 - Power module - Google Patents

Description

The present invention relates to a power module in which a power element and the like are contained in one package.

Examples of the power semiconductor element that constitutes the power module include, for example, a power MOSFET (hereinafter simply referred to as “power MOS”), an insulation control type bipolar transistor (hereinafter referred to as “IGBT”), a gallium nitride (GaN) power device, and a carbonization device. Power transistors such as silicon (SiC) power devices are known.

Patent Document 1 describes a technique of a semiconductor device with a current detection function, which is capable of accurately detecting a current flowing in an inductive load in a semiconductor device that uses an IGBT to drive and control an inductive load such as an AC motor. ing.
In Patent Document 2, in a drive circuit as a power module using, for example, an IGBT as an insulated gate switching element, a constant current source using a current mirror, a switching circuit, and a current mode selection circuit in order to reduce current consumption. The technology of a drive circuit having a is described.

In Patent Document 3, an input DC voltage is converted into an AC voltage by a MOSFET that is a power MOS on the primary side and an insulation transformer, and then converted to a DC voltage by a synchronous rectification MOSFET and a reflux MOSFET on the secondary side. An insulated direct current/direct current (DC/DC) converter for converting and outputting is described. In this DC/DC converter, when the operation is stopped, in order to prevent an overvoltage that occurs in the secondary side synchronous rectification MOSFET and the freewheeling MOSFET when the operation is stopped, the controller causes the synchronous rectification MOSFET The freewheeling MOSFET is stopped by the soft stop operation.

FIG. 8 is an equivalent circuit diagram showing an outline of a conventional N-channel type power MOS.
The N-channel power MOS 1 has three electrodes of a gate G, a drain D and a source S. For example, a load resistance Rl on the load circuit 6 side and a power supply E that outputs a power supply voltage Vdd are connected in series to the drain/source of the N-channel power MOS 1. In this N-channel power MOS 1, when the gate voltage Vg applied to the gate G rises and exceeds the threshold voltage Vth, the drain-source turns on, and when the gate voltage Vg falls and falls below the threshold voltage Vth, The drain-source turns off.

The gate G, the drain D, and the source S have parasitic capacitance and parasitic inductance. For example, a parasitic capacitance Cgd exists between the gate and the drain, a parasitic capacitance Cgs exists between the gate and the source, and a parasitic capacitance Cds exists between the drain and the source. Further, the parasitic inductance Ld exists on the drain D side and the parasitic inductance Ls exists on the source S side.

The parasitic capacitance Cgd between the gate and the drain has a great influence on the switching characteristics. When the drain-source voltage Vds becomes equal to or lower than the gate-source voltage Vgs, the parasitic capacitance Cgd between the gate and the drain sharply increases, for example, about 10 times. A relational expression such as the following expression (1) is established for each capacitance of the power MOS 1.
Input capacitance Ciss≈Cgd+Cgs
Feedback capacitance Crss≈Cgd
Output capacitance Coss≈Cgd+Cds... (1)

Since the power MOS 1 is a voltage-controlled element, it does not require a drive current when holding the on state or the off state, but when performing a switching operation, the charge/discharge current with respect to the input capacitance Ciss is changed each time. Flowing.

FIG. 9 is a switching operation waveform diagram of the power MOS 1 with respect to the load resistance Rl of FIG.

In the power MOS 1 of FIG. 8, when the drain-source voltage Vds falls from a high (hereinafter “H”) level to a low (hereinafter “L”) level (that is, the drain current Id changes from L level to H level). When the drain-source voltage Vds rises from the L level to the H level (that is, when the drain current Id falls from the H level to the L level), it turns on.

Here, the turn-on time tr is the time between the time 90% from the start of the fall and the time 10% before the end of the fall in the falling waveform of the drain-source voltage Vds. Furthermore, the turn-off time tf is the time between the time of 10% from the start of rising and the time of 90% before the end of rising in the rising waveform of the drain-source voltage Vds.

The hatching area at the intersection of the fall of the drain-source voltage Vds and the rise of the drain current Id and the hatching area of the intersection of the rise of the drain-source voltage Vds and the fall of the drain current Id are on. It is a switching loss Sloss (=Vds×Id) that occurs when switching on/off. At the rise of the drain-source voltage Vds, an overvoltage surge voltage Vdsg [=(Ld+Ls)×di/dt, where di/dt is a switching time] may occur due to the influence of the parasitic inductances Ld and Ls.

FIG. 10 is a data sheet showing an example of the electrical/thermal characteristics (case temperature Tc=25° C.) of the power MOS 1 of FIG. The case temperature Tc is the temperature of the case that is the package that houses the power MOS 1.

In FIG. 10, when the drain current Id=25 A and the gate-source voltage Vgs=10 V, the drain-source on-resistance Ron has a standard value TYP=6.9 mΩ and a maximum value MAX=8.7 mΩ. is there. When the drain current Id=1 mA and the drain-source voltage Vds=10 V, the gate threshold voltage Vth has a minimum value MIN=2.0 V, a standard value TYP=3.0 V, and a maximum value MAX=4.0 V as standard values. Is.

When the drain-source voltage Vds=25 V, the gate-source voltage Vgs=0 V, and the operating frequency f=1 MHz, the input capacitance Ciss is the standard value TYP=5880 pF as the standard value, and the feedback capacitance Crss is the standard value. Is a standard value TYP=250 pF, and the output capacitance Coss is a standard value TYP=530 pF.

Further, drain current Id=25 A, load resistance Rl=2 Ω, power supply voltage Vdd=50 V, gate resistance Rg=0 Ω, (+) side gate-source voltage Vgs(+)=10 V, and (−) side gate-source When the inter-electrode voltage Vgs(−)=0 V, the turn-on time tr is the standard value TYP=28 ns as the standard value, and the turn-off time tf is the standard value TYP=49 ns as the standard value.

JP, 2003-299363, A International publication WO2012-153459 JP, 2015-43652, A

The conventional power module using the power semiconductor element such as the power MOS 1 has the following problems (A) and (B).

(A) In the data sheet of FIG. 10 showing the electrical/thermal characteristics of the power MOS 1, only the standard value TYP is defined as the standard value of the turn-on time tr and the turn-off time tf (for example, the standard of the turn-on time tr) Since the value TYP is 28 ns, the standard value TYP of the turn-off time tf is 49 ns, and there is no standard value MAX/minimum value MIN in the device design, the worst (worst) design of the power module cannot be performed. That is, in the switching operation waveform of FIG. 9, the worst values of the switching loss Sloss (=Vds×Id) and the surge voltage Vdsg [=(Ld+Ls)×di/dt] are unknown.

Even if the maximum value MAX/minimum value MIN of the turn-on time tr/turn-off time tf can be standardized, the standard value TYP (for example, tr=28 ns, tf= 49 ns), the maximum value MAX/minimum value MIN is in the range of -50%/+100%. If the value is used as it is in the design of the power module, the worst value of the switching loss Sloss will be twice the standard value TYP, and the heat dissipation design must also be doubled. Regarding the minimum value MIN of the turn-on time tr/turn-off time tf, the surge voltage Vdsg generated by the parasitic inductances Ld and Ls is double the standard value TYP, so that the voltage rating of the power MOS1 is exceeded and electromagnetic interference noise is generated. (Electro-Magnetic Interference noise; EMI noise) is a concern.

(B) When the power MOS1 is turned off by a current in an overcurrent state larger than normal, a large surge voltage Vdsg is generated due to the short switching time (di/dt) when the power MOS is off, and in some cases the power MOS1 There is a problem of exceeding the withstand voltage. However, Patent Document 3 neither discloses nor suggests such a problem.

The power module of the present invention includes a power semiconductor element, a first constant current circuit, a first switch, a second constant current circuit, and a second switch.

Here, the power semiconductor element includes a first electrode, a second electrode, and a control electrode that is turned on/off between the first electrode and the second electrode when a control voltage is applied, When the first control driving current is injected into the input capacitance formed of the parasitic capacitance generated in the control electrode, the first electrode and the second electrode are turned on, and the accumulated charge of the input capacitance is discharged to drive the second control drive. A switching element that turns off between the first electrode and the second electrode when a current is discharged. The first constant current circuit is a circuit to which a first reference voltage is input and which causes the constant first control drive current corresponding to the first reference voltage to flow. The first switch is a switch that is turned on/off by a drive signal and injects the first control drive current into the input capacitance when in the on state.

The second constant current circuit is a circuit to which a second reference voltage is input and which causes the constant second control drive current corresponding to the second reference voltage to flow. The second switch is turned off by the drive signal when the first switch is in the on state, and is turned on when the first switch is in the off state, and the second control drive current is moved to the ground side. It is a switch to release. Then, the first reference voltage and/or the second reference voltage is adjusted according to the variation of the power semiconductor element.
Furthermore, in the present invention, the overcurrent state of the conduction current flowing between the first electrode and the second electrode of the power semiconductor element is detected, and the second reference voltage and the second current are detected based on the overcurrent detection result. It is characterized in that a surge voltage suppressing circuit for suppressing a surge voltage generated when the power semiconductor element is turned off is provided by changing the control drive current .

The surge voltage suppression circuit, for example, detects an overcurrent state of the conduction current and outputs the overcurrent detection result, and adjusts the second reference voltage based on the overcurrent detection result. And a voltage adjusting circuit for changing the second control drive current.

Further, the surge voltage suppression circuit inputs, for example, a third reference voltage smaller than the second reference voltage, and corresponds to the third reference voltage and has a constant third smaller than the second control drive current. A third constant current circuit that discharges a control drive current from the input capacitance to the ground side through the second switch, and an overcurrent detection circuit that outputs the overcurrent detection result when an overcurrent state of the conduction current is detected. And a selecting means for selecting and operating the third constant current circuit instead of the second constant current circuit when the result of the overcurrent detection is input.

For example, the power module further includes a reference voltage supply circuit that supplies the first reference voltage, the second reference voltage, and the third reference voltage.
The reference voltage supply circuit includes, for example, a reference power source that outputs the first reference voltage, the second reference voltage, and the third reference voltage, respectively.

Further, the reference voltage supply circuit is configured by, for example, a voltage dividing resistor that divides a power supply voltage and outputs the first reference voltage, the second reference voltage, and the third reference voltage, respectively.

The first constant current circuit detects, for example, one stage or a plurality of stages of first current mirror circuits that flow the first control drive current proportional to the first drive current, and detects the first drive current and responds thereto. A first error amplification circuit that changes the first drive current by causing the first drive voltage to follow the first reference voltage. The second constant current circuit detects, for example, one stage or a plurality of stages of second current mirror circuits for flowing the second control drive current proportional to the second drive current, and detects the second drive current and responds thereto. And a second error amplifier circuit that changes the second drive current by causing the second drive voltage to follow the second reference voltage. Further, the third constant current circuit detects, for example, one or a plurality of stages of third current mirror circuits for flowing the third control drive current proportional to the third drive current and the third drive current. And a third error amplification circuit that changes the third drive current by causing the third drive voltage to follow the third reference voltage.

The power module is housed in a package, for example.

The power module of the present invention has the following effects (a) to (c).

(A) Since the first constant current circuit and the second constant current circuit are provided and the first reference voltage and/or the second reference voltage is adjusted according to the variation of the power semiconductor element , the turn-on time and The variation of the maximum value and/or the minimum value of the turn-off time can be improved. As a result, it is possible to realize a power module with less variation in switching loss and surge voltage.

(B) Since the power semiconductor device has the surge voltage suppressor circuit, the second control drive current changes when the conduction current of the power semiconductor device is in the overcurrent state, and the surge voltage generated when the power semiconductor device is turned off is suppressed. To be done. As a result, it is possible to realize a power module in which the surge voltage generated when the power semiconductor element is turned off in the overcurrent state is reduced.

(C) When the first constant current circuit, the second constant current circuit, and the third constant current circuit are composed of, for example, a current mirror circuit and an error amplifier circuit, the current mirror circuit is provided in multiple stages to reduce the current amplification factor. Increase and stability of characteristics can be realized.

1 is a schematic configuration diagram showing a power module according to a first embodiment of the present invention. Example 2 Schematic configuration diagram showing a power module in Example 2 of the present invention Circuit diagram showing a configuration example of the first constant current circuit in FIG. A circuit diagram showing a configuration example of the second and third constant current circuits in FIG. Circuit diagram showing a configuration example of the first and second switches in FIG. Voltage/current waveform diagram showing the operation of the power module in Fig. 2. Voltage/current waveform diagram showing details of short-circuit fault turn-off in Fig. 4 Circuit diagram showing a configuration example of a reference voltage supply circuit in Example 3 of the present invention Equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element in Example 4 of the present invention Equivalent circuit diagram showing the outline of a conventional N-channel power MOS Waveform diagram of the switching operation of the power MOS1 with respect to the load resistance Rl in FIG. Data sheet showing an example of electrical/thermal characteristics (case temperature Tc=25° C.) of the power MOS 1 of FIG.

Modes for carrying out the present invention will become apparent when the following description of the preferred embodiments is read in view of the accompanying drawings. However, the drawings are for the purpose of explanation only, and do not limit the scope of the present invention.

(Structure of Example 1)
1 is a schematic configuration diagram showing a power module according to a first embodiment of the present invention.
The power supply for gate drive 55 is connected to the input side of the power module 10, and the load circuit 60 is connected to the output side of the power module 10.

The power module 10 has a package 10a that houses a power semiconductor element and the like. The package 10a is made of resin or ceramics having high heat resistance and high insulation properties. In this package 10a, a (+) side power supply terminal 11a for inputting a DC power supply voltage VDD, a (−) side power supply terminal 11b for grounding, a control terminal 12 for inputting a drive signal (for example, a gate pulse) Pg, ( A (+) side output terminal 13a and a (-) side output terminal 13b on the ground side are provided.

In the package 10a, a first constant current circuit 20, a second constant current circuit 30-1, a first reference power supply 23 for adjusting a turn-on time (tr) as a reference voltage supply circuit, and a turn-off time (tf1) adjustment. The second reference power supply 33-1 for use, the first and second switches 41 and 42, the power semiconductor element (for example, N-channel type power MOS) 43, and the surge voltage suppression circuit 50 are housed.

The first constant current circuit 20, the first and second switches 41 and 42, and the second constant current circuit 30-1 are connected in series between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. Has been done. A gate as a control electrode of the power MOS 43 is connected to a connection point between the first switch 41 and the second switch 42. The drain as the first electrode of the power MOS 43 is connected to the (+) side output terminal 13a, and the source as the second electrode of the power MOS 43 is connected to the (-) side output terminal 13b.

The first constant current circuit 20 is a circuit for flowing a constant first control drive current I41 corresponding to the first reference voltage Vtr input from the first reference power supply 23 for turn-on time (tr) adjustment to the first switch 41 side. Is. The second constant current circuit 30-1 includes a constant second control drive current I42 or a third control drive corresponding to the second reference voltage Vtf1 input from the second reference power supply 33-1 for adjusting the turn-off time (tf1). It is a circuit that allows a current I43 (<I42) to flow to the ground side.

The first switch 41 is turned on/off by the gate pulse Pg input from the control terminal 12 (for example, turned on by the L level of the gate pulse Pg and turned off by the H level), and when the on state is set, the first switch 41 The first control drive current I41 from the first constant current circuit 20 is injected through the gate of the power MOS 43 into the input capacitance Ciss which is its parasitic capacitance. The second switch 42 is turned off by the gate pulse Pg input from the control terminal 12 when the first switch 41 is on (for example, turned off by the L level of the gate pulse Pg), and the first switch 41 is turned on. When in the off state, it is turned on (for example, turned on by the H level of the gate pulse Pg), and the second control drive current I42 or the third control drive current I43 from the gate of the power MOS 43 is transferred to the second constant current circuit 30-. It is released to the 1 side.

The power MOS 43 is turned on when the first control drive current I41 is injected into the input capacitance Ciss generated at the gate and the gate voltage Vg as a control voltage applied to the input capacitance Ciss rises and exceeds the threshold voltage Vth, and the input capacitance Ciss is turned on. It is a switching element that is turned off when the accumulated charge of Ciss is discharged and the second control drive current I42 or the third control drive current I43 is discharged, and the gate voltage Vg applied to the input capacitance Ciss decreases and falls below the threshold voltage Vth. ..

The surge voltage suppression circuit 50 is connected to the drain side of the power MOS 43 and the second reference power supply 33-1 side. The surge voltage suppression circuit 50 detects an overcurrent state of a conduction current (for example, drain current Id) flowing between the drain and source of the power MOS 43, and based on the overcurrent detection result, the second reference voltage Vtf1 and the second control. It is a circuit that changes the drive current I42 to suppress the surge voltage generated when the power MOS 43 is turned off.

The surge voltage suppression circuit 50 includes, for example, an overcurrent detection circuit 51 connected between the (+) side output terminal 13a and the drain side of the power MOS 43, the overcurrent detection circuit 51, and the second reference power supply 33-1. And a voltage adjusting circuit 52 connected between the side and the side. The overcurrent detection circuit 51 is a circuit that detects an overcurrent state of the drain current Id in the power MOS 43 and outputs an overcurrent detection signal S51 as an overcurrent detection result to the voltage adjustment circuit 52. The voltage adjustment circuit 52 adjusts the second reference voltage Vtf1 of the second reference power supply 33-1 based on the overcurrent detection signal S51 to change the second control drive current I42 to the third control drive current I43 (<I42). It is a circuit that changes.

A gate drive power supply 50 for applying a power supply voltage VDD is connected between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. Further, a load circuit 60 is connected to the (+) side output terminal 13a and the (−) side output terminal 13b. The load circuit 60 has, for example, a load resistor 61 and a DC drive power source 62, which are connected in series between the (+) side output terminal 13a and the (−) side output terminal 13b.

(Operation of Example 1)
In a normal state where the drain current Id of the power MOS 43 is not in the overcurrent state, the overcurrent detection signal S51 is not output from the overcurrent detection circuit 51 in the surge voltage suppression circuit 50, so the surge voltage suppression circuit 50 does not operate. When the gate pulse Pg applied to the control terminal 12 is at L level, the first switch 41 is turned on and the second switch 42 is turned off. The first constant current circuit 20 operates to flow a constant first control drive current I41 based on the first reference voltage Vtr supplied from the first reference power supply 23 for adjusting the turn-on time (tr). The first control drive current I41 flows to the gate of the power MOS 43 through the first switch 41.

When the first control drive current I41 flows into the gate of the power MOS 43, the first control drive current I41 is injected into the input capacitance Ciss of the power MOS 43, and the gate voltage Vg of the power MOS 43 rises. When the gate voltage Vg rises and exceeds the threshold voltage Vth of the power MOS 43, the power MOS 43 turns on after a predetermined turn-on time tr. When the power MOS 43 is turned on, a drive current flows in the drive power supply 62 →load resistance 61 →power MOS 43 in the load circuit 60, and the load circuit 60 operates.

When the gate pulse Pg applied to the control terminal 12 becomes H level, the first switch 41 is turned off and the second switch 42 is turned on. Then, the charge accumulated in the input capacitance Ciss of the power MOS 43 flows to the second constant current circuit 30-1 through the second switch 42. The second constant current circuit 30-1 operates to flow a constant second control drive current I42 based on the second reference voltage Vtf1 supplied from the second reference power supply 33-1 for adjusting the turn-off time (tf1). To do. Therefore, the second control drive current I42 is discharged to the (−) side power supply terminal 11b.

When the charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged and the gate voltage Vg drops and falls below the threshold voltage Vth, the power MOS 43 turns off after a predetermined turn-off time tf. When the power MOS 43 is turned off, the drive current in the load circuit 60 is cut off and the operation is stopped.

Here, the variation of the power MOS 43 will be described.
Due to the variation of the power MOS 43, the switching loss Sloss and the surge voltage Vdsg vary for each power module 10. Therefore, the first control drive current I41 is adjusted by the first reference voltage Vtr, and when the turn-on time tr of the power MOS 43 (that is, the fall time of the drain-source voltage Vds) is large, the first control drive current I41 is made small, and the turn-on time is reduced. If tr is small, increase it. Further, the second control drive current I42 is adjusted by the second reference voltage Vtf1, and when the turn-off time tf of the power MOS 43 (that is, the rise time of the drain-source voltage Vds) is long, the second control drive current I42 is made small, and the turn-on time tf is reduced. If is small, increase it. As described above, by setting the optimum first control drive current I41 and/or second control drive current I42 for each power module 10, it is possible to reduce variations in the switching loss Sloss and the surge voltage Vdsg.

Next, the operation when the drain current Id of the power MOS 43 is in the overcurrent state will be described.
For example, when the power MOS 43 is turned off at a current (overcurrent state) larger than usual when the power MOS 43 has a short circuit failure, a large surge voltage Vdsg is generated due to the switching time at the time of turn-off, and the withstand voltage of the power MOS 43 may be increased in some cases. It may exceed. In order to solve such a conventional problem, the first embodiment operates as follows.

When the drain current Id of the power MOS 43 is in the overcurrent state, this is detected by the overcurrent detection circuit 51 in the surge voltage suppression circuit 50, and the overcurrent detection signal S51 is output from the overcurrent detection circuit 51. Then, the voltage adjustment circuit 52 lowers the second reference voltage Vtf1 supplied from the second reference power supply 33-1, and the second constant current circuit 30-1 causes the third control that is smaller than the second control drive current I42. It operates so as to pass the drive current I43.

When the first switch 41 is turned off and the second switch 42 is turned on by the H level of the gate pulse Pg, and the charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged to the ground side, the accumulated charge is It flows through the 2 switch 42 and the 2nd constant current circuit 30-1 to the (-) side power supply terminal 11b. At this time, the second constant current circuit 30-1 causes the third control drive current I43 smaller than the normal second control drive current I42 to flow to the (−) side power supply terminal 11b. Therefore, the fall time of the drain current Id when the power MOS 43 is turned off becomes gradual, and the voltage change also becomes gradual, so that the surge voltage Vdsg is reduced.

(Effect of Example 1)
The power module 10 according to the first embodiment has the following effects (1) and (2).

(1) It has a first constant current circuit 20 and a second constant current circuit 30-1, and is configured to adjust the first reference voltage Vtr and/or the second reference voltage Vtf1 according to variations in the power MOS 43 . Therefore, the initial variation in the maximum value MAX and/or the minimum value MIN of the turn-on time tr and/or the turn-off time tf is improved. As a result, it is possible to realize the power module 10 in which variations in the switching loss Sloss and the surge voltage Vdsg are small.

(2) Since the surge voltage suppressor circuit 50 is included, when the drain current Id of the power MOS 43 is in the overcurrent state, the third control drive current smaller than the second control drive current I42 is output from the gate of the power MOS 43. I43 is released, and the surge voltage Vdsg generated when the power MOS 43 is turned off is suppressed. This makes it possible to realize the power module 10 in which the surge voltage Vdsg generated when the power MOS 43 is turned off in the overcurrent state is reduced.

(Structure of Example 2)
FIG. 2 is a schematic configuration diagram showing a power module according to a second embodiment of the present invention, and elements common to those in FIG. 1 showing the first embodiment are designated by common reference numerals.

The power module 10A of the second embodiment has a package 10a similar to that of the first embodiment. In the package 10a, the first constant current circuit 20, the second constant current circuit 30-1, the first reference power supply 23 and the turn-off time for adjusting the turn-on time (tr) as the reference voltage supply circuit, which are the same as those in the first embodiment, are provided. (Tf1) The second reference power source 33-1 for adjustment, the first and second switches 41 and 42, the power MOS 43, and the surge voltage suppression circuit 50A having a different configuration from the first embodiment are housed.

The surge voltage suppressor circuit 50A is connected between the drain side of the power MOS 43 and the output side of the second constant current circuit 30-1, and is configured with the overcurrent detection circuit 51 similar to that of the first embodiment and the first embodiment. Different selection circuit 53, third constant current circuit 30-2, third reference power supply 33-2 for adjusting turn-off time (tf2) as a reference voltage supply circuit, and first and second switch elements 34-1 and 34. -2.

The first switch element 34-1 is connected between the output side of the second constant current circuit 30-1 and the (−) side power supply terminal 11b. The third constant current circuit 30-2 and the second switch element 34-2 are connected in series, and the series circuit is connected in parallel to the second constant current circuit 30-1 and the first switch element 34-1. Has been done. The third constant current circuit 30-2 has a constant third control corresponding to the third reference voltage Vtf2 (<second reference voltage Vtf1) input from the third reference power supply 33-2 for adjusting the turn-off time (tf2). It is a circuit that causes the drive current I43 (<second control drive current I42) to flow to the ground side via the second switch element 34-2. The first and second switch elements 34-1 and 34-2 are composed of, for example, switching transistors.

An overcurrent detection circuit 51 is connected between the (+) side output terminal 13a and the drain side of the power MOS 43, and a selection circuit 53 is connected to the output side of the overcurrent detection circuit 51. The selection circuit 53 selects the first switch element 34-1 or the second switch element 34-2 based on the overcurrent detection signal S51 output from the overcurrent detection circuit 51 and shuts off the first switch element 34-1. It is a circuit for turning on (that is, turning off) and conducting (that is, turning on) the second switch element 34-2. That is, when the drain current Id flowing between the drain and the source of the power MOS 43 is in the normal current state, the selection circuit 53 turns on the first switch element 34-1 and turns off the second switch element 34-2 to turn off the power. When the drain current Id flowing between the drain and the source of the MOS 43 is in the overcurrent state, it has a function of turning off the first switch element 34-1 and turning on the second switch element 34-2.

The selection circuit 53 and the first and second switch elements 34-1 and 34-2 constitute a selection unit. Other configurations are similar to those of the first embodiment.

FIG. 3A is a circuit diagram showing a configuration example of the first constant current circuit 20 in FIG.
The first constant current circuit 20 is composed of a first stage current mirror circuit 21 and a first error amplifier circuit 22. The first current mirror circuit 21 is a circuit that allows a first control drive current I41 proportional to the first drive current I21a flowing to the input side to flow to the output side. The first error amplifier circuit 22 detects the first drive current I21a flowing to the input side of the first current mirror circuit 21, generates the corresponding first drive voltage V22b, and turns on the first drive voltage V22b. It is a circuit that changes the first drive current I21a flowing to the input side of the first current mirror circuit 21 by following the first reference voltage Vtr input from the first reference power supply 23 for time (tr) adjustment.

The first current mirror circuit 21 is composed of a pair of transistors (for example, P-channel MOSFET, hereinafter referred to as “PMOS”) 21a and 21b having a transistor size of 1:x (for example, 1:100). Gates of the pair of PMOSs 21a and 21b are commonly connected, and their sources are connected in parallel to the (+) side power supply terminal 11a. The drain of the PMOS 21a is connected to the gates of the PMOS 21a and 21b.

The first error amplification circuit 22 detects a transistor (for example, an N-channel MOSFET, hereinafter referred to as “NMOS”) 22a that changes the current value of the first drive current I21a and the first drive current I21a and responds thereto. The resistor 22b for generating the first drive voltage V22b and the operational amplifier (hereinafter referred to as "op amp") 22c. The drain/source of the NMOS 22a and the resistor 22b are connected in series between the drain of the PMOS 21a and the gates of the PMOSs 21a and 21b and the ground side. The source of the NMOS 22a is connected to the (−) side input terminal of the operational amplifier 22c, and the gate of the NMOS 22a is connected to the output terminal of the operational amplifier 22c. The (+) side input terminal of the operational amplifier 22c is connected to the first reference power source 23, and the first drive voltage V22b input to the (−) side input terminal is input to the (+) side input terminal as a first reference. It has a function of changing the first drive current I21a flowing through the NMOS 22a by following the voltage Vtr.

FIG. 3B is a circuit diagram showing a configuration example of the second and third constant current circuits 30-1 and 30-2 in FIG.
The third constant current circuit 30-2 in FIG. 2 has the same configuration as the second constant current circuit 30-1.

The second constant current circuit 30-1 is composed of a two-stage second current mirror circuit 31 and a second error amplification circuit 32. The second current mirror circuit 31 has a second control drive current I42 proportional to the second drive current I31a flowing to the input side (in the case of the third constant current circuit 30-2, a second drive current I31a proportional to the second drive current I31a flowing to the input side). The third control drive current I43) is supplied to the output side. The second error amplification circuit 32 detects the second drive current I31a flowing to the input side of the second current mirror circuit 31, generates a second drive voltage V32b corresponding to the second drive current I31a, and outputs the second drive voltage V32b to the second drive voltage V32b. The second reference voltage Vtf1 input from the second reference power supply 33-1 (in the case of the third constant current circuit 30-2, the third reference voltage Vtf2 input from the third reference power supply 33-2) is made to follow, This is a circuit that changes the second drive current I31a flowing to the input side of the second current mirror circuit 31.

The second current mirror circuit 31 includes a pair of front-stage transistors (for example, PMOS) 31a and 31b having a transistor size of 1:1 and a pair of rear-stage transistors having a transistor size of 1:x (for example, 1:100). And transistors (for example, NMOS) 31c and 31d.

Gates of the PMOSs 31a and 31b on the front stage side are commonly connected, and their sources are connected in parallel to the power supply voltage VDD side terminal. The drain of the PMOS 31a is connected to the gates of the PMOS 31a and 31b. Gates of the latter-stage NMOSs 31c and 31d are commonly connected, and the gates thereof are connected to the drain of the PMOS 31b and the drain of the NMOS 31c. The drain of the NMOS 31d is connected to the second switch 42 side terminal. Further, the sources of the NMOSs 31c and 31d are connected in parallel to the first switch element 34-1 side terminal (the second switch element 34-2 side terminal in the case of the third constant current circuit 30-2). ..

The second error amplifier circuit 32 includes a transistor (for example, NMOS) 32a that changes the current value of the second drive current I31a, and a resistor that detects the second drive current I31a and generates a second drive voltage V32b corresponding to the detected current. It is constituted by 32b and an operational amplifier 32c. Between the drain of the PMOS 31a and the gates of the PMOSs 31a and 31b and the first switch element 34-1 side terminal (the second switch element 34-2 side terminal in the case of the third constant current circuit 30-2), the NMOS 32a is connected. The drain/source and the resistor 32b are connected in series. The source of the NMOS 32a is connected to the (−) side input terminal of the operational amplifier 32c, and the gate of the NMOS 32a is connected to the output terminal of the operational amplifier 32c. The (+) side input terminal of the operational amplifier 32c is connected to the second reference power supply 33-1 (the third reference power supply 33-2 in the case of the third constant current circuit 30-2), and the (−) side input terminal is connected to the (−) side input terminal. The input second drive voltage V32b is made to follow the second reference voltage Vtf1 (third reference voltage Vtf2 in the case of the third constant current circuit 30-2) input to the (+) side input terminal, and the NMOS 32a. It has a function of changing the second drive current I31a flowing in the.

FIG. 3C is a circuit diagram showing a configuration example of the first and second switches 41 and 42 in FIG.
The first switch 41 and the second switch 42 are configured by complementary transistors (for example, CMOS transistors including a PMOS 41a and an NMOS 42a connected in series) that perform complementary on/off operations. The control terminal 12 is commonly connected to the gates of the PMOS 41a and the NMOS 42a via the buffer 14. The drain of the PMOS 41a and the drain of the NMOS 42a are connected to each other, and this connection point is connected to the gate of the power MOS 43.

(Operation when the drain current Id of the power MOS 43 is in the normal state)
FIG. 4 is a voltage/current waveform diagram showing the operation of the power module 10A of FIG.
In FIG. 4, the horizontal axis represents time t, and the vertical axis represents the voltage value of the source-drain voltage Vds waveform in the power MOS 43 and the current value of the drain current Id waveform in the power MOS 43.

Since the electric/thermal characteristics of the power MOS 43 vary depending on the element, for example, the minimum value tr_min of the turn-on time tr is 50 ns, the maximum value tr_max is 200 ns, and the standard value tr_typ is 100 ns. Similarly, the minimum value tf_min of the turn-off time tf is 50 ns, the maximum value tf_max is 200 ns, and the standard value tf_typ is 100 ns. The hatching area at the intersection of the fall of the drain-source voltage Vds and the rise of the drain current Id and the hatching area of the intersection of the rise of the drain-source voltage Vds and the fall of the drain current Id are on. It is a switching loss Sloss (=Vds×Id) that occurs when switching on/off. When the drain-source voltage Vds rises, an overvoltage surge voltage Vdsg [=(Ld+Ls)×di/dt] may occur due to the influence of the parasitic inductances Ld and Ls.

For example, in the standard value of the power MOS 43, when the turn-on time tr and the turn-off time tf are standard values tr_typ (=50 ns) and tf_typ (=50 ns), the following operation is performed.

In the normal state where the drain current Id of the power MOS 43 is not in the overcurrent state, the overcurrent detection signal S51 is not output from the overcurrent detection circuit 51, so the first switch element 34-1 is turned on by the output signal of the selection circuit 53. Then, the second switch element 34-2 is turned off.

When the gate pulse Pg applied to the control terminal 12 is at L level, it is driven by the buffer 14 in FIG. 3C and supplied to the gates of the PMOS 41a and the NMOS 42a. Then, the PMOS 41a is turned on and the NMOS 42a is turned off.

The operational amplifier 22c in the first constant current circuit 20 of FIG. 3A includes the first reference voltage Vtr supplied from the first reference power supply 23 for adjusting the turn-on time (tr) and the first drive voltage V22b detected by the resistor 22b. And the error is calculated, and the NMOS 22a is gate-controlled so that the error decreases (that is, the first drive voltage V22b follows the first reference voltage Vtr), and the (+) side power supply terminal 11a→ The first drive current I21a flowing from the PMOS 21a to the NMOS 22a to the resistor 22b to the ground side is changed. The changed first drive current I21a is amplified 100 times, for example, by the first current mirror circuit 21 including the pair of PMOSs 21a and 21b, and the amplified first control drive current I41 is fed to the (+) side power supply terminal. 11a→source/drain of PMOS 21b→source/drain of PMOS 41a in FIG. 3C→gate of power MOS 43.

When the first control drive current I41 flows into the gate of the power MOS 43, the first control drive current I41 is injected into the input capacitance Ciss of the power MOS 43, and the gate voltage Vg of the power MOS 43 rises. When the gate voltage Vg rises and exceeds the threshold voltage Vth of the power MOS 43, the power MOS 43 turns on after a predetermined turn-on time (standard turn-on time tr_typ=100 ns). When the power MOS 43 is turned on, a drive current flows in the drive power supply 62 →load resistance 61 →power MOS 43 in the load circuit 60, and the load circuit 60 operates.

When the gate pulse Pg applied to the control terminal 12 becomes H level, this is driven by the buffer 14 in FIG. 3C, the PMOS 41a is turned off and the NMOS 42a is turned on.

The operational amplifier 32c in the second constant current circuit 30-1 of FIG. 3B has the second reference voltage Vtf1 supplied from the second reference power supply 33-1 for adjusting the turn-off time (tf1) and the second reference voltage Vtf1 detected by the resistor 32b. The difference between the drive voltage V32b and the second drive voltage V32b is obtained, and the NMOS 32a is gate-controlled so that this error decreases (that is, the second drive voltage V32b follows the second reference voltage Vtf1), and the power supply voltage VDD terminal →PMOS 31a→NMOS 32a→resistor 32b→first switch element 34-1→(−) side power supply terminal 11b, and the second drive current I31a is changed.

The changed second drive current I31a is converted to 1:1 by the pair of PMOS 31a and 31b at the front stage in the second current mirror circuit 31, and then amplified 100 times by the pair of NMOS 31c and 31d at the rear stage. The generated second control drive current I42 is the gate of the power MOS 43→the drain/source of the NMOS 42a in FIG. 3C→the drain/source of the NMOS 31d in the second constant current circuit 30-1 of FIG. 3B→the first switch element 34−. The charges flowing to the 1→(−) side power supply terminal 11b and accumulated in the input capacitance Ciss of the power MOS 43 are discharged to the (−) side power supply terminal 11b.

When the charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged and the gate voltage Vg drops and falls below the threshold voltage Vth, the power MOS 43 keeps a predetermined turn-off time (standard turn-off time tf_typ=100 ns). Turn off. When the power MOS 43 is turned off, the drive current in the load circuit 60 is cut off and the operation is stopped.

Next, the variation of the power MOS 43 will be described.
Due to the variation of the power MOS 43, the switching loss Sloss (=Vds×Id) and the surge voltage Vdsg [=(Ld+Ls)×di/dt)] vary for each power module 10A. Therefore, the first control drive current I41 is adjusted by the first reference voltage Vtr, and when the turn-on time tr of the power MOS 43 (that is, the fall time of the drain-source voltage Vds) is long as shown in FIG. , And if the turn-on time tr is small, increase it. Further, the second control drive current I42 is adjusted by the second reference voltage Vtf1, and if the turn-off time tf of the power MOS 43 (that is, the rise time of the drain-source voltage Vds) is long, it is made small and the turn-on time tf. If is small, increase it.

As described above, by setting the optimum first control drive current I41 and/or second control drive current I42 for each power module 10A, it is possible to reduce variations in the switching loss Sloss and the surge voltage Vdsg.

(Operation when the drain current Id of the power MOS 43 is in the overcurrent state)
FIG. 5 is a voltage/current waveform diagram showing details of the short circuit fault turn-off in FIG.

The horizontal axis of FIG. 5 represents time t, and the vertical axis represents voltage value and current value. In this voltage/current waveform diagram, for example, the time t of one scale (div) is 200 ns, the voltage of one scale (div) is 100 V/div, and the current of one scale (div) is 20 A/div. As waveform measurement conditions, the drain-source voltage Vds of the power MOS 43 is 400 V, and the power MOS temperature (Tg) is 125° C.

When the power MOS 43 is turned off at the time of a short circuit failure, the surge voltage Vdsg rises largely (for example, 100 V or less), and the drain current Id sharply falls to turn off (for example, within 2 μs). VdsSF is an overshoot surge voltage (for example, about 30 to 50 V) reduced by the surge voltage suppressing action of the second embodiment, and IdSF gently falls and turns off due to the surge voltage suppressing action of the second embodiment. Drain current.

For example, when the power MOS 43 is short-circuited and the power MOS 43 is turned off with a current (overcurrent state) larger than usual, a large surge voltage Vdsg is generated due to the switching time (di/dt) at turn-off, and in some cases The breakdown voltage of the power MOS 43 may be exceeded. In order to solve such a conventional problem, the second embodiment operates as follows.

When the drain current Id of the power MOS 43 is in the overcurrent state, this is detected by the overcurrent detection circuit 51, and the overcurrent detection signal S51 is output from the overcurrent detection circuit 51. Then, the selection circuit 53 switches the first switch element 34-1 to the off state and switches the second switch element 34-2 to the on state.

When the NMOS 42a in FIG. 3C is turned on by the H level of the gate pulse Pg and the charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged to the ground side, the accumulated charge is the third constant current circuit 30-2. And through the second switch element 34-2 to the (−) side power supply terminal 11b. At this time, in the third constant current circuit 30-2, the third reference voltage Vtf2 (<second reference voltage Vtf1) supplied from the third reference power supply 33-2 for adjusting the turn-off time (tf2) is used to control the normal voltage. The third control drive current I43 smaller than the second control drive current I42 is input to the power MOS 43 by the input capacitance Ciss→NMOS 42a→third constant current circuit 30-2→second switch element 34-2→(−) side power supply terminal 11b, Shed to.

Therefore, the fall time (di/dt) of the drain current Id when the power MOS 43 is turned off becomes gentle (current waveform IdSF), and the voltage change (dv/dt) also becomes gentle, so that the surge voltage Vdsg becomes a waveform. It is reduced like VdsSF.

(Effect of Example 2)
The power module 10A of the second embodiment has the following effects (i) to (iii).

(I) has a first constant current circuit 20 and the second constant current circuit 30-1, in the same manner as in Example 1, the first reference voltage Vtr and / or the second reference voltage Vtf1 depending on variations in the power MOS43 Due to the adjustment, the initial variation in the maximum value MAX and/or the minimum value MIN of the turn-on time tr and/or the turn-off time tf is improved. As a result, it is possible to realize the power module 10A with less variation in the switching loss Sloss and the surge voltage Vdsg.

(Ii) Since the surge voltage suppressor circuit 50A is included, when the drain current Id of the power MOS 43 becomes an overcurrent state, the third control drive current smaller than the second control drive current I42 is output from the gate of the power MOS 43. I43 is released, and the surge voltage Vdsg generated when the power MOS 43 is turned off is suppressed. As a result, it is possible to realize the power module 10A in which the surge voltage Vdsg generated when the power MOS 43 is turned off in the overcurrent state is reduced.

(Iii) When the first, second and third constant current circuits 20, 30-1 and 30-2 are respectively composed of, for example, current mirror circuits 21 and 31 and error amplification circuits 22 and 32, their current mirrors By increasing the number of circuits 21 and 31, the current amplification factor can be increased and the characteristics can be stabilized.

(Structure/Operation)
FIGS. 6A and 6B are circuit diagrams showing a configuration example of the reference voltage supply circuit according to the third embodiment of the present invention.

In the second embodiment, the reference voltage supply circuit includes the first reference power supply 23 for adjusting the turn-on time (tr) and the second and third reference power supplies 33-1 and 33-2 for adjusting the turn-off time (tf1, tf2). It is composed of.

On the other hand, the reference voltage supply circuit 23B shown in FIG. 6A of the third embodiment includes two fixed resistors 23a for voltage division and a variable resistor 23b. The two fixed resistors 23a for voltage division and the variable resistor 23b are connected in series between the power supply voltage VDD terminal and the ground side, and the first reference voltage Vtr from the connection point of the fixed resistor 23a and the variable resistor 23b. Is output. The first reference voltage Vtr can be adjusted by changing the resistance value of the variable resistor 23b.

Similarly, in the reference voltage supply circuits 33-1B and 33-2B shown in FIG. 6B of the third embodiment, the voltage dividing fixed resistors 33a and the variable resistors 33b are respectively configured. The two fixed resistors 33a for voltage division and the variable resistor 33b are connected in series between the power supply voltage VDD terminal and the ground side, and from the connection point of the fixed resistor 33a and the variable resistor 33b, the second and third reference points are connected. The voltages Vtf1 and Vtf2 are output, respectively. The second and third reference voltages Vtf1 and Vtf2 can be adjusted by changing the resistance value of the variable resistor 33b.

(effect)
According to the third embodiment, the voltage dividing resistors 23a, 23b, 33a, 33b generate the first, second, and third reference voltages Vtr, Vtf1, Vtf2. Therefore, the external circuit of the power module 10A is Easy to do.

FIG. 7 is an equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element according to the fourth embodiment of the present invention.

The IGBT 56 of the fourth embodiment has three electrodes of an emitter E, a collector C, and a gate G, and has substantially the same operational effect as the power MOS 43 of the first to third embodiments.

Other power transistors such as gallium nitride (GaN) power device and silicon carbide (SiC) power device may be used as the power semiconductor element.

(Other modifications of Examples 1 to 4)
The present invention is not limited to the above-described first to fourth embodiments, and other usage forms and modifications are possible. For example, the following (a) to (d) are available as the usage forms and modified examples.

(A) In the power module 10A of FIG. 2, the second reference voltage Vtf1 for setting the discharge current in the normal state and the third reference voltage Vtf2 for setting the discharge current in the overcurrent state are separately provided. However, the configuration is not limited to this. For example, the ratio of the second reference voltage Vtf1/the third reference voltage Vtf2 can be set to a predetermined value. In this case, when one of the second reference voltage Vtf1 and the third reference voltage Vtf2 is determined, the other voltage is automatically determined. Further, the second constant current circuit 30-1 and the third constant current circuit 30-2 may be configured by one common constant current circuit as in the first embodiment.

(B) The first, second and third constant current circuits 20, 30-1 and 30-2 are different from the first and second current mirror circuits 21 and 31 and the first and second error amplification circuits 22 and 32. You may comprise by another circuit.

(C) The first and second switches 41 and 42 may be configured using semiconductor elements other than the CMOS transistor including the PMOS 41a and the NMOS 42a.

(D) The overcurrent detection circuit 51 may be configured by using a resistor between the source side of the power MOS 43 and the (−) side output terminal 13b, or may be configured by using a current transformer. Further, the power MOS 43 may be a circuit with a current sensing function to configure the circuit.

10, 10A Power Module 10a Package 20, 30-1, 30-2 First, Second, Third Constant Current Circuit 21, 31 First, Second Current Mirror Circuit 22, 32 First, Second Error Amplifier Circuit 23 , 33-1, 33-2 First, second and third reference power sources 23B, 33-1B, 33-2B Reference voltage supply circuits 23a, 33a Voltage dividing fixed resistors 23b, 33b Voltage dividing variable resistors 34-1, 34 -First and second switch elements 41 and 42 First and second switches 41a PMOS
42a NMOS
43 Power MOS
50,50A Surge voltage suppression circuit 51 Overcurrent detection circuit 52 Voltage adjustment circuit 53 Selection circuit 60 Load circuit

Claims (11)

It has a first electrode, a second electrode, and a control electrode that performs an on/off operation between the first electrode and the second electrode when a control voltage is applied, and comprises a parasitic capacitance generated in the control electrode. When the first control drive current is injected into the input capacitance, the first electrode and the second electrode are turned on, the accumulated charge of the input capacitance is discharged, and the second control drive current is released . A power semiconductor device in which one electrode and the second electrode are turned off,
A first constant current circuit to which a first reference voltage is input and which flows a constant first control drive current corresponding to the first reference voltage;
A first switch that is turned on/off by a drive signal and injects the first control drive current into the input capacitance when in an on state;
A second constant current circuit to which a second reference voltage is input and which causes the constant second control drive current corresponding to the second reference voltage to flow;
A second switch that is turned off by the drive signal when the first switch is in the on state and is turned on when the first switch is in the off state, and discharges the second control drive current to the ground side; ,
Equipped with
A power module configured to adjust the first reference voltage and/or the second reference voltage according to variations in the power semiconductor element,
An overcurrent state of a conduction current flowing between the first electrode and the second electrode of the power semiconductor element is detected, and the second reference voltage and the second control drive current are changed based on the overcurrent detection result. A surge voltage suppressing circuit that suppresses a surge voltage generated when the power semiconductor element is turned off,
A power module characterized by being provided.
The surge voltage suppression circuit,
An overcurrent detection circuit that detects an overcurrent state of the conduction current and outputs the overcurrent detection result,
A voltage adjustment circuit that adjusts the second reference voltage to change the second control drive current based on the overcurrent detection result;
The power module according to claim 1, further comprising: The surge voltage suppression circuit,
A third reference voltage smaller than the second reference voltage is input, and a constant third control drive current smaller than the second control drive current is supplied from the input capacitance to the third reference voltage in correspondence with the third reference voltage. A third constant current circuit for discharging to the ground side through two switches,
When detecting an overcurrent state of the conduction current, an overcurrent detection circuit that outputs the overcurrent detection result,
Selecting means for selecting and operating the third constant current circuit in place of the second constant current circuit when the overcurrent detection result is input;
The power module according to claim 1, further comprising: The power module according to claim 3 further comprises:
A power module comprising a reference voltage supply circuit for supplying the first reference voltage, the second reference voltage, and the third reference voltage. The reference voltage supply circuit,
And a reference power source that outputs the first reference voltage, the second reference voltage, and the third reference voltage, respectively.
The power module according to claim 4, wherein The reference voltage supply circuit,
And a voltage dividing resistor for dividing the power supply voltage and outputting the first reference voltage, the second reference voltage, and the third reference voltage, respectively.
The power module according to claim 4, wherein The first constant current circuit,
A one-stage or multiple-stage first current mirror circuit for flowing the first control drive current proportional to the first drive current;
A first error amplifier circuit that detects the first drive current, generates a first drive voltage corresponding to the first drive current, and causes the first drive voltage to follow the first reference voltage to change the first drive current; ,
Have
The second constant current circuit,
A one-stage or multiple-stage second current mirror circuit for flowing the second control drive current proportional to the second drive current;
A second error amplifier circuit that detects the second drive current, generates a second drive voltage corresponding to the second drive current, and causes the second drive voltage to follow the second reference voltage to change the second drive current. ,
Have
The third constant current circuit,
One or a plurality of stages of a third current mirror circuit for flowing the third control drive current proportional to the third drive current;
A third error amplifier circuit that detects the third driving current, generates a corresponding third driving voltage, and causes the third driving voltage to follow the third reference voltage to change the third driving current. ,
Has,
The power module according to claim 3, wherein the power module is a power module. The selection means is
A first switch element for connecting/disconnecting the output current of the second constant current circuit;
A second switch element for connecting/disconnecting the output current of the third constant current circuit;
A selection circuit that selects the first switch element or the second switch element based on the overcurrent detection result, shuts off the first switch element, and connects the second switch element;
The power module according to any one of claims 3 to 7, further comprising: The first switch and the second switch are
9. The power module according to claim 1, wherein the power module is configured by a complementary transistor that is turned on/off complementarily by the drive signal. The power semiconductor element,
The power module according to claim 1, which is a power transistor including a power MOSFET, an IGBT, a GaN power device, or a SiC power device. The power module according to any one of claims 1 to 10,
A power module that is housed in a package.

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