JP6706875B2 - Power module and semiconductor device - Google Patents

Description

The present invention relates to a power module in which a power element and the like are housed in one package, and a semiconductor device including the power module.

Examples of the power semiconductor element that constitutes the power module include, for example, a power MOSFET (hereinafter simply referred to as “power MOS”), an insulation control type bipolar transistor (hereinafter referred to as “IGBT”), a gallium nitride (GaN) power device, and a carbonization device. Power transistors such as silicon (SiC) power devices are known.

Patent Document 1 describes a technique of a semiconductor device with a current detection function, which is capable of accurately detecting a current flowing in an inductive load in a semiconductor device that uses an IGBT to drive and control an inductive load such as an AC motor. ing.

In Patent Document 2, in a drive circuit as a power module using, for example, an IGBT as an insulated gate switching element, a constant current source using a current mirror, a switching circuit, and a current mode selection circuit in order to reduce current consumption. The technology of a drive circuit having a is described.

FIG. 6 is an equivalent circuit diagram showing an outline of a conventional N-channel type power MOS.
The N-channel power MOS 1 has three electrodes of a gate G, a drain D and a source S. For example, a load resistance Rl on the load circuit 2 side and a power supply E that outputs a power supply voltage Vdd are connected in series to the drain/source of the N-channel power MOS 1. In this N-channel power MOS 1, when the gate voltage Vg applied to the gate G rises and exceeds the threshold voltage Vth, the drain-source turns on, and when the gate voltage Vg falls and falls below the threshold voltage Vth, The drain-source turns off.

The gate G, the drain D, and the source S have parasitic capacitance and parasitic inductance. For example, a parasitic capacitance Cgd exists between the gate and the drain, a parasitic capacitance Cgs exists between the gate and the source, and a parasitic capacitance Cds exists between the drain and the source. Further, the parasitic inductance Ld exists on the drain D side and the parasitic inductance Ls exists on the source S side.

The parasitic capacitance Cgd between the gate and the drain has a great influence on the switching characteristics. When the drain-source voltage Vds becomes equal to or lower than the gate-source voltage Vgs, the parasitic capacitance Cgd between the gate and the drain sharply increases, for example, about 10 times. A relational expression such as the following expression (1) is established for each capacitance of the power MOS 1.
Input capacitance Ciss≈Cgd+Cgs
Feedback capacitance Crss≈Cgd
Output capacitance Coss≈Cgd+Cds... (1)

Since the power MOS 1 is a voltage-controlled element, it does not require a drive current when holding the on state or the off state, but when performing a switching operation, the charge/discharge current with respect to the input capacitance Ciss is changed each time. Flowing.

FIG. 7 is a switching operation waveform diagram of the power MOS 1 with respect to the resistance load Rl of FIG.

In the power MOS 1 of FIG. 6, when the drain-source voltage Vds falls from a high (hereinafter “H”) level to a low (hereinafter “L”) level (that is, the drain current Id changes from L level to H level). When the drain-source voltage Vds rises from the L level to the H level (that is, when the drain current Id falls from the H level to the L level), it turns on.

Here, the turn-on time tr is the time between the time 90% from the start of the fall and the time 10% before the end of the fall in the falling waveform of the drain-source voltage Vds. Furthermore, the turn-off time tf is the time between the time of 10% from the start of rising and the time of 90% before the end of rising in the rising waveform of the drain-source voltage Vds.

The hatching area at the intersection of the fall of the drain-source voltage Vds and the rise of the drain current Id and the hatching area of the intersection of the rise of the drain-source voltage Vds and the fall of the drain current Id are on. It is a switching loss Sloss (=Vds×Id) that occurs when switching on/off. At the rise of the drain-source voltage Vds, an overvoltage surge voltage Vdsg [=(Ld+Ls)×di/dt, where di/dt is a switching time] may occur due to the influence of the parasitic inductances Ld and Ls.

FIG. 8 is a data sheet showing an example of electrical/thermal characteristics (case temperature Tc=25° C.) of the power MOS 1 of FIG.
In FIG. 8, when the drain current Id=25 A and the gate-source voltage Vgs=10 V, the drain-source on-resistance Ron has a standard value TYP=6.9 mΩ and a maximum value MAX=8.7 mΩ. is there. When the drain current Id=1 mA and the drain-source voltage Vds=10 V, the gate threshold voltage Vth has a minimum value MIN=2.0 V, a standard value TYP=3.0 V, and a maximum value MAX=4.0 V as standard values. Is.

When the drain-source voltage Vds=25 V, the gate-source voltage Vgs=0 V, and the operating frequency f=1 MHz, the input capacitance Ciss is the standard value TYP=5880 pF as the standard value, and the feedback capacitance Crss is the standard value. Is a standard value TYP=250 pF, and the output capacitance Coss is a standard value TYP=530 pF.

Further, drain current Id=25 A, load resistance Rl=2 Ω, power supply voltage Vdd=50 V, gate resistance Rg=0 Ω, (+) side gate-source voltage Vgs(+)=10 V, and (−) side gate-source When the inter-electrode voltage Vgs(−)=0 V, the turn-on time tr is the standard value TYP=28 ns as the standard value, and the turn-off time tf is the standard value TYP=49 ns as the standard value.

JP, 2003-299363, A International publication WO2012-153459

The conventional power module using the power semiconductor element such as the power MOS 1 and the semiconductor device including the power module have the following problems (a) and (b).

(A) In the data sheet of FIG. 8 showing the electrical/thermal characteristics of the power MOS 1, only the standard value TYP is defined as the standard value of the turn-on time tr and the turn-off time tf (for example, the standard of the turn-on time tr The value TYP is 28 ns, the standard value TYP of the turn-off time tf is 49 ns, and there is no standard value of the maximum value MAX/minimum value MIN in the device design, so the worst (worst) design of the module cannot be performed. That is, in the switching operation waveform of FIG. 7, the worst value of the switching loss Sloss (=Vds×Id) and the surge voltage Vdsg [=(Ld+Ls)×di/dt] is unknown.

Even if the maximum value MAX/minimum value MIN of the turn-on time tr/turn-off time tf can be standardized, the standard value TYP (for example, tr=28 ns, tf= 49 ns), the maximum value MAX/minimum value MIN is in the range of -50%/+100%. If the value is used as it is in the design of the power module, the worst value of the switching loss Sloss will be twice the standard value TYP, and the heat dissipation design must also be doubled. Regarding the minimum value MIN of the turn-on time tr/turn-off time tf, the surge voltage Vdsg generated by the parasitic inductances Ld and Ls is double the standard value TYP, so that the voltage rating of the power MOS1 is exceeded and electromagnetic interference noise is generated. (Electro-Magnetic Interference noise; EMI noise) is a concern.

(B) Since the power MOS1 has manufacturing variations, for example, when manufacturing a semiconductor device such as a power module using the power MOS1, the user must adjust the turn-on time tr and the turn-off time tf of the power MOS1. It is disadvantageous and inconvenient.

The power module of the present invention includes a power semiconductor element, a first constant current circuit, a first switch, a second constant current circuit, and a second switch.

Here, the power semiconductor element includes a first electrode, a second electrode, and a control electrode that is turned on/off between the first electrode and the second electrode when a control voltage is applied, When the first control driving current is injected into the input capacitance formed of the parasitic capacitance generated in the control electrode, the first electrode and the second electrode are turned on, and the accumulated charge of the input capacitance is discharged to drive the second control drive. A switching element that turns off between the first electrode and the second electrode when a current is discharged. The first constant current circuit is a circuit to which a first reference voltage is input and which causes the constant first control drive current corresponding to the first reference voltage to flow.

The first switch is a switch that is turned on/off by an input drive signal and injects the first control drive current into the input capacitance when in the on state. The second constant current circuit is a circuit to which a second reference voltage is input and which causes the constant second control drive current corresponding to the second reference voltage to flow. The second switch is turned off by the drive signal when the first switch is in the on state, and is turned on when the first switch is in the off state, and the second control drive current is moved to the ground side. It is a switch to release. Then, the first reference voltage and/or the second reference voltage is adjusted according to the variation of the power semiconductor element.

Further, in the present invention, when the detection result of the turn-on time and/or the turn-off time during the switching of the power semiconductor device is input, the detection result is a preset turn-on time set value and/or turn-off time setting. An adjusting unit for adjusting the first reference voltage and/or the second reference voltage so as to match the value and giving the first constant current circuit and/or the second constant current circuit. To do.

A semiconductor device of the present invention includes the power module of the present invention, and a waveform detection unit that obtains the detection result of the turn-on time and/or the turn-off time.

According to the power module and the semiconductor device of the present invention, there are the following effects (A) and (B).

(A) has a first constant current circuit and the second constant current circuit, since it is configured to adjust the first reference voltage and / or the second reference voltage in response to variation in the power semiconductor device, the turn-on time and The variation in the maximum value/minimum value of the turn-off time can be improved. As a result, it is possible to realize a power module with less variation in switching loss and surge voltage.

(B) Since the adjustment unit is included, the first reference voltage and/or the second reference voltage can be automatically adjusted according to variations in the power semiconductor element, and the maximum/minimum turn-on time and/or turn-off time can be set. The dispersion of the values can be easily improved. Moreover, since the first reference voltage and/or the second reference voltage can be automatically adjusted, the user does not need to make adjustments, which improves convenience.

1 is a schematic configuration diagram showing a semiconductor device according to a first embodiment of the present invention. Circuit diagram showing an example of the configuration of the first constant current circuit in FIG. Circuit diagram showing a configuration example of the second constant current circuit in FIG. A circuit diagram showing a configuration example of the first and second switches in FIG. Voltage/current waveform diagram showing the operation of the power MOS in Figure 1. Flowchart showing the operation of the semiconductor device of FIG. Equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element in Example 2 of the present invention Equivalent circuit diagram showing the outline of a conventional N-channel power MOS Waveform diagram of the switching operation of the power MOS with respect to the load resistance Rl in FIG. Data sheet showing an example of electric/thermal characteristics (case temperature Tc=25° C.) of the power MOS shown in FIG.

Modes for carrying out the present invention will become apparent when the following description of the preferred embodiments is read in view of the accompanying drawings. However, the drawings are for the purpose of explanation only, and do not limit the scope of the present invention.

(Structure of Example 1)
First Embodiment FIG. 1 is a schematic configuration diagram showing a semiconductor device according to a first embodiment of the present invention.
This semiconductor device includes a power module 10, a gate drive power supply 55 connected to the input side of the power module 10, a waveform detection section 60 connected between the output side and the input side of the power module 10, The load circuit 70 is connected to the output side of the power module 10.

The power module 10 has a package 10a that houses a power semiconductor element and the like. The package 10a is made of resin or ceramics having high heat resistance and high insulation properties. In this package 10a, a (+) side power supply terminal 11a for inputting a DC power supply voltage VDD, a (-) side power supply terminal 11b for grounding, a control terminal 12 for inputting a drive signal (eg, gate pulse) Pg, and switching. The control terminal 13, the (+) side output terminal 14a, and the (-) side output terminal 14b on the ground side are provided for inputting the detection result Sv of the turn-on time tr and/or the turn-off time tf.

The first constant current circuit 20, the second constant current circuit 30, the first switch 41, the second switch 42, the power semiconductor element (for example, N-channel type power MOS) 43, and the adjustment unit 50 are housed in the package 10a. Has been done.

The first constant current circuit 20, the first switch 41, the second switch 42, and the second constant current circuit 30 are connected in series between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. There is. A gate as a control electrode of the power MOS 43 is connected to a connection point between the first switch 41 and the second switch 42. The drain as the first electrode of the power MOS 43 is connected to the (+) side output terminal 14a, and the source as the second electrode of the power MOS 43 is connected to the (-) side output terminal 14b. Further, the input side of the adjusting section 50 is connected to the control terminal 13, and the output side of the adjusting section 50 is connected to the first constant current circuit 20 and the second constant current circuit 30.

The first constant current circuit 20 is a circuit that causes a constant first control drive current I41 corresponding to the first reference voltage Vtr input from the adjustment unit 50 to flow to the first switch 41 side. The second constant current circuit 30 is a circuit that causes a constant second control drive current I42 corresponding to the second reference voltage Vtf input from the adjustment unit 50 to flow to the ground side.

The first switch 41 is turned on/off by the gate pulse Pg input from the control terminal 12 (for example, turned on by the L level of the gate pulse Pg and turned off by the H level), and when the on state is set, the first switch 41 The first control drive current I41 from the first constant current circuit 20 is injected through the gate of the power MOS 43 into the input capacitance Ciss which is its parasitic capacitance. The second switch 42 is turned off by the gate pulse Pg input from the control terminal 12 when the first switch 41 is on (for example, turned off by the L level of the gate pulse Pg), and the first switch 41 is turned on. When it is in the off state, it is in the on state (for example, in the on state due to the H level of the gate pulse Pg), and the second control drive current I42 from the gate of the power MOS 43 is discharged to the second constant current circuit 30 side.

The power MOS 43 is turned on when the first control drive current I41 is injected into the input capacitance Ciss generated at the gate and the gate voltage Vg as a control voltage applied to the input capacitance Ciss rises and exceeds the threshold voltage Vth, and the input capacitance This is a switching element that is turned off when the accumulated charge of Ciss is discharged and the second control drive current I42 is discharged, and the gate voltage Vg applied to its input capacitance Ciss drops and falls below the threshold voltage Vth.

When the detection result Sv, which is a digital signal of the turn-on time tr and/or the turn-off time tf when the power MOS 43 is switched, is input to the adjustment unit 50, the detection result Sv is a turn-on time that is a preset digital signal. The first reference voltage Vtr and/or the second reference voltage Vtf are adjusted so as to match the set value tr0 and/or the turn-off time set value tf0, and are applied to the first constant current circuit 20 and/or the second constant current circuit 30. It is a thing. The adjustment unit 50 includes a control unit (for example, a memory control unit) 51, an output unit (for example, a digital/analog conversion circuit, hereinafter referred to as “D/A conversion circuit”) 52 connected to the output side, have.

The memory control unit 51 has a memory 51a. In the memory 51a, a turn-on time set value tr0 and/or a turn-off time set value tf0 which are digital signals, and a first reference voltage Vtr and/or a second reference voltage Vtf which are digital signals adjusted by the adjusting unit 50 are stored. , Are stored. The memory control unit 51 detects the turn-on time set value tr0 and/or the turn-off time set value tf0, which are digital signals stored in the memory 51a, and the input turn-on time tr and/or the turn-off time tf, which are digital signals. An error ERR between Sv and Sv is obtained, and the first reference voltage Vtr and/or the second reference voltage Vtf composed of a digital signal stored in the memory 51a is adjusted and output so as to reduce the error ERR. , A MCU (Memory Control Unit) or the like having a memory, for example.

The D/A conversion circuit 52 converts the first reference voltage Vtr and/or the second reference voltage Vtf, which are digital signals output from the memory control unit 51, into an analog signal, and outputs the converted first reference voltage Vtr. It is a circuit for giving the first constant current circuit 20 and/or the converted second reference voltage Vtf to the second constant current circuit 30.

A gate drive power supply 55 for applying the power supply voltage VDD is connected between the (+) side power supply terminal 11a and the (−) side power supply terminal 11b. A waveform detection unit 60 is connected between the (+) side output terminal 14a and the (−) side output terminal 14b and the control terminals 12 and 13. A load circuit 70 is connected to the (+) side output terminal 14a and the (-) side output terminal 14b.

The waveform detection unit 60 has a waveform acquisition unit 61 and an information processing unit 62 connected to this output side. The waveform acquisition unit 61 acquires a voltage waveform when the power MOS 43 is switching, and is configured by, for example, a waveform measuring instrument including an oscilloscope. The information processing unit 62 obtains the detection result Sv, which is a digital signal of the turn-on time tr and/or the turn-off time tf, from the voltage waveform acquired by the waveform acquisition unit 61, and the detection result Sv is obtained via the control terminal 13. The drive signal Pg is output to the adjustment unit 50 and is output to the first and second switches 41 and 42 via the control terminal 12, and is used, for example, in a personal computer (PC) or the like. It is composed of arithmetic control means including a computer.

The load circuit 70 has, for example, a load resistor 71, a DC drive power source 72, and the like, which are connected in series between the (+) side output terminal 14a and the (−) side output terminal 14b.

FIG. 2A is a circuit diagram showing a configuration example of the first constant current circuit 20 in FIG.
The first constant current circuit 20 is composed of a first stage current mirror circuit 21 and a first error amplifier circuit 22. The first current mirror circuit 21 is a circuit that allows a first control drive current I41 proportional to the first drive current I21a flowing to the input side to flow to the output side. The first error amplifier circuit 22 detects a first drive current I21a flowing to the input side of the first current mirror circuit 21, generates a first drive voltage V22b corresponding to the first drive current I21a, and adjusts the first drive voltage V22b. This circuit changes the first drive current I21a flowing to the input side of the first current mirror circuit 21 by following the first reference voltage Vtr input from the unit 50.

The first current mirror circuit 21 is composed of a pair of transistors (for example, P-channel MOSFET, hereinafter referred to as “PMOS”) 21a and 21b having a transistor size of 1:x (for example, 1:100). Gates of the pair of PMOSs 21a and 21b are commonly connected, and their sources are connected in parallel to the (+) side power supply terminal 11a. The drain of the PMOS 21a is connected to the gates of the PMOS 21a and 21b.

The first error amplification circuit 22 detects a transistor (for example, an N-channel MOSFET, hereinafter referred to as “NMOS”) 22a that changes the current value of the first drive current I21a and the first drive current I21a and responds thereto. The resistor 22b for generating the first drive voltage V22b and the operational amplifier (hereinafter referred to as "op amp") 22c. The drain/source of the NMOS 22a and the resistor 22b are connected in series between the drain of the PMOS 21a and the gates of the PMOSs 21a and 21b and the ground side. The source of the NMOS 22a is connected to the (−) side input terminal of the operational amplifier 22c, and the gate of the NMOS 22a is connected to the output terminal of the operational amplifier 22c. The operational amplifier 22c has a (+) side input terminal to which the first reference voltage Vtr is input, and a (−) side input terminal to which the first drive voltage V22b is input to a (+) side input terminal. The circuit changes the first drive current I21a flowing through the NMOS 22a by following the voltage Vtr.

FIG. 2B is a circuit diagram showing a configuration example of the second constant current circuit 30 in FIG.
The second constant current circuit 30 is composed of a two-stage second current mirror circuit 31 and a second error amplifier circuit 32. The second current mirror circuit 31 is a circuit that causes a second control drive current I42 proportional to the second drive current I31a flowing on the input side to flow on the output side. The second error amplifier circuit 32 detects the second drive current I31a flowing to the input side of the second current mirror circuit 31, generates a second drive voltage V32b corresponding to the second drive current I31a, and adjusts the second drive voltage V32b. This circuit changes the second drive current I31a flowing to the input side of the second current mirror circuit 31 by following the second reference voltage Vtf input from the unit 50.

The second current mirror circuit 31 includes a pair of front-stage transistors (for example, PMOS) 31a and 31b having a transistor size of 1:1 and a pair of rear-stage transistors having a transistor size of 1:x (for example, 1:100). And transistors (for example, NMOS) 31c and 31d.

Gates of the PMOSs 31a and 31b on the front side are commonly connected, and their sources are connected in parallel to the power supply voltage VDD terminal. The drain of the PMOS 31a is connected to the gates of the PMOS 31a and 31b. Gates of the latter-stage NMOSs 31c and 31d are commonly connected, and the gates thereof are connected to the drain of the PMOS 31b and the drain of the NMOS 31c. The sources of the NMOSs 31c and 31d are connected in parallel to the (−) side power supply terminal 11b.

The second error amplifier circuit 32 includes a transistor (for example, NMOS) 32a that changes the current value of the second drive current I31a, and a resistor that detects the second drive current I31a and generates a second drive voltage V32b corresponding to the detected current. It is constituted by 32b and an operational amplifier 32c. The drain/source of the NMOS 32a and the resistor 32b are connected in series between the drain of the PMOS 31a and the gates of the PMOSs 31a and 31b and the (−) side power supply terminal 11b. The source of the NMOS 32a is connected to the (−) side input terminal of the operational amplifier 32c, and the gate of the NMOS 32a is connected to the output terminal of the operational amplifier 32c. In the operational amplifier 32c, the second reference voltage Vtf is input to the (+) side input terminal, and the second drive voltage V32b input to the (−) side input terminal is input to the (+) side input terminal as the second reference voltage Vtf. It is a circuit that follows the voltage Vtf and changes the second drive current I31a flowing through the NMOS 32a.

FIG. 2C is a circuit diagram showing a configuration example of the first and second switches 41 and 42 in FIG.
The first switch 41 and the second switch 42 are configured by complementary transistors that perform on/off operations in a complementary manner (for example, a CMOS transistor including a PMOS 41a and an NMOS 42a connected in series). The control terminal 12 is commonly connected to the gates of the PMOS 41a and the NMOS 42a via the buffer 15. The drain of the PMOS 41a and the drain of the NMOS 42a are connected to each other, and this connection point is connected to the gate of the power MOS 43.

(Operation of Example 1)
FIG. 3 is a voltage/current waveform diagram showing the operation of the power MOS 43 in FIG.
The horizontal axis of FIG. 3 represents time t, and the vertical axis represents the voltage value of the source-drain voltage Vds waveform in the power MOS 43 and the current value of the drain current Id waveform in the power MOS 43.

Since the electric/thermal characteristics of the power MOS 43 vary depending on the element, for example, the minimum value tr_min of the turn-on time tr is 50 ns, the maximum value tr_max is 200 ns, and the standard value tr_typ is 100 ns. Similarly, the minimum value tf_min of the turn-off time tf is 50 ns, the maximum value tf_max is 200 ns, and the standard value tf_typ is 100 ns. The hatching area at the intersection of the fall of the drain-source voltage Vds and the rise of the drain current Id and the hatching area of the intersection of the rise of the drain-source voltage Vds and the fall of the drain current Id are on. It is a switching loss Sloss (=Vds×Id) that occurs when switching on/off. When the drain-source voltage Vds rises, an overvoltage surge voltage Vdsg [=(Ld+Ls)×di/dt] may occur due to the influence of the parasitic inductances Ld and Ls.

FIG. 4 is a flowchart showing the operation of the semiconductor device of FIG.
For example, when the turn-on time tr and the turn-off time tf are standard values tr_typ (=50 ns) and tf_typ (=50 ns) in the standard value of the power MOS 43, the semiconductor device of FIG. 1 operates as in steps S1 to S7 below. To do.

When the semiconductor device of FIG. 1 starts operating and proceeds to step S1 of FIG. 4, the memory control unit 51 sets the first reference voltage Vtr and/or the second reference voltage Vtf, which are digital signals stored in the memory 51a. It is read and given to the D/A conversion circuit 52. The D/A conversion circuit 52 converts the first reference voltage Vtr and/or the second reference voltage Vtf formed of the read digital signal into an analog signal, and uses the converted first reference voltage Vtr as an initial value. Output to the first constant current circuit 20 and/or to the second constant current circuit 30 with the converted second reference voltage Vtf as an initial value, and the process proceeds to step S2.

In step S2, the information processing section 62 outputs the gate pulse Pg to the control terminal 12. When the gate pulse Pg is at the L level, it is driven by the buffer 15 of FIG. 2C, the PMOS 41a of FIG. 2C corresponding to the first switch 41 is turned on, and the NMOS 42a of FIG. 2C corresponding to the second switch 42 is turned off. .. Then, in the first constant current circuit 20 of FIG. 2A, the operational amplifier 22c obtains an error between the first reference voltage Vtr input as the initial value and the first drive voltage V22b detected by the resistor 22b, and this error So as to decrease (that is, so that the first drive voltage V22b follows the first reference voltage Vtr), the gate of the NMOS 22a is controlled, and the (+) side power supply terminal 11a→PMOS 21a→NMOS 22a→resistor 22b→ground side. , The first drive current I21a flowing to, is changed. The changed first drive current I21a is amplified 100 times, for example, by the first current mirror circuit 21 including the pair of PMOSs 21a and 21b, and the amplified first control drive current I41 is fed to the (+) side power supply terminal. 11a→source/drain of PMOS 21b→source/drain of PMOS 41a→gate of power MOS 43.

When the first control drive current I41 flows into the gate of the power MOS 43, the first control drive current I41 is injected into the input capacitance Ciss of the power MOS 43, and the gate voltage Vg of the power MOS 43 rises. When the gate voltage Vg rises and exceeds the threshold voltage Vth of the power MOS 43, the power MOS 43 turns on after a predetermined turn-on time (standard turn-on time tr_typ=100 ns). When the power MOS 43 is turned on, a drive current flows from the drive power supply 72 in the load circuit 70 to the load resistance 71 to the power MOS 43, and the load circuit 70 operates.

When the gate pulse Pg input to the control terminal 12 becomes the H level, this is driven by the buffer 15 of FIG. 2C, the PMOS 41 a of FIG. 2C corresponding to the first switch 42 is turned off, and the gate pulse Pg of the second switch 42 is corresponded. The NMOS 42a in FIG. 2C is turned on. Then, in the second constant current circuit 30 of FIG. 2B, the operational amplifier 32c obtains the error between the second reference voltage Vtf input as the initial value and the second drive voltage V32b detected by the resistor 32b, and this error Power supply voltage VDD terminal→PMOS 31a→NMOS 32a→resistor 32b→(−) side power supply by controlling the gate of the NMOS 32a so that the output voltage decreases (that is, the second drive voltage V32b follows the second reference voltage Vtf). The second drive current I31a flowing to the terminal 11b is changed.

The changed second drive current I31a is converted to 1:1 by the pair of PMOS 31a and 31b at the front stage in the second current mirror circuit 31, and then amplified 100 times by the pair of NMOS 31c and 31d at the rear stage. The generated second control drive current I42 flows to the gate of the power MOS 43→the drain/source of the NMOS 42a→the drain/source of the NMOS 31d→the (−) side power supply terminal 11b, and the charge accumulated in the input capacitance Ciss of the power MOS 43 is stored. , (−) side power supply terminal 11b is discharged.

When the charge accumulated in the input capacitance Ciss of the power MOS 43 is discharged and the gate voltage Vg drops and falls below the threshold voltage Vth, the power MOS 43 keeps a predetermined turn-off time (standard turn-off time tf_typ=100 ns). Turn off. When the power MOS 43 is turned off, the drive current in the load circuit 70 is cut off and the operation is stopped.

After such operation of step S2 of FIG. 4, the process proceeds to step S3. In step S3, the waveform acquisition unit 61 acquires the waveform of the drain-source voltage Vds at the time of switching the power MOS 43, and proceeds to step S4. In step S4, the information processing unit 62 takes in the voltage change amount (dv/dt) at the time of falling and the time of rising from the acquired waveform of the drain-source voltage Vds, and turns on the turn-on time tr and/or turn-off. The time tf is detected, the detection result Sv consisting of a digital signal is given to the memory control unit 51 via the control terminal 13, and the process proceeds to step S5.

In step S5, the memory controller 51 detects the detection result Sv which is a digital signal of the input turn-on time tr and/or the turn-off time tf, and the turn-on time set value tr0 and/or the digital signal stored in the memory 51a. If the turn-on time set value tf0 is compared with the turn-on time tr and/or the turn-off time tf does not reach the turn-on time set value tr0 and/or the turn-off time set value tf0 (that is, the turn-on time set value tr0 and/or Alternatively, if there is an error ERR between the turn-off time set value tf0 and the turn-on time tr and/or the turn-off time tf), the process proceeds to step S6. On the other hand, when the turn-on time tr and/or the turn-off time tf reaches the turn-on time set value tr0 and/or the turn-off time set value tf0 (that is, the turn-on time set value tr0 and/or the turn-off time set value tf0, If there is no error ERR between the turn-on time tr and/or the turn-off time tf), the process proceeds to step S7.

When the process proceeds to step S6, the memory control unit 51 adjusts by decreasing or increasing the first reference voltage Vtr and/or the second reference voltage Vtf stored in the memory 51a so that the error ERR decreases. To do. The D/A conversion circuit 52 converts the adjusted first reference voltage Vtr and/or the second reference voltage Vtf into an analog signal, outputs the first reference voltage Vtr to the first constant current circuit 20, and/ Alternatively, the second reference voltage Vtf is output to the second constant current circuit 30, and the process returns to step S2. Then, the operations of steps S2 to S5 similar to the above are performed, and in step S5, the turn-on time tr and/or the turn-off time tf reaches the set value of the turn-on time set value tr0 and/or the turn-off time set value tf0. In this case, the process proceeds to step S7.

In step S7, the memory control unit 51 writes the adjusted first reference voltage Vtr and/or the second reference voltage Vtf in the memory 51a, and then ends the operation.

Next, the variation of the power MOS 43 will be described.
Due to the variation of the power MOS 43, the switching loss Sloss (=Vds×Id) and the surge voltage Vdsg [=(Ld+Ls)×di/dt)] vary for each power module 10. Therefore, the first control drive current I41 is changed by the adjusted first reference voltage Vtr, and as shown in FIG. 3, the turn-on time tr of the power MOS 43 (that is, the fall time of the drain-source voltage Vds) is long. If the turn-on time tr is small, it is made large.

Further, the second control drive current I42 is changed by the adjusted second reference voltage Vtf, and if the turn-off time tf of the power MOS 43 (that is, the rise time of the drain-source voltage Vds) is long, it is made small. If the turn-on time tf is small, it is increased. As described above, by automatically setting the optimum first control drive current I41 and/or second control drive current I42 for each power module 10, it is possible to reduce variations in the switching loss Sloss and the surge voltage Vdsg. become.

(Effect of Example 1)
The semiconductor device of Example 1 has the following effects (1) to (3).

(1) Since the first constant current circuit 20 and the second constant current circuit 30 are provided and the first reference voltage Vtr and/or the second reference voltage Vtf1 is adjusted according to the variation of the power MOS 43 , It is possible to improve the variation in the maximum value MAX/minimum value MIN of the turn-on time tr and/or the turn-off time tf. As a result, it is possible to realize the power module 10 in which variations in the switching loss Sloss and the surge voltage Vdsg are small.

(2) Since the adjustment unit 50 is included, the first reference voltage Vtr and/or the second reference voltage Vtf can be automatically adjusted according to the variation of the power MOS 43, and the turn-on time tr and/or the turn-off time tf can be adjusted. The variation of the maximum value MAX/minimum value MIN can be easily improved. In addition, since the first reference voltage Vtr and/or the second reference voltage Vtf can be automatically adjusted, the user does not need to make adjustments and convenience is improved.

(3) When the first constant current circuit 20 and the second constant current circuit 30 are respectively configured by the first and second current mirror circuits 21 and 31 and the first and second error amplification circuits 22 and 32, respectively, The second current mirror circuit 31 may be composed of one stage. Further, if the first current mirror circuit 21 and the second current mirror circuit 31 are provided in multiple stages (for example, two stages), an increase in current amplification factor and stability of characteristics can be realized.

FIG. 5 is an equivalent circuit diagram showing an outline of an IGBT as a power semiconductor element according to the second embodiment of the present invention.
The IGBT 80 of the second embodiment has three electrodes of an emitter E, a collector C, and a gate G, and has substantially the same operational effect as the power MOS 43 of the first embodiment.

Other power transistors such as gallium nitride (GaN) power device and silicon carbide (SiC) power device may be used as the power semiconductor element.

(Other modifications of Examples 1 and 2)
The present invention is not limited to the first and second embodiments described above, and other usage forms and modifications are possible. Examples of the usage form and the modified examples include the following (i) to (iii).

(I) The first and second constant current circuits 20 and 30 may be configured by circuits other than the first and second current mirror circuits 21 and 31 and the first and second error amplification circuits 22 and 32. ..

(Ii) The adjusting unit 50 and the waveform detecting unit 60 may be changed to configurations other than those shown in the drawings.

(Iii) The first and second switches 41 and 42 may be configured by using a semiconductor element other than the CMOS transistor including the PMOS 41a and the NMOS 42a.

10 power module 10a package 20,30 1st, 2nd constant current circuit 21,31 1st, 2nd current mirror circuit 22,32 1st, 2nd error amplification circuit 41,42 1st, 2nd switch 41a PMOS
42a NMOS
43 Power MOS
50 adjustment unit 51 memory control unit 51a memory 52 D/A conversion circuit 60 waveform detection unit 61 waveform acquisition unit 62 information processing unit 70 load circuit 80 IGBT

Claims (9)

An input capacitance, which has a first electrode, a second electrode, and a control electrode that switches between the first electrode and the second electrode when a control voltage is applied, is formed as a parasitic capacitance generated in the control electrode. When the first control drive current is injected, the then between the first electrode and the second electrode is turned on, the accumulated charge of the input capacitance second control drive current is discharged is released, the first electrode and A power semiconductor device in which the second electrodes are turned off,
A first constant current circuit to which a first reference voltage is input and which flows a constant first control drive current corresponding to the first reference voltage;
A first switch that is turned on/off by an input drive signal and injects the first control drive current into the input capacitance when in an on state;
A second constant current circuit to which a second reference voltage is input and which causes the constant second control drive current corresponding to the second reference voltage to flow;
A second switch that is turned off by the drive signal when the first switch is in the on state and is turned on when the first switch is in the off state, and discharges the second control drive current to the ground side; ,
Equipped with
A power module configured to adjust the first reference voltage and/or the second reference voltage according to variations in the power semiconductor element,
When the detection result of the turn-on time and/or the turn-off time during the switching of the power semiconductor device is input, the detection result may match the preset turn-on time set value and/or turn-off time set value. An adjusting unit which adjusts the first reference voltage and/or the second reference voltage and gives the first constant current circuit and/or the second constant current circuit ,
A power module characterized by being provided . The adjustment unit,
The turn-on time setting value and/or the turn-off time setting value, and a memory for storing the adjusted first reference voltage and/or second reference voltage, and the turn-on time setting value stored in the memory. Value and/or an error between the turn-off time set value and the detection result is obtained, and the first reference voltage and/or the second reference voltage stored in the memory is adjusted so that the error decreases. Output control unit,
An output unit for applying the first reference voltage output from the control unit to the first constant current circuit and/or applying the second reference voltage output from the control unit to the second constant current circuit. When,
The power module according to claim 1, further comprising: The control unit includes a memory control device having the memory,
The output unit includes a digital/analog conversion circuit,
The power module according to claim 2, wherein The first constant current circuit,
A one-stage or multiple-stage first current mirror circuit for flowing the first control drive current proportional to the first drive current;
A first error amplifier circuit that detects the first drive current, generates a first drive voltage corresponding to the first drive current, and causes the first drive voltage to follow the first reference voltage to change the first drive current; ,
Have
The second constant current circuit,
A one-stage or multiple-stage second current mirror circuit for flowing the second control drive current proportional to the second drive current;
A second error amplifier circuit that detects the second drive current, generates a second drive voltage corresponding to the second drive current, and causes the second drive voltage to follow the second reference voltage to change the second drive current. ,
Has,
The power module according to claim 1, wherein the power module is a power module. The first switch and the second switch are
The power module according to any one of claims 1 to 4, wherein the power module is configured by a complementary transistor that is turned on/off complementarily by the drive signal. The power semiconductor element,
The power module according to any one of claims 1 to 5, which is a power transistor including a power MOSFET, an IGBT, a GaN power device, or a SiC power device. A power module according to any one of claims 1 to 6,
A waveform detection unit that obtains the detection result of the turn-on time and/or the turn-off time,
A semiconductor device comprising: The waveform detection unit,
A waveform acquisition unit that acquires a voltage waveform during the switching of the power semiconductor element,
From the voltage waveform acquired by the waveform acquisition unit, the detection result of the turn-on time and/or the turn-off time is obtained and given to the adjustment unit, and the drive signal is output to output the drive signal and the first switch and the first switch. An information processing unit for the two switches,
The semiconductor device according to claim 7, further comprising: The waveform acquisition unit is composed of a waveform measuring instrument including an oscilloscope,
The information processing section is composed of arithmetic control means including a computer,
9. The semiconductor device according to claim 8, wherein:

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