CN104767518A - Substrate switching circuit based on CMOS - Google Patents
Substrate switching circuit based on CMOS Download PDFInfo
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- CN104767518A CN104767518A CN201510183942.2A CN201510183942A CN104767518A CN 104767518 A CN104767518 A CN 104767518A CN 201510183942 A CN201510183942 A CN 201510183942A CN 104767518 A CN104767518 A CN 104767518A
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Abstract
The invention belongs to the technical field of integrated circuits, and relates to a substrate switching circuit based on a CMOS. The circuit comprises a reference current source circuit, a comparator circuit and a high-voltage selection circuit. The circuit is characterized in that one, higher in voltage, of two voltage sources is automatically selected to be provided as the substrate level of a PMOS tube, and electricity leakage is prevented from occurring at the substrate end when the PMOS tube is turned off.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of substrate change-over circuit based on CMOS, be applicable to various have duplicate supply input chip system in, be specially adapted to mobile phone, portable computer etc. and have in the mobile device of duplicate supply.
Background technology
Substrate change-over circuit based on CMOS is widely used in analog module, is especially widely used in the circuit with duplicate supply, as in charger circuit, DC/DC booster circuit and boosted charge pump circuit.
Fig. 1 is the circuit diagram of a kind of substrate selection circuit in prior art.This substrate selection circuit structure is simple, as shown in Figure 1, PMOS transistor P1 and P2 is for selecting and driving tube, P1 source electrode is connected to supply voltage V1, grid is connected to supply voltage V2, and P2 source electrode is connected to supply voltage V2, and grid is connected to supply voltage V1, P1 and P2 drain electrode is connected, and is connected to the substrate of P1 and P2.For this substrate selection circuit, if V1 > is V2, the conducting of P1 pipe, P2 pipe ends, and output voltage VO UT is then V1; If V2 > is V1, then P1 pipe cut-off, the conducting of P2 pipe, output voltage VO UT is then V2, visible, and VOUT is select in both V1, V2 higher one.
Although above-mentioned substrate selection circuit structure is simple, but there is following shortcoming: above-mentioned substrate selection circuit can make selecting properly when V1 and V2 difference is larger, but work as V1, V2 difference is little and when needing driving force, because P1 and P2 all can not conducting completely, VOUT is caused not make selecting properly; If when having a voltage not exist in V1 and V2, the grid voltage floating of P1 or P2, also can cause VOUT not make selecting properly.
Summary of the invention
The object of the present invention is to provide a kind of substrate change-over circuit based on CMOS, overcome V1 and V2 that above-mentioned prior art exists close to or V1 and V2 in have a voltage not exist time substrate selection circuit can not make the shortcoming of selecting properly.
For overcoming the defect that prior art exists, the invention provides a kind of substrate change-over circuit based on CMOS, for exporting the higher person among the first supply voltage and second source voltage, be supplied to PMOS to use as underlayer voltage, comprise: reference current source circuit, comparator circuit and high voltage selection circuit;
Described reference current source, is connected to the first supply voltage, produces a reference current, obtains the first image current and the second image current respectively in the first supply voltage domain and second source voltage domain mirror image;
Described comparator circuit, utilizes described first image current and described second image current as load, compares the size of the first supply voltage and second source voltage, and utilize the first inverter to carry out shaping to comparison value, export a comparison value;
Described high voltage selection circuit, is input as the comparison value of described comparator, selects an output higher in the first supply voltage and second source voltage.
Concrete, described reference current source comprises: the first NMOS tube, the second NMOS tube and the first resistance, the second resistance; Second NMOS tube source connects the second resistance anode, and the first NMOS tube source connects the second resistance anode, the first resistance and the second resistance negativing ending grounding, and described first NMOS tube is connected the load input terminal of described comparator circuit with the drain terminal of the second NMOS tube.
Further, described comparator circuit comprises: the 3rd PMOS, the 4th PMOS and the first inverter; 3rd PMOS source and substrate connect the first supply voltage, 4th PMOS source and substrate connect second source voltage, 3rd PMOS grid and drain electrode short circuit are also connected to the grid of the 4th PMOS, the drain electrode of the above the second NMOS tube is also received in the drain electrode of the 3rd PMOS, the drain electrode of the 4th PMOS connects drain electrode and first inverter input of the above the first NMOS tube, the output of the first inverter exports comparison value, and the power end of described first inverter is the output of described high voltage selection circuit.
Concrete, described high voltage selection circuit comprises: the first PMOS, the 2nd PMOS and the second inverter and the 3rd inverter; First PMOS source connects the first supply voltage, and the second PMOS source connects second source voltage, and the drain terminal of the first and second PMOS and substrate are all connected to output voltage and as second and the 3rd supply voltage of inverter; The input that second inverter input connects the output of the first inverter, output connects the first PMOS grid and the 3rd inverter; The output of the 3rd inverter is connected to the grid of the second PMOS.
The present invention is owing to have employed above-mentioned technical scheme, compared with prior art, it can two input voltage values close to time still can make correct selection, meanwhile, the present invention also obtains less image current by current mirroring circuit mirror image, and the resistance that can arrange wherein resistance makes the quiescent current of whole circuit less, reduce circuit power consumption, it is wide that visible the present invention has input voltage range, and area is little, structure is simple, advantage low in energy consumption.
Accompanying drawing explanation
By following to the present invention is based on the embodiment of substrate change-over circuit of CMOS in conjunction with the description of its accompanying drawing, object of the present invention, specific structural features and advantage can be understood further.Wherein, accompanying drawing is:
Fig. 1 is the electrical schematic diagram of prior art based on the substrate change-over circuit of CMOS;
Fig. 2 is the electrical schematic diagram of the substrate change-over circuit that the present invention is based on CMOS.
Embodiment
As shown in Figure 2, substrate change-over circuit based on CMOS of the present invention is used for the higher person among the first supply voltage V1 and second source voltage V2 to output to VOUT, be supplied to PMOS to use as underlayer voltage, prevent when PMOS is closed, produce electric leakage in its substrate terminal.
First PMOS P1 is for the path of control V1 to VOUT, and the second PMOS P2 is for the path of control V2 to VOUT.P1 source electrode meets V1, and P2 source electrode meets V2, and drain electrode and the substrate of P1 and P2 are connected to VOUT.In the middle of P1 and P2, the same time only has a meeting conducting, below can illustrate what how circuit controlled the grid of P1 and P2.
Reference current source circuit, is made up of N1 ~ N2 and R1 ~ R2.First NMOS tube N1, the first resistance R1, the second NMOS tube N2, the second resistance R2 connect into the current mirror form of automatic biasing, second NMOS tube source connects the second resistance anode, first NMOS tube source connects the second resistance anode, first resistance and the second resistance negativing ending grounding, described first NMOS tube is connected the load input terminal of described comparator circuit with the drain terminal of the second NMOS tube, the drain electrode of two NMOS tube connects load as output, the load of such as a pair PMOS P3 as shown in Figure 2 and P4 composition.Adopting the form of automatic biasing to provide bias voltage without the need to re-using extra biasing circuit for N1 and N2, simplifying circuit design.
Represent the first inverter INV1, the second inverter INV2 and the 3rd inverter INV3 in dotted line frame shown in Fig. 2 respectively, three inverters are inverter structure well known in the art.
Comparator circuit can be made up of P3, P4 and the first inverter INV.P3 and P4 forms one group of current comparison circuit, and the source electrode of P3 meets the first supply voltage V1, and the source electrode of P4 meets second source voltage V2, and the grid of P3 and drain electrode short circuit are also connected to the grid of P4, form one group of current mirror.The drain electrode of N2 is received in the drain electrode of P3, and first group of current source is exported the load as P3; The drain electrode of N3 is received in the drain electrode of P4, and second group of current source is exported the load as P4.Because two groups of current sources are identical, therefore when V1=V2, the electric current of P3 with P4 is identical, circuit beinthebalancestate.As V1>V2, the grid voltage of P3 can and V1 synchronously raise, the grid of P4 also can be enhanced, and the electric current at this moment flowing through P4 from V2 will reduce, and the voltage of the input net1 point of the first inverter can be dragged down.Vice versa, if during V1<V2, the grid voltage of P3 can and V1 synchronously decline, the grid of P4 also can be lowered, and the electric current at this moment flowing through P4 from V2 will increase, the voltage high of net1 point.First inverter INV can carry out shaping to the voltage of net1 point, ensure V1 and V2 voltage compare close to time, export correct logic level.
Voltage output circuit is made up of the 5th PMOS P5, the 6th PMOS P6, the 5th NMOS tube N5, the 6th PMOS N6 and the first PMOS P1, the second PMOS P2.P5 and N5 forms the second inverter, the output of its input termination first inverter INV, and its output is connected to the grid of P1; P6 and N6 forms the 3rd inverter, and the output of its input termination second inverter, its output is connected to the grid of P2.Second and the 3rd the supply voltage of inverter be all connected to the drain electrode of P1 and P2, powered by higher one of voltage in V1 and V2.As V1>V2, the first inverter INV output HIGH voltage, then the second inverter output LOW voltage, the conducting of P1 pipe, the 3rd inverter output HIGH voltage, P2 pipe end, at this moment VOUT=V1; As V1<V2, the first inverter INV output LOW voltage, then the second inverter output HIGH voltage, the cut-off of P1 pipe, the 3rd inverter output LOW voltage, the conducting of P2 pipe, at this moment VOUT=V2.Therefore, VOUT have selected a voltage higher in the middle of V1 and V2 as its output voltage.If VOUT end needs large driving force, the size of P1 and P2 pipe suitably can be increased.
The substrate of P1 and P2 is not connected to respective source, but be connected to respective drain terminal, be because: first, when circuit start, the on off state of P1 and P2 is not also determined, V1 can produce leakage current by the substrate of P1 (V2 can by the substrate of P2) to VOUT end, for second and the 3rd inverter supply voltage is provided; The second, when circuit normally works, VOUT have selected a voltage higher in the middle of V1 and V2 as output voltage, and the substrate of P1 and P2 all links VOUT end, can prevent the mutual electric leakage between V1 and V2.
First inverter INV1 is by the 7th PMOS P7,7th NMOS tube N7 composition, the source electrode of the first PMOS connects the positive supply of output VOUT as the first inverter self of voltage output circuit, and the output voltage selected by automatically selecting is powered, and does not affect logic operation result.
In the middle of V1 and V2, have the situation that an input voltage does not have, this is applicable equally based on the substrate change-over circuit of CMOS.When V1 there is no input voltage, V2 have an input voltage time, reference current source circuit does not start, N3 ends, and P4 grid is low level and conducting, and at this moment net1 is high level, INV output low level, first order inverter exports high level afterwards, second level inverter output low level, therefore P1 cut-off, P2 conducting, VOUT=V2; Otherwise, when V1 have input voltage, V2 there is no an input voltage time, reference current source circuit starts, N3 conducting, P4 grid is high level and ends, at this moment the input net1 of the first inverter INV1 is low level, and INV1 exports high level, afterwards first order inverter output low level, second level inverter exports high level, therefore P1 conducting, P2 ends, VOUT=V1.Thus, selecting properly when this circuit realiration independent current source is powered.
In sum, the present invention is based on the substrate change-over circuit of CMOS, when two input voltage values are close or one of them voltage does not exist, still can make correct selection, simultaneously, the present invention also obtains less image current by current mirroring circuit mirror image, and the resistance that can arrange wherein resistance makes the quiescent current of whole circuit less, reduces circuit power consumption, it is wide that visible the present invention has input voltage range, area is little, and structure is simple, advantage low in energy consumption.
Above-described embodiment only illustrates technical conceive of the present invention and feature, its objective is and is person skilled in the art can be understood content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences done according to Spirit Essence of the present invention change or modify, and all should be encompassed within protection category of the present invention.
Claims (4)
1. based on the substrate change-over circuit of CMOS, for exporting the higher person among the first supply voltage and second source voltage, be supplied to PMOS to use as underlayer voltage, it is characterized in that, comprising: reference current source circuit, comparator circuit and high voltage selection circuit;
Described reference current source, is connected to the first supply voltage, produces a reference current, obtains the first image current and the second image current respectively in the first supply voltage domain and second source voltage domain mirror image;
Described comparator circuit, utilizes described first image current and described second image current as load, compares the size of the first supply voltage and second source voltage, and utilize the first inverter to carry out shaping to comparison value, export a comparison value;
Described high voltage selection circuit, is input as the comparison value of described comparator, selects an output higher in the first supply voltage and second source voltage.
2., as claimed in claim 1 based on the substrate change-over circuit of CMOS, it is characterized in that, described reference current source comprises: the first NMOS tube, the second NMOS tube and the first resistance, the second resistance; Second NMOS tube source connects the second resistance anode, and the first NMOS tube source connects the second resistance anode, the first resistance and the second resistance negativing ending grounding, and described first NMOS tube is connected the load input terminal of described comparator circuit with the drain terminal of the second NMOS tube.
3., as claimed in claim 2 based on the substrate change-over circuit of CMOS, it is characterized in that, described comparator circuit comprises: the 3rd PMOS, the 4th PMOS and the first inverter; 3rd PMOS source and substrate connect the first supply voltage, 4th PMOS source and substrate connect second source voltage, 3rd PMOS grid and drain electrode short circuit are also connected to the grid of the 4th PMOS, the drain electrode of the above the second NMOS tube is also received in the drain electrode of the 3rd PMOS, the drain electrode of the 4th PMOS connects drain electrode and first inverter input of the above the first NMOS tube, the output of the first inverter exports comparison value, and the power end of described first inverter is the output of described high voltage selection circuit.
4., as claimed in claim 1 based on the substrate change-over circuit of CMOS, described high voltage selection circuit comprises: the first PMOS, the 2nd PMOS and the second inverter and the 3rd inverter; First PMOS source connects the first supply voltage, and the second PMOS source connects second source voltage, and the drain terminal of the first and second PMOS and substrate are all connected to output voltage and as second and the 3rd supply voltage of inverter; The input that second inverter input connects the output of the first inverter, output connects the first PMOS grid and the 3rd inverter; The output of the 3rd inverter is connected to the grid of the second PMOS.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510183942.2A CN104767518A (en) | 2015-04-20 | 2015-04-20 | Substrate switching circuit based on CMOS |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510183942.2A CN104767518A (en) | 2015-04-20 | 2015-04-20 | Substrate switching circuit based on CMOS |
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| CN104767518A true CN104767518A (en) | 2015-07-08 |
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| CN201510183942.2A Pending CN104767518A (en) | 2015-04-20 | 2015-04-20 | Substrate switching circuit based on CMOS |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
| WO2018032538A1 (en) * | 2016-08-16 | 2018-02-22 | 深圳市华星光电技术有限公司 | Cmos inverter and electronic device applying same |
| CN108768381A (en) * | 2018-08-27 | 2018-11-06 | 珠海市中科蓝讯科技有限公司 | GPIO circuits and chip |
| CN110045779A (en) * | 2019-03-27 | 2019-07-23 | 华中科技大学 | A kind of voltage selecting circuit and method |
| CN113608569A (en) * | 2021-08-05 | 2021-11-05 | 广东合科泰实业有限公司 | Display screen driving IC |
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| CN1949121A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Double ring low differential voltage linear voltage stabilizer circuit |
| CN104133515A (en) * | 2014-07-09 | 2014-11-05 | 刘银 | PMOS transistor substrate selection circuit |
| CN104135149A (en) * | 2014-08-14 | 2014-11-05 | 西安电子科技大学 | Selectable error amplifier and voltage comparator multiplex circuit |
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- 2015-04-20 CN CN201510183942.2A patent/CN104767518A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1949121A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Double ring low differential voltage linear voltage stabilizer circuit |
| CN104133515A (en) * | 2014-07-09 | 2014-11-05 | 刘银 | PMOS transistor substrate selection circuit |
| CN104135149A (en) * | 2014-08-14 | 2014-11-05 | 西安电子科技大学 | Selectable error amplifier and voltage comparator multiplex circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018032538A1 (en) * | 2016-08-16 | 2018-02-22 | 深圳市华星光电技术有限公司 | Cmos inverter and electronic device applying same |
| CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
| CN108768381A (en) * | 2018-08-27 | 2018-11-06 | 珠海市中科蓝讯科技有限公司 | GPIO circuits and chip |
| CN108768381B (en) * | 2018-08-27 | 2024-01-23 | 深圳市中科蓝讯科技股份有限公司 | GPIO circuit and chip |
| CN110045779A (en) * | 2019-03-27 | 2019-07-23 | 华中科技大学 | A kind of voltage selecting circuit and method |
| CN113608569A (en) * | 2021-08-05 | 2021-11-05 | 广东合科泰实业有限公司 | Display screen driving IC |
| CN113608569B (en) * | 2021-08-05 | 2022-09-16 | 广东合科泰实业有限公司 | Display screen driving IC |
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Effective date of registration: 20160419 Address after: 201204 Zhang Heng road Shanghai, Pudong New Area Zhangjiang hi tech Park Lane 666 No. 2 floor 504-511 room 5 Applicant after: Shanghai Bright Power Semiconductor Co.,Ltd. Address before: West high tech Zone Fucheng Road in Chengdu city of Sichuan province 610000 399 No. 6 Building 1 unit 10 floor No. 2 Applicant before: Chengdu Minchuang Science & Technology Co., Ltd. |
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Address after: 5 room 504-511, room 2, Lane 666, Zhang Heng Road, Pudong New Area, China (Shanghai) free trade zone, Shanghai, China () Applicant after: Shanghai semiconducto Limited by Share Ltd Address before: 201204 Zhang Heng road Shanghai, Pudong New Area Zhangjiang hi tech Park Lane 666 No. 2 floor 504-511 room 5 Applicant before: Shanghai Bright Power Semiconductor Co.,Ltd. |
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Application publication date: 20150708 |