CN106292831B - The current mirror of adjustable mirror ratio - Google Patents
The current mirror of adjustable mirror ratio Download PDFInfo
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- CN106292831B CN106292831B CN201510260962.5A CN201510260962A CN106292831B CN 106292831 B CN106292831 B CN 106292831B CN 201510260962 A CN201510260962 A CN 201510260962A CN 106292831 B CN106292831 B CN 106292831B
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Abstract
The invention discloses a kind of current mirror of adjustable mirror ratio, including a current source, a mirror circuits, a feedback circuit and an adjustable element.Current source is producing a reference current；Mirror circuits have a first node and a section point, and first node is making one first mirrored current by, section point pass through one second mirrored current；Feedback circuit is coupled to mirror circuits, to make the voltage on first node and section point equal；And adjustable element is coupled to mirror circuits, and driven by an output of feedback circuit to provide a target output current.
Description
Technical field
The present invention is on a kind of current mirror, particularly a kind of current mirror of adjustable mirror ratio.
Background technology
Current mirror is widely used in Analogous Integrated Electronic Circuits.Current mirror produces output current, and this output current is mirror
Reference current and obtain.The present invention wishes adjustable mirror ratio between output current and reference current, so that output current has
There is accurate numerical value.
The content of the invention
According to one embodiment of the invention, a kind of current mirroring circuit is proposed.Current mirroring circuit includes a current source, a mirror
Circuit, a feedback circuit and an adjustable element.Current source is producing a reference current；Mirror circuits have a first node
And a section point, first node is making one first mirrored current by, section point lead to one second mirrored current
Cross；Feedback circuit is coupled to mirror circuits, to make the voltage on first node and section point equal；And adjustable element
Mirror circuits are coupled to, and are driven by an output of feedback circuit to provide a target output current.
According to another embodiment of the present invention, a kind of side to through a current mirror one target output current of generation is proposed
Method.The method of target output current is produced through current mirror to be included providing current mirror, and current mirror includes a current source, mirror electricity
Road, a feedback circuit and an adjustable element.Current source is producing a reference current；Mirror circuits have a first node and
One section point, first node is making one first mirrored current by, section point pass through one second mirrored current；
Feedback circuit is coupled to the mirror circuits, to make the voltage on the first node and the section point equal；It is and adjustable
Element is coupled to the mirror circuits, and is driven by an output of the feedback circuit to provide a target output current.
According to the further embodiment of the present invention, a kind of current mirroring circuit is proposed.Current mirroring circuit includes an electric current
Source, a mirror circuits, a feedback circuit and an output transistor.Current source is producing a reference current；Mirror circuits have
One first node and a section point, first node is making one first mirrored current by, section point to make one second
Mirrored current passes through；Feedback circuit is coupled to mirror circuits, to make the voltage on first node and section point equal；And
Output transistor is coupled to mirror circuits, and is driven by an output of feedback circuit to provide a target output current.
More preferably understand to have to the above-mentioned and other aspect of the present invention, special embodiment below, and coordinate institute's accompanying drawing
Formula elaborates.
Brief description of the drawings
Fig. 1 illustrates the circuit diagram of the conventional current mirror circuit according to an embodiment.
Fig. 2 is the computer artificial result of the mirror feature of Fig. 1 conventional current mirror circuit.
Fig. 3 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
Fig. 4 is the computer artificial result of the mirror feature of Fig. 3 current mirroring circuit.
Fig. 5 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
Fig. 6 A illustrate the drain-source of the offset voltage and P-type mos transistor according to Fig. 5 of an embodiment
Graph of a relation between electrode current.
Fig. 6 B illustrate the error of the relation shown in Fig. 6 A.
Fig. 7 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
Fig. 8 is the computer artificial result of the temperature compensation characteristic of Fig. 7 current mirroring circuit.
Fig. 9 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
Figure 10 is the computer artificial result of the temperature compensation characteristic of Fig. 9 current mirroring circuit.
Figure 11 is the Computer Simulation of the temperature compensation characteristic of the current mirroring circuit of Fig. 9 when room temperature reference current is offset
As a result.
Figure 12 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
Figure 13 is that the computer of the temperature compensation characteristic of the current mirroring circuit of Figure 12 when room temperature reference current is offset is imitated
True result.
Figure 14 illustrates the circuit diagram of the current mirroring circuit according to an embodiment.
【Symbol description】
100、300、500、700、900、1200、1400：Circuit
110、310、510、910：Current source
120、130、330、340、350、360、540、550：Node
210、410、610、640、810、1010、1110、1310：Abscissa
220、420、620、650、820、1020、1120、1320：Ordinate
230、240、430、440、630、660：Line
312、512：Mirror circuits
314、514：Feedback circuit
316：Output transistor
320、520、1430：Operational amplifier
516：Adjustable element
530：Adjustable-voltage source
710：Temperature independent voltage source
720：Temperature dependence voltage source
831、832、833、834、835、1031、1032、1033、1034、1035、1131、1132、1133、1134、
1135、1331、1332、1333、1334、1335：Curve
930：Voltage source
1410：Voltage counting circuit
1420：Zener diode
N0、N1、N2：N-type metal oxide semiconductor transistor
P0、P1、P2、P3、P4、P5、D1、D2：P-type mos transistor
R1：First resistor
R2：Second resistance
VDD：Supply voltage
IREF：Reference current
IOUT：Output current
M：The M factors
Embodiment
The present invention by following examples and can coordinate the detailed description of institute's accompanying drawings and apparent.In schema with implementing
In mode, same or analogous reference number is to represent same or similar part.
Fig. 1 illustrates the circuit diagram of the conventional current mirror circuit 100 (hereinafter referred to as " circuit 100 ") according to an embodiment.Electricity
Partly led including current source 110, N-type metal-oxide semiconductor (MOS) (NMOS) transistor N0 to N2 and p-type metal oxide on road 100
Body (PMOS) transistor P0 to P5.N-type metal oxide semiconductor transistor N0 includes drain electrode end, gate terminal and source terminal, its
Middle drain electrode end is coupled to reference current I caused by current source 110REF, gate terminal is coupled to drain electrode end, source terminal is coupled to reference
Voltage (such as ground connection).N-type metal oxide semiconductor transistor N1 includes drain electrode end, gate terminal and source terminal, wherein draining
End is coupled to node 120, gate terminal is coupled to N-type metal oxide semiconductor transistor N0 gate terminal, source terminal is coupled to
Ground.N-type metal oxide semiconductor transistor N2 includes drain electrode end, gate terminal and source terminal, and wherein drain electrode end is coupled to section
Point 130, gate terminal is coupled to N-type metal oxide semiconductor transistor N0 gate terminal and source terminal is coupled to ground.P-type
Metal oxide semiconductor transistor P0 includes source terminal, gate terminal and drain electrode end, and wherein source terminal is coupled to supply voltage VDD、
Gate terminal is coupled to node 120, drain electrode end is coupled to P-type mos transistor P2.P-type metal oxide is partly led
Body transistor P1 includes source terminal, gate terminal and drain electrode end, and wherein source terminal is coupled to supply voltage VDD, gate terminal be coupled to section
Point 120, drain electrode end are coupled to P-type mos transistor P3.P-type mos transistor P2 includes
Source terminal, gate terminal and drain electrode end, wherein source terminal are coupled to P-type mos transistor P0 drain electrode end, grid
Extremely it is coupled to node 130, drain electrode end is coupled to node 120.P-type mos transistor P3 include source terminal,
Gate terminal and drain electrode end, wherein source terminal are coupled to P-type mos transistor P1 drain electrode end, gate terminal coupling
Node 130 is coupled to node 130, drain electrode end.P-type mos transistor P4 include source terminal, gate terminal and
Drain electrode end, wherein source terminal are coupled to supply voltage VDD, gate terminal be coupled to node 120, drain electrode end be coupled to p-type metal oxidation
Thing semiconductor transistor P5.P-type mos transistor P5 includes source terminal, gate terminal and drain electrode end, wherein source
Extremely it is coupled to P-type mos transistor P4 drain electrode end, gate terminal is coupled to node 130, drain electrode end coupling
To external circuit (not illustrating) to export output current IOUT。
In circuit 100, each N-type metal oxide semiconductor transistor N0 to N2 and P-type mos
Transistor P0 to P5 all has the grid breadth length ratio (W/L) of 10 microns (μm)/10 micron (μm), and the M factors are all 1.Wherein, M
The factor is the number that unit transistor is in parallel in a transistor.
It is desirable that all N-type metal oxide semiconductor transistor N0 to N2 and P-type mos are brilliant
Body pipe P0 to P5 works in saturation region.In saturation region, the drain-source electrode current I of transistorDSIt is to be determined by following formula：
Wherein VGSFor the gate-source pole tension of transistor, VTHFor the threshold voltage (threshold voltage) of transistor,
μ is carrier mobility (charge-carrier mobility), CoxFor the gate oxide capacitance (gate in unit region
Oxide capacitance per unit area), M is the M factors, and W is grid width, and L is grid length.
Therefore, when all N-type metal oxide semiconductor transistor N0 to N2 and P-type mos are brilliant
When body pipe P0 to P5 works in saturation region, due to N-type metal oxide semiconductor transistor N0 to N2 gate-source pole tension VGS
It is all identical, so N-type metal oxide semiconductor transistor N0 to N2 drain-source electrode current IDSIt is all identical.Similarly, due to P
Type metal oxide semiconductor transistor P0, P1 and P4 gate-source pole tension VGSIt is all identical, so p-type metal oxide is partly led
Body transistor P0, P1 and P4 drain-source electrode current IDSIt is all identical.P-type mos transistor P2, P3 and P5's
Drain-source electrode current IDSP-type mos transistor P0, P1 and P4 drain-source electrode current I are same as respectivelyDS.Cause
This, each N-type metal oxide semiconductor transistor N0 to N2 and P-type mos transistor P0 to P5 all have
Have and be equal to reference current IREFDrain-source electrode current IDS.In this way, the mirror ratio of circuit 100 is 1:1, that is, output current
IOUTWith reference current IREFBetween ratio be 1:1.
However, work as reference current IREF(such as micromicroampere grade or smaller), P-type mos when small
Transistor P0 to P4 can leave saturation region and into linear zone.In linear zone, the drain-source electrode current I of transistorDSIt is by following
Formula is determined：
According to formula (2), in linear zone, the drain-source electrode current I of transistorDSNot only with gate-source pole tension VGSCorrelation,
With drain-source voltage VDSIt is related.Therefore, P-type mos transistor P0 VDS_P0With p-type metal oxide half
Conductor transistor P4 VDS_P4Between difference, P-type mos transistor P0 I will be causedDS_P0With p-type gold
Belong to oxide semi conductor transistor P4 IDS_P4Between difference.Such difference is error in the mirror ratio of circuit 100.
Fig. 2 is the computer artificial result of the mirror feature of circuit 100.In fig. 2, abscissa 210 represents reference current
IREF(ampere (A)), ordinate 220 represent ratio error (such as the error of mirror ratio is compared with its ideal situation).Line 230
It is the result emulated using fast-fast (MOS_FF) corner module (corner model), represents ratio error corresponding circuits 100
IREF.Fast-fast corner module (hereinafter referred to as " low-VTHDeflection corner ") assume all p-type metal oxides half in circuit 100
Conductor transistor and N-type metal oxide semiconductor transistor use minimum VTH' manufactured by s.Line 240 is to use slow-slow (MOS_
SS) the result that corner module is emulated, the I of ratio error corresponding circuits 100 is representedREF.Slow-slow corner module assumes circuit 100
In all P-type mos transistors and N-type metal oxide semiconductor transistor use highest VTH' manufactured by s.
As shown in Fig. 2 work as reference current IREFDuring less than 1.24 micromicroamperes (μ A), low-V is usedTHThe ratio error of deflection corner module
More than 0.8%.
Fig. 3 illustrates the circuit diagram of the current mirroring circuit 300 (hereinafter referred to as " circuit 300 ") according to an embodiment.Circuit 300
Including feedback path, make P-type mos transistor P0 and P1 drain-source electrode current equal, to reduce ratio mistake
Difference.
Fig. 3 is refer to, circuit 300 includes current source 310, mirror circuits 312, feedback circuit 314 and output transistor
316.Mirror circuits 312 include N-type metal oxide semiconductor transistor N0 to N2, P-type mos transistor
P0 to P3, P-type mos transistor P0 to P3 function are the mirrors transistor (mirroring of circuit 300
transistor).Feedback circuit 314 includes operational amplifier 320.Output transistor 316 includes P-type mos
Transistor P4.N-type metal oxide semiconductor transistor N0 includes drain electrode end, gate terminal and source terminal, and wherein drain electrode end couples
To reference current I caused by current source 310REF, gate terminal is coupled to drain electrode end, source terminal is coupled to reference voltage and (such as connect
Ground).N-type metal oxide semiconductor transistor N1 includes drain electrode end, gate terminal and source terminal, and wherein drain electrode end is coupled to node
330th, gate terminal is coupled to N-type metal oxide semiconductor transistor N0 gate terminal, source terminal is coupled to ground.N-type metal
Oxide semi conductor transistor N2 includes drain electrode end, gate terminal and source terminal, and wherein drain electrode end is coupled to node 340, gate terminal
It is coupled to N-type metal oxide semiconductor transistor N0 gate terminal, source terminal is coupled to ground.P-type metal oxide is partly led
Body transistor P0 includes drain electrode end, gate terminal and source terminal, and wherein source terminal is coupled to supply voltage VDD, gate terminal be coupled to section
Point 330, drain electrode end are coupled to node 350.P-type mos transistor P1 includes drain electrode end, gate terminal and source electrode
End, wherein source terminal are coupled to supply voltage VDD, gate terminal is coupled to node 330, drain electrode end is coupled to node 360.P-type metal
Oxide semi conductor transistor P2 includes drain electrode end, gate terminal and source terminal, and wherein source terminal is coupled to node 350, gate terminal
It is coupled to node 340, drain electrode end is coupled to node 330.P-type mos transistor P3 includes drain electrode end, grid
End and source terminal, wherein source terminal is coupled to node 360, gate terminal is coupled to node 340, drain electrode end is coupled to node 340.P
Type metal oxide semiconductor transistor P4 includes drain electrode end, gate terminal and source terminal, wherein source terminal be coupled to node 360,
Gate terminal is coupled to operational amplifier 320, drain electrode end is coupled to external circuit (not illustrating) to export output current IOUT.Computing
Amplifier 320 includes non-return end (symbol is "+"), backward end (symbol is "-") and output end, wherein non-return end is coupled to
Node 360, backward end are coupled to node 350, output end is coupled to P-type mos transistor P4 grid
Extremely.
Each N-type metal oxide semiconductor transistor N0 to N2 and P-type mos transistor P0 to P4
Width long (W/L) ratio all with 10 microns (μm)/10 micron (μm).The P-type mos transistor P1 M factors
MP1 is 2.The M factors of other transistors are 1, such as N-type metal oxide semiconductor transistor N0 to N2 and the oxidation of p-type metal
Thing semiconductor transistor P0, P2 to the P4 M factors are 1.In certain embodiments, P-type mos transistor P1
Including two unit transistor elements in parallel, and each N-type metal oxide semiconductor transistor N0 to N2 and p-type metal oxygen
Compound semiconductor transistor P0, P2 to P4 only includes a unit transistor element.In other embodiments, p-type metal aoxidizes
It is that other N-type metal-oxide semiconductor (MOS)s are brilliant that thing semiconductor transistor P1 has grid width W, its grid width W during fabrication
Twice of body pipe N0 to N2 and P-type mos transistor P0, P2 to P4 grid width is big.
The feedback path of operational amplifier 320 and P-type mos transistor P4 built-up circuits 300.Specifically
For, the non-return end of operational amplifier 320 receives P-type mos transistor P1 drain-source voltage VDS_P1。
The backward end of operational amplifier 320 receives P-type mos transistor P0 drain-source voltage VDS_P0.Computing is put
Big device 320 produces output voltage to drive P-type mos transistor P4.Output voltage and p-type metal oxide
Semiconductor transistor P0 drain-source voltage VDS_P0With P-type mos transistor P1 drain-source voltage
VDS_P1Between difference it is directly proportional.Work as VDS_P1>VDS_P0, output voltage is equal to G (VDS_P1-VDS_P0), wherein G is operation amplifier
The magnifying power of device 320.The output voltage of operational amplifier 320 is applied to P-type mos transistor P4 grid
End, thereby reduce the voltage of P-type mos transistor P4 source terminal.The output voltage of operational amplifier 320
It can pass through VDS_P1With VDS_P0Between difference and be adjusted until VDS_P1=VDS_P0.Therefore, operational amplifier 320 makes VDS_P1
And VDS_P0It is equal.
On the implementation, node 350 makes the first mirrored current by the way that the first mirrored current is P-type mos
Transistor P0 drain-source electrode current IDS_P0.Due to transistor N0, N1, P0 and P2 the M factors be 1, therefore the first mirrored current with
Reference current IREFIt is identical.In addition, node 360 makes the second mirrored current by the way that the second mirrored current is p-type metal oxide half
Conductor transistor P1 drain-source electrode current IDS_P1.As reference current IREFWhen small, P-type mos transistor
P0 and P1 work in linear zone, and MP1/MP0=2, according to formula (2), the second mirrored current is twice of the first mirrored current
Greatly.That is, IDS_P1=2IDS_P0=2IREF.Because P-type mos transistor P4 is coupled to node
360, the output current I that P-type mos transistor P4 is providedOUTIt is related to the second mirrored current.It is uncommon according to gram
Lotus husband current law (Kirchhoff ' s current law), in node 360, the second mirrored current is equal to N-type metal oxide
Semiconductor transistor N2 drain-source electrode current IDS_N2With P-type mos transistor P4 drain-source electrode currents IDS_P4
(namely output current IOUT) summation.That is, IDS_P1=IDS_N2+IOUT.Due to IDS_N2=IREF,IOUT=IDS_P1-
IDS_N2=IREF.Therefore, even if when P-type mos transistor P0 and P1 work in linear zone, output current
IOUTWith reference current IREFAlso can be identical.
Fig. 4 is the computer artificial result of the mirror feature of circuit 300.In Fig. 4, abscissa 410 represents reference current
IREF (ampere (A)), ordinate 420 represent ratio error.Line 430 is the result emulated using fast-fast corner module, is represented
The I of ratio error corresponding circuits 300REF.Line 440 is the result emulated using slow-slow corner module, represents ratio error pair
Answer the I of circuit 300REF.As shown in figure 4, only work as reference current IREFWhen training (nA) less than 550 nas, low-V is usedTHDeflection
The ratio error of corner module is more than 0.8%.
Fig. 5 illustrates the circuit diagram of the current mirroring circuit 500 (hereinafter referred to as " circuit 500 ") according to an embodiment.Circuit 500
Including adjustable element, adjustable element makes the mirror ratio of circuit 500 can tune to desired value, and mesh in feedback path
Scale value is not exclusively determined by the M factors of metal oxide semiconductor transistor.
Fig. 5 is refer to, circuit 500 includes current source 510, mirror circuits 512, feedback circuit 514 and adjustable element
516.Mirror circuits 512 include N-type metal oxide semiconductor transistor N0 to N2 and P-type mos crystal
Pipe P0 to P3, P-type mos transistor P0 to P3 function are the mirrors transistor of circuit 500.Feedback circuit
514 include operational amplifier 520.Adjustable element 516 includes P-type mos transistor D1 and D2 and can adjust
Voltage source 530.P-type mos transistor D1 and the D2 output transistor for acting as circuit 500.Current source
510th, N-type metal oxide semiconductor transistor N0 to N2, P-type mos transistor P0 to P3 and computing are put
The coupling mode of big device 520 is similar to current source 310, N-type metal oxide semiconductor transistor N0 to N2, P in circuit 300
Type metal oxide semiconductor transistor P0 to P3 and operational amplifier 320 coupling mode.Therefore, the detailed of relation is coupled
Description is not described here any more.
Compared to circuit 300, the p-type metal oxide that circuit 500 is located at circuit 300 including adjustable element 516 is partly led
Body transistor P4 position.Adjustable element 516 is coupled in the feedback path of circuit 500, to provide target output current.Tool
For body, operational amplifier 520 includes non-return end (symbol is "+"), backward end (symbol is "-") and output end, wherein
Non-return end is coupled to node 540, and node 540 is P-type mos transistor P3 source terminal, backward end coupling
To node 550, node 550 is that P-type mos transistor P0 drain electrode end, output end are coupled to p-type metal oxygen
Compound semiconductor transistor D2.P-type mos transistor D1 includes source terminal, gate terminal and drain electrode end, wherein
Source terminal is coupled to node 540, gate terminal is coupled to adjustable-voltage source 530, drain electrode end is coupled to external circuit (not illustrating)
To export output current IOUT.P-type mos transistor D2 includes source terminal, gate terminal and drain electrode end, wherein source
Extremely be coupled to node 540, gate terminal be coupled to can the output end of operational amplifier 520, drain electrode end be coupled to external circuit.P
Type metal oxide semiconductor transistor D1 and D2 are all driven by operational amplifier 520.Adjustable-voltage source 530 includes anode
(symbol is "+") and negative terminal (symbol is "-"), wherein anode is coupled to P-type mos transistor P2 grid
End, negative terminal are coupled to P-type mos transistor D1 gate terminal.
Each N-type metal oxide semiconductor transistor N0 to N2 and P-type mos transistor P0 to P3
Width long (W/L) ratio with 10 microns (μm)/10 micron (μm).N-type metal oxide semiconductor transistor N0 M factor MsN0For
4.P-type mos transistor P1 M factor MsP1For 5.The P-type mos transistor D1 M factors
MD1For 7.P-type mos transistor D2 M factor MsD2For 4.The M factors of other transistors are 1, that is, N-type
Metal oxide semiconductor transistor N1 and N2 and P-type mos transistor P0, P2 and P3 the M factors are
1。
On the implementation, node 550 makes the first mirrored current by the way that the first mirrored current is P-type mos
Transistor P0 drain-source electrode current IDS_P0, and IDS_P0=IREF/4.Node 540 makes the second mirrored current pass through the second mirror electricity
Flow the drain-source electrode current I for P-type mos transistor P1DS_P1, and IDS_P1=5IREF/4.According to Ke Xihe
Husband's current law, in node 540, the second mirrored current is equal to N-type metal oxide semiconductor transistor N2 drain-source electrode current
IDS_N2, P-type mos transistor D1 drain-source electrode current IDS_D1(namely output current IOUT) and p-type
Metal oxide semiconductor transistor D2 drain-source electrode current IDS_D2Summation.That is, IDS_P1=IDS_N2+IDS_D1+
IDS_D2.Because IDS_N2=IREF/4,IDS_D1+IDS_D2=IDS_P1-IDS_N2=5IREF/4-IREF/ 4=IREF。
Adjustable-voltage source 530 produces offset voltage VOS, offset voltage VOSApply brilliant in P-type mos
Body pipe D2 gate-source pole tension VGS_D2With P-type mos transistor D1 gate-source pole tension VGS_D1Between.Partially
Move voltage VOSIt is adjustable to obtain target output current Itarget.Offset voltage VOSWith target output current ItargetBetween
Relation can be obtained by following.
First, it is assumed that P-type mos transistor D1 and D2 work in saturation region.Therefore, according to formula
(1), each P-type mos transistor D1 and D2,
Wherein
Offset voltage VOSIn P-type mos transistor D1 gate-source pole tension VGS_D1With p-type metal oxygen
Compound semiconductor transistor D2 gate-source pole tension VGS_D2Between establish difference.Therefore, offset voltage VOSCan list below show,
In order that output current (namely P-type mos transistor D1 gate-source electrode current IDS_D1) etc.
In Itarget, IDS_D1I should be equal totarget.Due to IDS_D2=IREF-IDS_D1, IDS_D2=IREF-Itarget.In this way, formula (4) can be turned
Change into,
Therefore, according to formula (5), by adjusting VOS, circuit 500 can produce target output current Itarget.For example, when
IREF=12.6 micromicroamperes (μ A), pass through the configuration of adjustable element 516 as described above, VOSBeing adjustable to makes output current
IOUT=Itarget=10 micromicroamperes (μ A).Therefore, by adjusting offset voltage VOS, may achieve desired mirror ratio.
In circuit 500, the P-type mos transistor D1 and D2 M factors are not limited to 7 and 4 respectively, and
According to the application of circuit 500, it can be any integer.When P-type mos transistor D1 and D2 the M factors change
When, offset voltage VOSAlso it must correspond to and adjust.
In circuit 500, (namely the anode in adjustable-voltage source 530 and negative terminal exist the polarity in adjustable-voltage source 530
Coupling relation in circuit 500) reference current I can be based onREF, target output current ItargetAnd P-type mos
Transistor D1 and D2 the M factors and be determined.IfThe then anode in adjustable-voltage source 530
P-type mos transistor D2 gate terminal is coupled to, and the negative terminal in adjustable-voltage source 530 is coupled to p-type
Metal oxide semiconductor transistor D1 gate terminal, as shown in Figure 5.On the other hand, if
Then the polarity in adjustable-voltage source 530 is opposite.That is, the anode in adjustable-voltage source 530 is coupled to p-type metal oxygen
Compound semiconductor transistor D1 gate terminal, and the negative terminal in adjustable-voltage source 530 are coupled to P-type mos
Transistor D2 gate terminal.IfThen output current IDS_D1As target output current
Itarget.In this embodiment, i.e., the offset voltage V as caused by adjustable-voltage source 530OSFor 0.Therefore, adjustable-voltage source
530 polarity can be configured by one of above two mode.
Fig. 6 A illustrate the offset voltage V according to an embodimentOSWith P-type mos transistor D1 drain-source
Electrode current IDS_D1Between graph of a relation.In fig. 6, abscissa 610 represents offset voltage VOS(millivolt (mV)), and vertical seat
Mark 620 represents P-type mos transistor D1 drain-source electrode current IDS_D1(micromicroampere (μ A)).Line 630 represents inclined
Move voltage VOSWith P-type mos transistor D1 drain-source electrode current IDS_D1Between relation, it is by single order
Linear approximation (first-order linear approximation) is obtained.Fig. 6 B illustrate the skew electricity according to an embodiment
Press VOSWith P-type mos transistor D1 drain-source electrode current IDS_D1Between relation first-order linear it is approximate
Error.In fig. 6b, abscissa 640 represents offset voltage VOS(millivolt (mV)), and ordinate 650 are represented by first-order linear
The drain-source electrode current I that approximation is obtainedDS_D1Error (na train (nA)).Line 660 represents offset voltage VOSWith by single order line
Property the approximate P-type mos transistor D1 obtained drain-source electrode current IDS_D1Error between relation.
Fig. 7 illustrates the circuit diagram of the current mirroring circuit 700 (hereinafter referred to as " circuit 700 ") according to an embodiment.Circuit 700
Including temperature dependence voltage source (temperature dependent voltage source), so that the output electricity of circuit 700
Flow IOUTIt is independent (temperature independent) for temperature.That is, output current IOUTNot with circuit 700
Operation temperature (temperature namely when circuit 700 operates) and change.
Fig. 7 is refer to, circuit 700 includes current source 510, N-type metal oxide semiconductor transistor N0 to N2, p-type gold
Category oxide semi conductor transistor P0 is similar to circuit 500 to P3, D1 and D2 and operational amplifier 520, the element of the above.
Different from circuit 500, circuit 700 includes temperature independent voltage source 710 and temperature dependence voltage source 720, temperature independent electrical
Potential source 710 and temperature dependence voltage source 720 are located between P-type mos transistor D1 and D2.Temperature independent electrical
Potential source 710 produces room temperature offset voltage, and room temperature offset voltage is at room temperature to be adjustable, to obtain target output current.Temperature
Spend interdependent voltage source 720 and produce temperature dependence voltage, temperature dependence voltage is to compensate the change of output current, its output current
Caused by change is due to the change between room temperature and the operation temperature of circuit 700.
In circuit 700, current source 510 is temperature independent source.That is, I caused by current source 510REFWill not be with
The operation temperature of circuit 700 and change.However, some device parameters of the transistor of circuit 700, such as threshold voltage VTHAnd
Carrier mobility μ, change such as operation temperature.Lacking the situation of temperature dependence voltage source 720, even in room temperature
Lower output current IOUTReach desired value, when operation temperature is offset from room temperature, output current IOUTMay also can be inclined from desired value
Move.In order to keep IOUTTemperature is independent, and temperature dependence voltage source 720 produces temperature dependence voltage to compensate because temperature change institute
Caused by transistor the change that parameter is made.Relation between room temperature offset voltage, temperature dependence voltage and operation temperature T,
It can be drawn by following.
First, carrier mobility μ is temperature dependence, and it is represented by,
μ=μ0·(T/T0)-α (6)
Wherein T0For room temperature, μ0To be room temperature T when operation temperature0Carrier mobility, μ be operation temperature T carrier
Mobility, and the carrier mobility μ for the metal oxide semiconductor transistor that α is present invention mobility humidity index.
First order Taylor (first-order Taylor expansion) can be used to estimate for carrier mobility μ,
μ=μ0·(T/T0)-α=μ0·(1+ΔT/T0)-α
μ-1/2=μ0 -1/2·(1+ΔT/T0)α/2≈μ0 -1/2·[1+(α/2T0)·ΔT] (7)
Wherein Δ T=T-T0。
When convolution (4) and formula (7) are available,
Wherein VOSFor offset voltage, produced by it is combination temperature independent voltage source 710 and temperature dependence voltage source 720.
Assuming that P-type mos transistor D1 target drain-source electrode current (the namely target of circuit 700
Output current) it is I at room temperature10, and P-type mos transistor D2 target drain-source electrode current in room temperature
It is I down20.That is, at room temperature, IDS_D1=I10And IDS_D2=I20.So thatAnd
Then, formula (8) can by lower expression,
Offset voltage VOSCan be by room temperature offset voltage VOS0It is as follows and temperature coefficient TC is represented
VOS=VOS0·(1+TC·ΔT) (10)
Wherein VOS0For room temperature offset voltage, V caused by temperature independent voltage source 710OS0TC Δs T is the interdependent electricity of degree
Temperature dependence voltage caused by potential source 720, and TC are offset voltage VOSTemperature coefficient.
Comparison expression (9) and formula (10), room temperature offset voltage VOS0And temperature coefficient TC can following formula subrepresentation,
TC=α/2T0 (12)
According to formula (11), it is known that reference current IREF, room temperature offset voltage V can be determined according to formula (11)OS0To obtain room temperature
Under known target output current I10.That is, according to target output current I10, reference current IREF, unit area grid
Pole oxide capacitance Cox, width often than (W/L) and room temperature carrier mobility μ 0, room temperature offset voltage V can be determinedOS0.It is real one
Apply in example, as decision room temperature offset voltage VOS0When, it is assumed that CoxAnd μ 0 changes not as device is made, it is, CoxAnd μ 0
All it is consistent, will not changes because of different technology corners (process corners), such as typical case-typical corner
(MOS_TT corner), its all N-type metal oxide semiconductor transistor and P-type mos transistor
With typical VTH' s, typical VTH' s is in highest VTH' s and minimum VTH' between s, fast-fast corner (MOS_FF corner), its
All N-type metal oxide semiconductor transistors and P-type mos transistor have minimum VTH' s, it is slow-
Slow-speed angle (MOS_SS corner), its all N-type metal oxide semiconductor transistor and P-type mos
Transistor has highest VTH' s, fast-slow corner (MOS_FS corner), all N-type metal oxide semiconductor transistors
With minimum VTH' s, and all P-type mos transistors have highest VTH' s and slow-to-fast corner
(MOS_SF corner), all N-type metal oxide semiconductor transistors have highest VTH' s, and all p-type metal oxygens
Compound semiconductor transistor has minimum VTH’s.Once room temperature offset voltage VOS0After decision, room temperature offset voltage VOS0- will
Be it is fixed and will not with circuit 700 operation during temperature change and change.In addition, according to formula (12), due to temperature
Coefficient T C is uncorrelated in temperature change, VOS0TC will not also change with temperature.Therefore, during the operation of circuit 700, partially
Move voltage VOS=VOS0+VOS0In TC Δs T, unique variable is temperature difference T, its Δ T operation temperature T and room temperature T0 it
Between.Therefore, offset voltage VOSIt can change with temperature difference T, it can be used to compensate the crystalline substance because caused by temperature change
The change of the technological parameter of body pipe.
Fig. 8 is the computer artificial result of the temperature compensation characteristic of circuit 700.In fig. 8, abscissa 810 represents operation
Temperature T (DEG C), and ordinate 820 represent actual output current IOUTWith target output current I10Between output current error
Ierror(na trains (nA)).Curve 831 represents output current error Ierror(hereinafter referred to as " temperature-compensating misses respective operations temperature
Difference "), it is the result emulated using slow-slow (MOS_SS) corner model, it assumes p-type metal oxidation all in circuit 700
Thing semiconductor transistor and N-type metal oxide semiconductor transistor have highest VTH’s.Curve 832 represents that temperature-compensating misses
Difference, it is the result emulated using fast-slow (MOS_FS) corner model, it assumes that all N-type metal-oxide semiconductor (MOS)s are brilliant
Body pipe has minimum VTH' s and P-type mos transistor have highest VTH’s.Curve 833 represents temperature-compensating
Error, is the result emulated using typical case-typical (MOS_TT) corner model, and it assumes all N-type metal oxides half
Conductor transistor and P-type mos transistor have typical VTH' s, wherein typical VTH' s is in highest VTH' s with most
Low VTH' between s.Curve 834 represents temperature-compensating error, is the result emulated using slow-to-fast (MOS_SF) corner model, its
Assuming that all N-type metal oxide semiconductor transistors have highest VTH' s, and all P-type mos crystalline substance
Body pipe has minimum VTH’s.Curve 835 represents temperature-compensating error, is emulated using fast-fast (MOS_FF) corner model
As a result, all N-type metal oxide semiconductor transistors of its hypothesis and P-type mos transistor have minimum
VTH’s。
In simulation with during producing result as shown in Figure 8, IREFIt is set to 12.6 micromicroamperes (μ A), and according to
Formula (11) determines VOS0To meet I in T0out=I10=10uA, T0 are in the centre of the temperature simulation scope of each technology corner
Temperature spot.In addition, temperature dependence voltage VOS0TC Δs T is assumed to be and can not be adjusted.When fast-fast corner to be determined, slow-slow
When corner, fast-slow corner and slow-to-fast corner, in the parameter C of typical case-typical corner modeloxAnd μ is used to as these corners
CoxAnd μ.However, the temperature dependence voltage V determined in this wayOS0TC Δs T will not follow the trail of p-type metal oxide
The process variable of semiconductor transistor and N-type metal oxide semiconductor transistor.That is, device parameter such as CoxAnd μ
Change with device fabrication schedule, and also differed in different corner techniques, such as fast-fast corner, slow-slow corner, fast-slow
Corner and slow-to-fast corner.In these technology corners, CoxAnd μ difference may cause the change of temperature-compensating error.Therefore,
As shown in figure 8, curve 831 to 835 represents that the temperature-compensating error in different technology corners is all different.For example, when
When operation temperature is 120 DEG C, temperature-compensating error caused by fast-fast corner model is almost caused by other corner models
Twice of temperature-compensating error.From the point of view of other examples, when operation temperature is -40 DEG C, caused by slow-slow corner model
Temperature-compensating error is then higher than temperature-compensating error caused by other corner models.
During result as shown in Figure 8 is produced in simulation, CoxAnd μ can all change with different technology corners.So
And the present invention is not limited thereto.If CoxChange with different technology corners, and μ will not with different technology corners and
Change, then the temperature dependence voltage V determined based on typical case-typical corner modelOS0TC Δs T still will not follow the trail of technique
Parameter.Therefore, temperature-compensating error is all different in these technology corners.
Fig. 9 illustrates the circuit diagram of the current mirroring circuit 900 (hereinafter referred to as " circuit 900 ") according to an embodiment.Circuit 900
Including temperature dependence voltage source, made a variation with compensation temperature.
Fig. 9 is refer to, circuit 900 includes current source 910, N-type metal oxide semiconductor transistor N0 to N2, p-type gold
Belong to oxide semi conductor transistor P0 to P3, D1 and D2, operational amplifier 520 and voltage source 930.The current source of circuit 900
910th, N-type metal oxide semiconductor transistor N0 to N2, P-type mos transistor P0 to P3, D1 and D2,
The coupling mode of operational amplifier 520 and voltage source 930 is similar to the element of circuit 500.Each N-type metal-oxide semiconductor (MOS)
Transistor N0 to N2 and P-type mos transistor P0 has 10 microns (μm)/10 micron (μ to P3, D1 and D2
M) width long (W/L) ratio.N-type metal oxide semiconductor transistor N0 M factor MsN0For 4.P-type mos are brilliant
Body pipe P1 M factor MsP1For 5.P-type mos transistor D1 M factor MsD1For 7.P-type metal oxide is partly led
Body transistor D2 M factor MsD2For 4.The M factors of other transistors are 1, that is, N-type metal oxide semiconductor transistor N1
And N2 and P-type mos transistor P0, P2 and P3 the M factors are 1.
In circuit 900, current source 910 is temperature dependence current source, its caused reference current IREFCan be with operation temperature
Spend T change and change.Voltage source 930 is temperature independent voltage source, its caused offset voltage VOSWill not be with operation temperature
Spend T change and change.In order to keep IOUTTemperature is independent, and current source 910 is configured to provide reference current IREFWith compensation
Because the technological parameter of transistor produced by temperature change changes, wherein reference current IREFOperation temperature T can be based on and adjusted.
Reference current IREFIt can be drawn with operation temperature T by following formula.
First, it is assumed that temperature dependence reference current IREFIt is represented by,
IREF=I0[1+ΔT·TC] (13)
Wherein I0For in room temperature T0Reference current, I0Δ TTC is reference current I0Temperature dependence portion
Point, Δ T=T-T0And TC is reference current IREFTemperature coefficient.
At room temperature, IDS_D1=I10, IDS_D2=I20, and IREF=IDS_D1+IDS_D2=I10+I20.Therefore, IDS_D2It can represent
For,
Convolution (4) and formula (14), offset voltage VOSIt is represented by,
WhereinAnd
Convolution (7) and formula (15), offset voltage VOSIt is represented by,
In order to which offset voltage V is presentedOSTemperature is independent, and the formula relevant with single order Δ T must eliminate in formula (16).In order to disappear
Formula relevant with single order Δ T in formula (16) is gone, temperature coefficient TC can be set to,
Therefore, offset voltage VOS is represented by,
Therefore, in circuit 900, reference current I can be determined according to formula (13) and formula (17)REF, and can be determined according to formula (18)
Determine offset voltage VOS.Such as formula (13) and formula (17) finding, IREFIncluding temperature separate current I0And temperature dependence I0·ΔT·TC
Electric current, wherein temperature separate current I0To produce target output current, temperature dependence I at room temperature0Δ TTC electric currents are used
With compensation temperature.
Similar to Fig. 7 circuit 700, current source 910 can be realized by temperature independent current and temperature dependence current source.
In room temperature T0Under, temperature independent current produces reference current I0.Temperature dependence current source produces temperature dependence electric current I0·Δ
T·TC。
Figure 10 is the computer artificial result of the temperature compensation characteristic of circuit 900.In Fig. 10, abscissa 1010 represents behaviour
Make temperature T (DEG C), and ordinate 1020 represents actual output current IOUTWith target output current I10Between output current miss
Poor Ierror(na trains (nA)).Curve 1031 represents temperature-compensating error, and it is imitated using fast-fast (MOS_FF) corner model
Genuine result.Curve 1032 represents temperature-compensating error, and it is the result emulated using fast-slow (MOS_FS) corner model.
Curve 1033 represents temperature-compensating error, and it is the result emulated using typical case-typical (MOS_TT) corner model.Curve
1034 represent temperature-compensating error, are the results emulated using slow-to-fast (MOS_SF) corner model.Curve 1035 represents temperature
Error is compensated, is the result emulated using slow-slow (MOS_SS) corner model.
During result as shown in Figure 10 is produced in simulation, room temperature reference current I012.6 micromicroamperes (uA) are set as,
And offset voltage V is determined according to formula (18)OSI is met with the medium temperature point in the temperature simulation scope of each technology cornerout
=I10=10uA.Moreover, it is assumed that temperature dependence voltage I0Δ TTC is to be adjusted.According to formula (17), IREFTemperature
Coefficient T C and CoxAnd μ is uncorrelated, only with known parameters such as B1, B2, I0、I20、T0And α is related.That is, IREFTemperature
Interdependent part I0Δ TTC is less by process variables influence.Therefore, as Figure 10, temperature-compensating error will not be with different
Technology corner and change (as shown in Figure 8).In this way, circuit 900 includes temperature dependence current source 910, temperature-compensating mistake can be reduced
Change of the difference in different process corner.
Figure 11 is as room temperature reference current I0It is offset to I0'=90%I0When circuit 900 temperature compensation characteristic meter
Calculation machine simulation result.In fig. 11, abscissa 1110 represents that operation temperature T (DEG C), and ordinate 1120 represent output current
Error Ierror=IOUT-I10(na trains (nA)), wherein I10For 10 micromicroamperes (μ A), and IOUTIt is that formula (13) is based on according to IREF
And formula (17) is determined.Wherein the TC of formula (17) is according to original I0=12.6 μ A are determined, but the I of formula (13)0It is then I0'=
90%I0.Curve 1131 represents temperature-compensating error, and it is the result emulated using fast-fast (MOS_FF) corner model.
Curve 1132 represents temperature-compensating error, and it is the result emulated using fast-slow (MOS_FS) corner model.The table of curve 1133
Temperature displaying function compensates error, and it is the result emulated using typical case-typical (MOS_TT) corner model.Curve 1134 represents temperature
Error is compensated, is the result emulated using slow-to-fast (MOS_SF) corner model.Curve 1135 represents temperature-compensating error, is
The result emulated using slow-slow (MOS_SS) corner model.
Work as I0=12.6uA is offset to I0'=90%I0During=11.3uA, I0' it is more than target output current I10=10 μ A.
Although VOSPolarity and formula (17) and formula (18) inner I10And B1 values remain unchanged.But I20' 1.3uA is changed into from 2.6uA made
Into corresponding B2 ' valuesDiminish.By I20' with B2 ' substitute into formula (17) and formula (18) corresponding I can be obtained0' WithBut VOS' and TC ' is both greater than
Corresponding I0VOSWith TC.Output current error I shown in this phenomenon explanation figure 11errorThe temperature range scope from -40 DEG C to 40 DEG C
It is inside a negative temperature dependent characteristics.And in the output current error I of 125 DEG C of correspondences, five technology cornerserrorIt is dissipated into maximum.
Figure 12 illustrates the circuit diagram of the current mirroring circuit 1200 (hereinafter referred to as " circuit 1200 ") according to an embodiment.Circuit
1200 include P-type mos transistor P0 and P1, and its metal oxide semiconductor transistor P0 and P1 tools adjust
The M factors to compensate the I of skew0。
Figure 12 is refer to, circuit 1200 includes current source 910, N-type metal oxide semiconductor transistor N0 to N2, p-type
Metal oxide semiconductor transistor P0 is to P3, D1 and D2, operational amplifier 520 and voltage source 930, and its element is similar to electricity
The element on road 900.Different from circuit 900, P-type mos transistor P0 M factor MsP0For 3 and p-type
Metal oxide semiconductor transistor P1 M factor MsP1For 16.
Circuit 1200 is used in room temperature reference current I0It is offset to I0'=90%I0In the case of.As previously indicated,
Work as I0It is offset to I0'=90%I0When, IREF temperature dependence part also can according to 90% factor offset.This will cause
The temperature-compensating error of different process corner, particularly in high-temperature region.However, in circuit 1200, MP1/MP0Ratio adjusted
It is whole to 5/1 rather than 16/3 so that drift current I0' it is exaggerated 1.083 (=(16/3-1)/4) times.Therefore, 1.083I0' etc.
Original I in 97.49% (=1.083 × 0.9)0。
In circuit 1200, P-type mos transistor P0 and P1 the M factors are respectively 3 and 16.However,
The present invention is not limited thereto, and P-type mos transistor P0 and P1 the M factors can be according to room temperature reference current I0And
It is determined.For example, in order to adjust the P-type mos transistor P0 and P1 M factors, circuit 1200 may include
Metal oxide semiconductor switch (does not illustrate), is connected to each P-type mos transistor P0 and P1.Work as detecting
To I0Skew when, metal oxide semiconductor switch can be according to I0Skew adjustment P-type mos transistor P0
And the P1 M factors.
Figure 13 is as room temperature reference current I0It is offset to I0'=90%I0When circuit 1200 temperature compensation characteristic
Computer artificial result.In fig. 13, abscissa 1310 represents that operation temperature T (DEG C), and ordinate 1320 represent output electricity
Stream error Ierror=IOUT-I10(na trains (nA)), wherein I10For 10 micromicroamperes (μ A), and IOUTIt is according to IREFBased on formula (13)
And formula (17) is determined.Wherein the TC of formula (17) is according to original I0=12.6 μ A are determined, but the I of formula (13)0It is then I0'=
90%I0.Curve 1331 represents temperature-compensating error, and it is the result emulated using fast-fast (MOS_FF) corner model.
Curve 1332 represents temperature-compensating error, and it is the result emulated using fast-slow (MOS_FS) corner model.The table of curve 1333
Temperature displaying function compensates error, and it is the result emulated using typical case-typical (MOS_TT) corner model.Curve 1334 represents temperature
Error is compensated, is the result emulated using slow-to-fast (MOS_SF) corner model.Curve 1335 represents temperature-compensating error, is
The result emulated using slow-slow (MOS_SS) corner model.
As previously indicated, in circuit 1200, due to P-type mos transistor P0 and P1 M factor quilts
Adjustment is amplified to the I of skew0', therefore even if work as I0Skew, output current IOUTAlso I can be maintained at10.Therefore, Figure 13 curve
1331 to 1335 are similar to Figure 10 curve 1031 to 1035.That is compared to Figure 11, Figure 13 five technology corners in-
40 DEG C and numerically it is closer in 125 DEG C of temperature-compensating error.Such as mended in -40 DEG C and in 125 DEG C of maximum temperature
Difference is repaid, 36.22 nas that Figure 13 is reduced to by Figure 11 97.82 nas training are trained.
Figure 14 illustrates the circuit diagram of the current mirroring circuit 1400 (hereinafter referred to as " circuit 1400 ") according to an embodiment.Circuit
1400 include voltage counting circuit, to realize the voltage source 530 of circuit 500.
Figure 14 is refer to, circuit 1400 includes current source 510, N-type metal oxide semiconductor transistor N0 to N2, p-type
Metal oxide semiconductor transistor P0 is to P3, D1 and D2, operational amplifier 520 and voltage counting circuit 1410.Current source
510th, N-type metal oxide semiconductor transistor N0 to N2, P-type mos transistor P0 to P3, D1 and D2,
Similar component of the operational amplifier 520 similar to Fig. 5 circuit 500.
Voltage counting circuit 1410 is connected to P-type mos transistor D2 gate terminal and p-type metal oxygen
Between compound semiconductor transistor D1 gate terminal.Voltage counting circuit 1410 include Zener diode 1420, first resistor R1,
Second resistance R2 and operational amplifier 1430.Zener diode 1420 includes first end and the second end, and wherein first end is coupled to
P-type mos transistor D2 gate terminal, the second end are coupled to first resistor R1.First resistor R1 includes first
End and the second end, wherein first end are coupled to the second end of Zener diode 1420, and the second end is coupled to second resistance R2.Second
Resistance R2 is adjustable resistance, and is coupled to first resistor R1, the coupling of the second end including first end and the second end, wherein first end
To P-type mos transistor D1 gate terminal.Operational amplifier 1430 include non-return end (symbol is "+"),
Backward end (symbol is "-") and output end, wherein non-return end is coupled to P-type mos transistor D2 grid
End, backward end are coupled to first resistor R1 the second end, output end is coupled to P-type mos transistor D1 grid
Extremely.
The function of voltage counting circuit 1410 is adjustable-voltage source, and it produces offset voltage VOS, applied to p-type metal oxygen
Between compound semiconductor transistor D1 and D2.Offset voltage VOSCan by following expression,
Wherein R1For first resistor R1Impedance, R2For second resistance R2Impedance and VZFor collapsing for Zener diode 1420
Routed voltage.Due to second resistance R2For adjustable resistance, therefore it can pass through adjustment second resistance R2Impedance adjust VOS.Citing
For, VOSIt can be adjusted according to formula (5), so that the output current I of circuit 1400OUTCan be desired value Itarget。
Circuit 300,500,700,900,1200 and 1400 is metal oxide semiconductor circuit.However, the present invention is not
It is limited to metal oxide semiconductor circuit, can applies to field-effect transistor (FET) circuit, bipolar junction transistor (BJT) circuit, double
Pole complementary metal oxide semiconductor (BiCMOS) circuit.
Current mirror disclosed by the embodiment of the present invention can be applied to the circuit system of accurate source electric current, such as relaxation vibration
Device circuit and current comparator etc..
In summary, although the present invention is disclosed above with embodiment, so it is not limited to the present invention.Institute of the present invention
Has usually intellectual in category technical field, without departing from the spirit and scope of the present invention, when various changes and profit can be made
Decorations.Protection scope of the present invention has not limited because of the description of embodiment, when regarding appended claims scope institute circle
Fixed is defined.
Claims (9)
1. a kind of current mirror, including：
One current source, to produce a reference current；
One mirror circuits, have a first node and a section point, the first node to make one first mirrored current by,
The section point is passing through one second mirrored current；
One feedback circuit, the mirror circuits are coupled to, to make the voltage on the first node and the section point equal；And
One adjustable element, is coupled to the mirror circuits, and is driven by an output of the feedback circuit defeated with one target of offer
Go out electric current；
Wherein, the adjustable element includes：
One first output transistor, is coupled to the section point, to export the target output current；
One second output transistor, the section point is coupled to, and is driven by the output of an operational amplifier；And
One adjustable-voltage source, be coupled to the gate terminal of first output transistor and second output transistor gate terminal it
Between, to produce an offset voltage to provide the target output current.
2. current mirror according to claim 1, wherein the adjustable-voltage source are according to a carrier mobility, a unit area
The gate oxide capacitance in domain, a breadth length ratio of first output transistor and second output transistor, the target output current,
The M factors of the M factors and second output transistor of the reference current and first output transistor produce the offset voltage；
And according to the target output current, the reference current, the M factors of first output transistor and second output transistor
The M factors configure the polarity in the adjustable-voltage source, the wherein adjustable-voltage source produces a room temperature offset voltage, the room temperature
Offset voltage provides the target output current, and a temperature dependence offset voltage at room temperature, with compensation because a temperature becomes
The change of the target output current caused by changing.
3. current mirror according to claim 2, wherein the adjustable-voltage source are according to the gate oxidation electricity of a unit area
Appearance, a breadth length ratio of first output transistor and second output transistor, a room temperature carrier mobility, target output
Electric current, the reference current, that the M factors of the M factors of first output transistor and second output transistor produce the room temperature is inclined
Move voltage, the gate oxide capacitance of the unit area and the room temperature carrier mobility at least one with different technique
Corner and change；And
The adjustable-voltage source is according to the room temperature offset voltage, the difference and a temperature coefficient of an operation temperature and a room temperature
The temperature dependence offset voltage is produced, the wherein temperature coefficient is the humidity index and the room temperature according to a carrier mobility
Determined.
4. the offset voltage caused by current mirror according to claim 1, wherein the adjustable-voltage source is that temperature is only
It is vertical, and
The reference current caused by the current source is temperature dependence, with compensation because the target caused by a temperature change is defeated
Go out the change of electric current, and wherein the current source produces a room temperature reference current and a temperature dependence reference current, the current source root
The temperature dependence is produced with reference to electricity according to the room temperature reference current, an operation temperature and a difference of a room temperature and a temperature coefficient
Stream, and
A humidity index, the room temperature, the reference current, target that the temperature coefficient is relevant to a carrier mobility export electricity
Stream, the gate oxide capacitance of the carrier mobility, a unit area, first output transistor the M factors and this is second defeated
Go out the M factors of transistor.
5. current mirror according to claim 1, the wherein mirror circuits include one first mirrors transistor and one second mirror
Transistor is penetrated, first mirrors transistor is coupled to the first node, and second mirrors transistor is coupled to the section point,
The M factors of first mirrors transistor and the M factors of second mirrors transistor are to compensate the reference at room temperature
One skew of electric current.
6. a kind of method that a target output current is produced through a current mirror, including：
The current mirror is provided, comprising：
One current source, to produce a reference current；
One mirror circuits, have a first node and a section point, the first node to make one first mirrored current by,
The section point is passing through one second mirrored current；
One feedback circuit, the mirror circuits are coupled to, to make the voltage on the first node and the section point equal；And
One adjustable element, is coupled to the mirror circuits, and is driven by an output of the feedback circuit defeated with one target of offer
Go out electric current；
Wherein, the adjustable element further includes：
One first output transistor is provided, is coupled to the section point, to export the target output current；
One second output transistor is provided, is coupled to the section point, and driven by the output of an operational amplifier；And
One adjustable-voltage source is provided, is coupled to the gate terminal of first output transistor and the grid of second output transistor
Between end, to produce an offset voltage.
7. the method according to claim 6 that a target output current is produced through a current mirror, further includes and is carried according to one
Flow transport factor, the gate oxide capacitance of a unit area, first output transistor and second output transistor one is wide
Long ratio, the target output current, the reference current and the M factors of first output transistor and the M of second output transistor
The factor produces the offset voltage；
And the method that the described current mirror of transmission one produces a target output current, further include according to the target output current, be somebody's turn to do
The M factors of reference current, the M factors of first output transistor and second output transistor configure the adjustable-voltage source
One polarity；
The method that the described current mirror of transmission one produces a target output current, further include adjust the offset voltage with compensate due to
The change of the target output current caused by one temperature change.
8. the method according to claim 6 that a target output current is produced through a current mirror, wherein adjusting the skew
Voltage further includes：
A room temperature offset voltage is adjusted, to provide the target output current at room temperature；And
A temperature dependence offset voltage is adjusted, to compensate due to the change of the target output current caused by the temperature change.
9. the method according to claim 6 that a target output current is produced through a current mirror, further includes and adjusts the electricity
Reference current caused by stream source, to compensate due to the change of the target output current caused by a temperature change；
Wherein the current source includes a room temperature reference current and a temperature dependence reference current,
Adjusting the reference current includes the difference and a temperature according to the room temperature reference current, an operation temperature and a room temperature
The coefficient adjustment temperature dependence reference current.
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| US5680037A (en) * | 1994-10-27 | 1997-10-21 | Sgs-Thomson Microelectronics, Inc. | High accuracy current mirror |
| CN101498950A (en) * | 2008-12-25 | 2009-08-05 | 四川登巅微电子有限公司 | Current mirror circuit with feedback regulation and method thereof |
| CN101893910A (en) * | 2010-07-28 | 2010-11-24 | 苏州日月成科技有限公司 | Self-adaptive current mirror |
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| JP2012216034A (en) * | 2011-03-31 | 2012-11-08 | Toshiba Corp | Constant current source circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5680037A (en) * | 1994-10-27 | 1997-10-21 | Sgs-Thomson Microelectronics, Inc. | High accuracy current mirror |
| CN101498950A (en) * | 2008-12-25 | 2009-08-05 | 四川登巅微电子有限公司 | Current mirror circuit with feedback regulation and method thereof |
| CN101893910A (en) * | 2010-07-28 | 2010-11-24 | 苏州日月成科技有限公司 | Self-adaptive current mirror |
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