CN221202533U - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN221202533U CN221202533U CN202323109716.9U CN202323109716U CN221202533U CN 221202533 U CN221202533 U CN 221202533U CN 202323109716 U CN202323109716 U CN 202323109716U CN 221202533 U CN221202533 U CN 221202533U
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- nmos tube
- tube
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- pmos
- power
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- 239000003990 capacitor Substances 0.000 claims description 5
- 238000007493 shaping process Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 8
- 230000003068 static effect Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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Abstract
The power-on reset circuit comprises a starting PMOS tube, wherein a source electrode of the starting PMOS tube is connected with a power supply, a grid electrode of the starting PMOS tube is connected with grid electrodes of a pull-down NMOS tube and a first load NMOS tube, the pull-down NMOS tube and the first load NMOS tube are connected in a current mirror mode, the pull-down NMOS tube is in a diode connection mode, a drain electrode of the starting PMOS tube is connected with a drain electrode of the first load NMOS tube, and source electrodes of the pull-down NMOS tube and the first load NMOS tube are grounded; the source electrode of the output NMOS tube is grounded through a second load NMOS tube, and the grid electrode of the second load NMOS tube is connected with the grid electrode of the first load NMOS tube. The power-on reset circuit has small quiescent current required by normal operation, and is suitable for power-on reset application scenes with weak low power supply voltage and power supply carrying capacity.
Description
Technical Field
The utility model belongs to the field of electronic circuits, and particularly relates to a power-on reset circuit.
Background
The power-on reset circuit is a circuit module used for outputting a starting signal to each circuit module in the integrated circuit when the circuit is powered on.
In the application scenario of weak low power supply voltage and power supply carrying capacity, the power-on reset circuit is unstable in the power-on reset working process, if larger static current occurs in the power-on reset process, the power supply voltage is easy to power down, so that the power-on reset process is interrupted, and the static current in the power-on reset process needs to be reduced as much as possible.
Disclosure of utility model
In order to overcome the defects in the prior art, the utility model discloses a power-on reset circuit.
The power-on reset circuit comprises a starting PMOS tube, wherein a source electrode of the starting PMOS tube is connected with a power supply, a grid electrode of the starting PMOS tube is connected with grid electrodes of a pull-down NMOS tube and a first load NMOS tube, the pull-down NMOS tube and the first load NMOS tube are connected in a current mirror mode, the pull-down NMOS tube is in a diode connection mode, a drain electrode of the starting PMOS tube is connected with a drain electrode of the first load NMOS tube, and source electrodes of the pull-down NMOS tube and the first load NMOS tube are grounded;
The output stage of the power-on reset circuit comprises an output PMOS tube and an output NMOS tube which are connected in an inverter mode, wherein the source electrode of the output NMOS tube is grounded through a second load NMOS tube, and the grid electrode of the second load NMOS tube is connected with the grid electrode of the first load NMOS tube.
Preferably, the power supply comprises a power supply, a pull-down NMOS tube, a first control PMOS tube, a second control PMOS tube, a control NMOS tube and a switch-on control circuit, wherein the power supply is connected with the pull-down NMOS tube; and a current limiting resistor is connected between the grid electrode of the pull-down NMOS tube and a power supply.
Preferably, the output stage is further connected with a shaping circuit, and the shaping circuit comprises a schmitt trigger connected with an output end, namely, an output PMOS tube drain electrode, wherein an input end and an output end of the schmitt trigger are respectively connected with an MOS capacitor.
The power-on reset circuit has small quiescent current required by normal operation, and is suitable for power-on reset application scenes with weak low power supply voltage and power supply carrying capacity.
Drawings
Fig. 1 is a schematic diagram of a power-on reset circuit according to an embodiment of the utility model.
Description of the embodiments
The following describes the embodiments of the present utility model in further detail with reference to the accompanying drawings.
The power-on reset circuit comprises a starting PMOS tube, wherein a source electrode of the starting PMOS tube is connected with a power supply, a grid electrode of the starting PMOS tube is connected with grid electrodes of a pull-down NMOS tube and a first load NMOS tube, the pull-down NMOS tube and the first load NMOS tube are connected in a current mirror mode, the pull-down NMOS tube is in a diode connection mode, a drain electrode of the starting PMOS tube is connected with a drain electrode of the first load NMOS tube, and the source electrodes of the pull-down NMOS tube and the first load NMOS tube are grounded.
The output stage of the power-on reset circuit comprises an output PMOS tube and an output NMOS tube which are connected in an inverter mode, wherein the source electrode of the output NMOS tube is grounded through a second load NMOS tube, and the grid electrode of the second load NMOS tube is connected with the grid electrode of the first load NMOS tube.
As shown in fig. 1, when the power VCC is powered on, since the gate N1 and the drain of the pull-down NMOS transistor are connected to form a diode connection, the gate of the pull-down NMOS transistor N1 is grounded, the voltage difference between the gate and source of the start PMOS transistor P2 is greater than the turn-on threshold voltage of the start PMOS transistor, the start PMOS transistor P2 is turned on, the current limiting resistor turns on the first load NMOS transistor and the second load NMOS transistor after the power VCC is powered on, and the start PMOS transistor and the first load NMOS transistor N2, and the output PMOS transistor P3 and the output NMOS transistor N5 connected in an inverter form are connected in an inverter form, and a high-level valid power-on reset signal is output at the output end, i.e., the drain of the output PMOS transistor.
The power-on reset circuit further comprises a turn-off control circuit, the turn-off control circuit is used for controlling the system to be turned off in a power-off state, the power-on reset circuit is prevented from outputting a power-on reset signal when the system is turned off, the turn-off control circuit comprises a first control PMOS tube connected between a power supply and a grid electrode of a pull-down NMOS tube, a second control PMOS tube connected between the grid electrode of the output PMOS tube and the power supply, and a control NMOS tube connected between the ground and the grid electrode of the pull-down NMOS tube, wherein a turn-off control end SD is directly connected with the grid electrodes of the control NMOS tube and the first control PMOS tube, and the turn-off control circuit is connected with the grid electrode of the second control PMOS tube through an inverter INV. A current limiting resistor R can be connected between the grid electrode of the pull-down NMOS tube and the drain electrode of the first control PMOS tube.
When the shutdown control end SD inputs a high level, the first control PMOS tube P1 is turned off, the second control PMOS tube P4 is turned on, the control NMOS tube N4 is turned on, the potential of the grid electrode of the pull-down NMOS tube is zero and turned off, the grid electrode of the output PMOS tube is high level, and a low level signal indicating that the power-on reset is invalid is output. In the power-up process, the turn-off control end SD is usually connected to a pull-down device, so that the turn-off control end SD is at a low level in the power-up process, the first control PMOS transistor P1 is turned on, and a bias voltage is provided to the pull-down NMOS transistor N1 through the current-limiting resistor R.
In the power-on reset signal generation process, due to the connection mode of the inverter, only static current is needed to be provided at the current-limiting resistor, the static current is only used for driving the grid electrodes of the two load NMOS tubes, and the power-on reset can normally work only by extremely low static current by increasing the resistance value of the current-limiting resistor R, for example, by adopting a high-resistance MOS resistor.
In the specific embodiment shown in fig. 1, the output stage is further connected with a shaping circuit, and includes a schmitt trigger SMIT connected to the output end, i.e., the drain electrode of the output PMOS tube, where the input end and the output end of the schmitt trigger are respectively connected with a MOS capacitor, the MOS capacitor delays the output signal, the schmitt trigger corrects the edge of the output signal to make it steeper, and the MOS capacitor is used to adjust the level logic conversion time of the rising edge and the falling edge, and output a high-level effective power-on reset signal through the output end POR of the power-on reset circuit by the inverter INV.
The foregoing description of the preferred embodiments of the present utility model is not obvious contradiction or on the premise of a certain preferred embodiment, but all the preferred embodiments can be used in any overlapped combination, and the embodiments and specific parameters in the embodiments are only for clearly describing the utility model verification process of the inventor and are not intended to limit the scope of the utility model, and the scope of the utility model is still subject to the claims, and all equivalent structural changes made by applying the specification and the content of the drawings of the present utility model are included in the scope of the utility model.
Claims (3)
1. The power-on reset circuit is characterized by comprising a starting PMOS tube, wherein a source electrode of the starting PMOS tube is connected with a power supply, a grid electrode of the starting PMOS tube is connected with grid electrodes of a pull-down NMOS tube and a first load NMOS tube, the pull-down NMOS tube and the first load NMOS tube are connected in a current mirror mode, the pull-down NMOS tube is in a diode connection mode, a drain electrode of the starting PMOS tube is connected with a drain electrode of the first load NMOS tube, and source electrodes of the pull-down NMOS tube and the first load NMOS tube are grounded;
The output stage of the power-on reset circuit comprises an output PMOS tube and an output NMOS tube which are connected in an inverter mode, wherein the source electrode of the output NMOS tube is grounded through a second load NMOS tube, and the grid electrode of the second load NMOS tube is connected with the grid electrode of the first load NMOS tube.
2. The power-on reset circuit of claim 1, further comprising a turn-off control circuit comprising a first control PMOS connected between the power supply and the gate of the pull-down NMOS, a second control PMOS connected between the gate of the output PMOS and the power supply, and a control NMOS connected between the ground and the gate of the pull-down NMOS, wherein the turn-off control terminal is directly connected to the gates of the control NMOS and the first control PMOS, the gate of the second control PMOS is connected through an inverter, and a current limiting resistor is connected between the gate of the pull-down NMOS and the drain of the first control PMOS.
3. The power-on reset circuit as recited in claim 1 wherein said output stage is further connected with a shaping circuit comprising a schmitt trigger connected to an output terminal, i.e., a drain of an output PMOS transistor, said schmitt trigger having an input terminal and an output terminal connected to MOS capacitors, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323109716.9U CN221202533U (en) | 2023-11-17 | 2023-11-17 | Power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323109716.9U CN221202533U (en) | 2023-11-17 | 2023-11-17 | Power-on reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221202533U true CN221202533U (en) | 2024-06-21 |
Family
ID=91495773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202323109716.9U Active CN221202533U (en) | 2023-11-17 | 2023-11-17 | Power-on reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221202533U (en) |
-
2023
- 2023-11-17 CN CN202323109716.9U patent/CN221202533U/en active Active
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