JP2017055299A - Electrostatic protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit capable of suppressing malfunction and sufficiently discharging an ESD surge.SOLUTION: An electrostatic protection circuit includes: a first trigger circuit that is connected between a first power supply line and a second power supply line, includes a capacitor and a resistor that constitute a first CR circuit having a first time constant, and outputs a first trigger signal; a buffer circuit that outputs a driving signal to a signal line in response to the first trigger signal; a shunt circuit that has a main current path connected between the first power supply line and the second power supply line and responds to the driving signal; and a second trigger circuit that is connected between the signal line and the first power supply line or between the signal line and the second power supply line, includes a capacitor and a resistor that constitute a second CR circuit having a second time constant smaller than the first time constant, and outputs a second trigger signal. The second trigger signal disconnects the main current path of the shunt circuit.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to an electrostatic protection circuit.

  2. Description of the Related Art Conventionally, various protection circuits for ESD (Electrostatic Discharge) have been proposed. ESD refers to a discharge from a charged human or machine to a semiconductor device, a discharge from a charged semiconductor device to a ground potential, or the like. When ESD occurs in a semiconductor device, a large amount of charge flows from the terminal as a current and flows into the semiconductor device, and the charge generates a high voltage inside the semiconductor device, causing breakdown of internal elements and failure of the semiconductor device. cause.

  A typical example of the electrostatic protection circuit is an RCT (RC Triggered) MOS circuit. A trigger circuit composed of a series circuit of a resistor and a capacitor is connected between the power supply terminals, and a discharge MOS transistor is driven using the voltage at the connection point of the resistor and the capacitor as a trigger signal. Since the on-time of the discharging MOS transistor is determined by the time constant of the trigger circuit, it is necessary to set the time constant to sufficiently discharge the ESD surge. However, if the time constant becomes long, the trigger circuit responds to voltage fluctuations when the power is turned on or fluctuations in the power supply voltage accompanying the operation of the internal circuit, and the discharge MOS transistor can malfunction despite not being an ESD surge. There is sex. If the discharging MOS transistor malfunctions when the power is turned on, there is a problem that the power supply voltage does not rise sufficiently, which may cause malfunction of the internal circuit. In addition, if the trigger circuit responds to fluctuations in the power supply voltage and the discharge MOS transistor is turned on for a long time, the discharge MOS transistor itself may be destroyed. is there.

Japanese Patent Application Laid-Open No. 2014-207412 JP 2014-241537 A Japanese Patent No. 5404343

  One embodiment aims to provide an electrostatic protection circuit capable of suppressing malfunction and sufficiently discharging an ESD surge.

  According to one embodiment, the electrostatic protection circuit includes a capacitor and a resistor connected between the first power supply line and the second power supply line and constituting a first CR circuit having a first time constant. A first trigger circuit that outputs one trigger signal; A buffer circuit for outputting a drive signal to the signal line in response to the first trigger signal; A main current path is connected between the first power supply line and the second power supply line, and a shunt circuit responding to the drive signal is provided. A second CR circuit connected between the signal line and the first power supply line or between the signal line and the second power supply line and having a second time constant smaller than the first time constant. And a second trigger circuit that outputs a second trigger signal. The second trigger signal interrupts the main current path of the shunt circuit.

FIG. 1 is a diagram illustrating an electrostatic protection circuit according to the first embodiment. FIG. 2 is a diagram illustrating an electrostatic protection circuit according to the second embodiment. FIG. 3 is a diagram illustrating an electrostatic protection circuit according to the third embodiment. FIG. 4 is a diagram illustrating the electrostatic protection circuit of the fourth embodiment. FIG. 5 is a diagram illustrating an electrostatic protection circuit according to a fifth embodiment. FIG. 6 is a diagram illustrating an electrostatic protection circuit according to a sixth embodiment.

  Hereinafter, an electrostatic protection circuit according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a diagram illustrating an electrostatic protection circuit according to the first embodiment. The electrostatic protection circuit of the present embodiment includes a first power supply terminal 1 and a second power supply terminal 2. A first power supply line 3 is connected to the first power supply terminal 1. A second power supply line 4 is connected to the second power supply terminal 2. An internal circuit (not shown) is connected between the first power supply line 3 and the second power supply line 4, but is omitted.

  A first trigger circuit 10 having a first time constant τ 1 is connected between the first power supply line 3 and the second power supply line 4. The first trigger circuit 10 outputs a first trigger signal in response to a power supply voltage applied between the first power supply line 3 and the second power supply line 4.

  The first trigger signal is supplied to the buffer circuit 11. The buffer circuit 11 outputs a drive signal to the signal line 5 in response to the first trigger signal.

  A shunt circuit 14 is connected between the first power supply line 3 and the second power supply line 4. The drive signal output to the signal line 5 is supplied to the shunt circuit 14. On / off of the shunt circuit 14 is controlled by a drive signal.

  A second trigger circuit 12 having a second time constant τ 2 is connected between the signal line 5 and the second power supply line 4. The second trigger circuit 12 outputs a second trigger signal in response to the voltage between the signal line 5 and the second power supply line 4.

  A switch circuit 13 is connected between the signal line 5 and the second power supply line 4. The second trigger signal of the second trigger circuit 12 is supplied to the switch circuit 13. On / off of the switch circuit 13 is controlled by the second trigger signal. The time constant τ 2 of the second trigger circuit 12 is set to a value smaller than the time constant τ 1 of the first trigger circuit 10.

  For example, the time constant τ1 of the first trigger circuit 10 is set to a value in consideration of the ESD test standard. In the ESD human body model (HBM), a test is performed in which a charge charged to 100 pF (picofarad) is discharged through a resistance of 1.5 kΩ (kiloohm). Therefore, the time constant τ1 of the first trigger circuit 10 is, for example, 6 to 7 of 150 nS in consideration of the time constant of 150 nS (nanosecond) due to the 100 pF capacitor and the resistance of 1.5 kΩ which is the ESD test standard. The double value is set to 1 μS (microseconds). This is because the ESD surge is sufficiently discharged by the shunt circuit 14.

  For example, the time constant τ2 of the second trigger circuit 12 is set to a value between 2 nS and 10 nS defined as the surge rise time in the human body model (HBM) of the ESD test standard. When the voltage applied between the signal line 5 and the second power supply line 4 has a rising earlier than the time constant τ 2 of the second trigger circuit 12, the second trigger circuit 12 causes the second trigger circuit 12 to A signal is supplied to the switch circuit 13 to turn on the switch circuit 13. When the switch circuit 13 is turned on, the signal line 5 and the second power supply line 4 are electrically connected, and the supply of the drive signal from the buffer circuit 11 to the shunt circuit 14 is blocked. As a result, the shunt circuit 14 is turned off. That is, the second trigger signal turns on the switch circuit 13 to cut off the main current path of the shunt circuit 14.

  For this reason, even if the time constant τ1 of the first trigger circuit 10 is set to a sufficiently large value, for example, the value of the rise time of the ESD surge that defines the time constant τ2 of the second trigger circuit 12 in the ESD test standard. By setting to, it is possible to avoid a situation in which a malfunction occurs in response to the fluctuation of the power supply voltage having a rising earlier than the ESD surge.

  According to the electrostatic protection circuit of this embodiment, the time constant τ1 of the first trigger circuit 10 is a large value, for example, 1 μS (microseconds) that is 6 to 7 times the time constant 150 nS defined in the ESD test standard. By setting to, the ESD surge can be sufficiently discharged. On the other hand, by setting the time constant τ2 of the second trigger circuit 12 to a value corresponding to 2 nS to 10 nS defined as the rise time of the ESD surge of the human body model of the ESD test standard, for example, the rise earlier than the ESD surge is achieved. It is possible to avoid a situation in which malfunction occurs in response to fluctuations in the power supply voltage.

(Second Embodiment)
FIG. 2 is a diagram illustrating a configuration of the electrostatic protection circuit according to the second embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the first trigger circuit 10 is configured by a CR circuit having a series circuit of a resistor 100 and a capacitor 101. The first trigger circuit 10 has a first time constant τ1. The first time constant τ1 is set by the values of the resistor 100 and the capacitor 101. The resistor 100 and the capacitor 101 are connected at the first common connection end 102. The first common connection terminal 102 is connected to the gate of the PMOS transistor 110 constituting the buffer circuit 11.

  The source of the PMOS transistor 110 is connected to the first power supply line 3, and the drain is connected to the second common connection terminal 112. The second common connection end 112 is connected to the second power supply line 4 via the resistor 111. As a result, the source / drain path which is the main current path of the PMOS transistor 110 is electrically connected between the first power supply line 3 and the second power supply line 4.

  The second common connection end 112 is connected to the signal line 5. The signal line 5 is connected to the gate of the NMOS transistor 140 constituting the shunt circuit 14. The drain of the NMOS transistor 140 is connected to the first power supply line 3, and the source is connected to the second power supply line 4. As a result, the source / drain path which is the main current path of the NMOS transistor 140 is electrically connected between the first power supply line 3 and the second power supply line 4.

  A second trigger circuit 12 is connected between the signal line 5 and the second power supply line 4. The second trigger circuit 12 includes a CR circuit having a series circuit of a capacitor 121 and a resistor 120. The second trigger circuit 12 has a second time constant τ2. The second time constant τ 2 is set by the values of the resistor 120 and the capacitor 121. The capacitor 121 and the resistor 120 are connected at the third common connection end 122. The third common connection terminal 122 is connected to the gate of the NMOS transistor 130 constituting the switch circuit 13, that is, the control terminal of the switch circuit 13, and the output signal of the second trigger circuit 12 is input to the switch circuit 13. .

  The drain of the NMOS transistor 130 is connected to the signal line 5, and the source is connected to the second power supply line 4. As a result, the source / drain path which is the main current path of the NMOS transistor 130 is electrically connected between the signal line 5 and the second power supply line 4.

  The ESD protection operation of this embodiment is as follows. When a positive surge is applied to the first power supply line 3 with respect to the second power supply line 4 and the rise time of this ESD surge is shorter than the first time constant τ1, the first trigger circuit 10 responds. Thus, a current flows transiently through the first trigger circuit 10. When the potential of the first common connection terminal 102 decreases beyond the threshold of the PMOS transistor 110 due to a voltage drop in the resistor 100 of the first trigger circuit 10, the PMOS transistor 110 is turned on. When the PMOS transistor 110 is turned on, the potential of the second common connection end 112 rises to a voltage obtained by subtracting the voltage drop due to the PMOS transistor 110 from the voltage of the first power supply line 3.

  The PMOS transistor 110 constituting the buffer circuit 11 is turned on / off in response to the trigger signal of the first trigger circuit 10, and the change in voltage generated at the first common connection terminal 102 is changed in the second power supply line 4. The signal is amplified to a change from the voltage to the voltage of the first power supply line 3 and supplied as a drive signal to the second common connection terminal 112, and thus to the signal line 5.

  When the rise of the voltage fluctuation generated between the signal line 5 and the second power supply line 4 is earlier than the second time constant τ2, the second trigger circuit 12 responds to the second trigger circuit 12 in a transient manner. Current flows through When the voltage drop across the resistor 120 of the second trigger circuit 12 exceeds the threshold value of the NMOS transistor 130, the NMOS transistor 130 is turned on. When the NMOS transistor 130 is turned on, the voltage of the signal line 5 is lowered to a voltage higher than the voltage of the second power supply line 4 by the voltage drop between the source and drain of the NMOS transistor 130. Since the voltage drop between the source and the drain when the NMOS transistor 130 is turned on is smaller than the threshold voltage for turning on the NMOS transistor 140, the NMOS transistor 140 is turned off when the NMOS transistor 130 is turned on.

  According to the present embodiment, the first trigger circuit 10 responds to the ESD surge and outputs the first trigger signal. The buffer circuit 11 amplifies the first trigger signal and supplies a drive signal to the signal line 5. In response to the drive signal, the NMOS transistor 140 of the shunt circuit 14 is turned on to discharge the ESD surge. On the other hand, when the rise of the voltage appearing on the signal line 5 is earlier than the time constant τ 2 of the second trigger circuit 12, the second trigger circuit 12 responds and the second trigger signal is supplied to the NMOS transistor 130. Then, the NMOS transistor 130 is turned on, and the NMOS transistor 140 of the shunt circuit 14 is turned off. Therefore, by setting the time constant τ2 of the second trigger circuit 12 to, for example, the rise time of the ESD surge specified in the ESD test standard, the shunt circuit against the fluctuation of the power supply voltage having the rise earlier than the ESD surge. The situation where 14 malfunctions can be avoided. The buffer circuit 11 can also be configured by a CMOS inverter (not shown) that amplifies the trigger signal of the first trigger circuit 10 and supplies the amplified signal to the signal line 5.

(Third embodiment)
FIG. 3 is a diagram illustrating an electrostatic protection circuit according to the third embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals, and redundant description is performed only when necessary. In the electrostatic protection circuit of the present embodiment, a first trigger circuit 10 having a first time constant τ1 is connected between a first power supply line 3 and a second power supply line 4. The first trigger signal is supplied to the buffer circuit 11. The buffer circuit 11 outputs a drive signal to the signal line 5 in response to the first trigger signal.

  A shunt circuit 14 is connected between the first power supply line 3 and the second power supply line 4. The drive signal output to the signal line 5 is supplied to the shunt circuit 14. On / off of the shunt circuit 14 is controlled by a drive signal.

  A second trigger circuit 12 having a second time constant τ 2 is connected between the first power supply line 3 and the signal line 5. The second trigger circuit 12 outputs a second trigger signal in response to a voltage fluctuation between the first power supply line 3 and the signal line 5.

  A switch circuit 13 is connected between the first power supply line 3 and the signal line 5. The second trigger signal of the second trigger circuit 12 is supplied to the switch circuit 13. On / off of the switch circuit 13 is controlled by the second trigger signal. The time constant τ 2 of the second trigger circuit 12 is set to a value smaller than the time constant τ 1 of the first trigger circuit 10.

  The time constant τ1 of the first trigger circuit 10 is set to 1 μS, which is a value 6 to 7 times the time constant 150 nS of the ESD test standard, for example. This is because the time constant τ 1 is set to a sufficiently large value with respect to the time constant 150 nS of the ESD test standard, and the ESD surge is sufficiently discharged by the shunt circuit 14.

  For example, the time constant τ2 of the second trigger circuit 12 is set to a value between 2 nS and 10 nS defined as the rise time of the ESD surge in the human body model of the ESD test standard. When the voltage applied between the first power supply line 3 and the signal line 5 has a rise earlier than the time constant τ2 of the second trigger circuit 12, the second trigger circuit 12 A trigger signal is supplied to the switch circuit 13 to turn on the switch circuit 13. When the switch circuit 13 is turned on, the first power supply line 3 and the signal line 5 are shunted, and supply of the drive signal from the buffer circuit 11 to the shunt circuit 14 is blocked. As a result, the shunt circuit 14 is turned off.

  For this reason, even if the time constant τ1 of the first trigger circuit 10 is set to a value sufficiently larger than the time constant defined by the ESD test standard, for example, the rise of the ESD surge that defines the time constant τ2 by the ESD test standard By setting the value of the time constant, it is possible to avoid a situation in which the shunt circuit 14 responds to fluctuations in voltage having a rise earlier than that of the ESD surge. Responding malfunctions can be avoided.

(Fourth embodiment)
FIG. 4 is a diagram illustrating a configuration of the electrostatic protection circuit of the fourth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the first trigger circuit 10 is configured by a CR circuit having a series circuit of a resistor 100 and a capacitor 101. The first trigger circuit 10 has a first time constant τ1. The first time constant τ1 is set by the values of the resistor 100 and the capacitor 101. The resistor 100 and the capacitor 101 are connected at the first common connection end 102. The first common connection terminal 102 is connected to the gate of the NMOS transistor 113 constituting the buffer circuit 11.

  The source of the NMOS transistor 113 is connected to the second power supply line 4, and the drain is connected to the second common connection end 112. The second common connection end 112 is connected to the first power supply line 3 via the resistor 111. Thereby, the source / drain path which is the main current path of the NMOS transistor 113 is electrically connected between the first power supply line 3 and the second power supply line 4.

  The second common connection end 112 is connected to the signal line 5. The signal line 5 is connected to the gate of the PMOS transistor 141 constituting the shunt circuit 14. The source of the PMOS transistor 141 is connected to the first power supply line 3, and the drain is connected to the second power supply line 4. As a result, the source / drain path which is the main current path of the PMOS transistor 141 is electrically connected between the first power supply line 3 and the second power supply line 4.

  A second trigger circuit 12 is connected between the signal line 5 and the first power supply line 3. The second trigger circuit 12 includes a CR circuit having a series circuit of a capacitor 121 and a resistor 120. The second trigger circuit 12 has a second time constant τ2. The second time constant τ 2 is set by the values of the resistor 120 and the capacitor 121. The capacitor 121 and the resistor 120 are connected at the third common connection end 122. The third common connection terminal 122 is connected to the gate of the PMOS transistor 131 constituting the switch circuit 13, that is, the control terminal of the switch circuit 13, and the output signal of the second trigger circuit 12 is input to the switch circuit 13. .

  The drain of the PMOS transistor 131 is connected to the signal line 5, and the source is connected to the first power supply line 3. As a result, the source / drain path which is the main current path of the PMOS transistor 131 is electrically connected between the signal line 5 and the first power supply line 3.

  The ESD protection operation of this embodiment is as follows. When a positive surge is applied to the first power supply line 3 with respect to the second power supply line 4 and the rise time of this ESD surge is shorter than the first time constant τ1, the first trigger circuit 10 responds. Thus, a current flows transiently through the first trigger circuit 10. When the voltage at the first common connection terminal 102 rises above the threshold value of the NMOS transistor 113 due to a voltage drop in the resistor 100 of the first trigger circuit 10, the NMOS transistor 113 is turned on. When the NMOS transistor 113 is turned on, the voltage of the second common connection end 112 is lowered to a voltage that is higher than the second power supply line 4 by a voltage drop by the NMOS transistor 113. The NMOS transistor 113 is turned on / off in response to the trigger signal of the first trigger circuit 10, and changes in the voltage generated at the first common connection terminal 102 from the voltage of the first power supply line 3 are substantially second. The signal is amplified to a change up to the voltage of the power supply line 4 and supplied as a drive signal to the second common connection end 112, and thus to the signal line 5.

  When the rise of the voltage fluctuation generated between the signal line 5 and the first power supply line 3 is earlier than the second time constant τ2, the second trigger circuit 12 responds to the second trigger circuit 12 in a transient manner. Current flows through When the voltage drop across the resistor 120 of the second trigger circuit 12 exceeds the threshold value of the PMOS transistor 131, the PMOS transistor 131 is turned on. When the PMOS transistor 131 is turned on, the potential of the signal line 5 is raised to a voltage lower than the voltage of the first power supply line 3 by the voltage drop between the source and drain of the PMOS transistor 131. Since the voltage drop between the source and the drain when the PMOS transistor 131 is turned on is smaller than the threshold voltage for turning on the PMOS transistor 141, the PMOS transistor 141 is turned off when the PMOS transistor 131 is turned on.

  According to the present embodiment, the first trigger circuit 10 responds to the ESD surge and outputs the first trigger signal. The buffer circuit 11 amplifies the first trigger signal and supplies it to the signal line 5 as a drive signal. In response to the drive signal, the PMOS transistor 141 of the shunt circuit 14 is turned on to discharge the ESD surge. On the other hand, when the rise of the voltage appearing on the signal line 5 is earlier than the time constant τ 2 of the second trigger circuit 12, the second trigger circuit 12 responds and the second trigger signal is supplied to the PMOS transistor 131. Then, the PMOS transistor 131 is turned on, and the PMOS transistor 141 of the shunt circuit 14 is turned off. Therefore, by setting the time constant τ2 of the second trigger circuit 12 to, for example, the rise time of the ESD surge specified in the ESD test standard, the shunt circuit 14 can cope with the fluctuation of the power supply voltage that rises earlier than the ESD surge. Can be prevented from malfunctioning.

(Fifth embodiment)
FIG. 5 is a diagram illustrating a configuration of the electrostatic protection circuit according to the fifth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals, and redundant description is performed only when necessary. The electrostatic protection circuit of the present embodiment includes a first trigger circuit 20 connected between the first power supply line 3 and the second power supply line 4. The first trigger circuit 20 has a first time constant τ1 and outputs a first trigger signal in response to a power supply voltage applied between the first power supply line 3 and the second power supply line 4. Output. The first trigger signal is supplied to the buffer circuit 21.

  For example, the time constant τ1 of the first trigger circuit 20 is set to a value between 2 nS and 10 nS defined as the rise time of the ESD surge in the human body model (HBM) of the ESD test standard. When the voltage applied between the first power supply line 3 and the second power supply line 4 has a rising earlier than the time constant τ1 of the first trigger circuit 20, the first trigger circuit 20 The first trigger signal is supplied to the buffer circuit 21.

  A second trigger circuit 22 having a second time constant τ 2 is connected between the first power supply line 3 and the second power supply line 4. The second time constant τ2 is set to a value larger than the first time constant τ1. The second time constant τ2 is set to 1 μS, which is a value 6 to 7 times 150 nS, for example, considering the time constant 150 nS defined by the ESD test standard. The second trigger circuit 22 responds to the fluctuation of the power supply voltage having a rise earlier than the second time constant τ 2, and supplies the second trigger signal to the buffer circuit 21.

  The buffer circuit 21 supplies a drive signal to the signal line 5 in response to the first trigger signal and the second trigger signal. That is, when both the first trigger signal and the second trigger signal are supplied, the buffer circuit 21 supplies the drive signal to the signal line 5. By setting the first time constant τ 1 to a value smaller than the second time constant τ 2, the first trigger circuit 20 and the second trigger circuit 20 can be used for fluctuations in the power supply voltage having a rise earlier than the second time constant τ 2. When the trigger circuit 22 responds, the buffer circuit 21 outputs a drive signal to the signal line 5.

  A shunt circuit 14 is connected between the first power supply line 3 and the second power supply line 4. On / off of the shunt circuit 14 is controlled by a drive signal output from the buffer circuit 21. That is, the buffer circuit 21 supplies a drive signal to the shunt circuit 14 in response to the fluctuation of the power supply voltage having a rise earlier than the first time constant τ1, and the shunt circuit 14 is turned on to perform the discharge operation.

  A feedback circuit 23 to which a drive signal for the signal line 5 is supplied is provided. The feedback circuit 23 performs a positive feedback operation so that the level of the drive signal of the signal line 5 is maintained in response to the drive signal of the buffer circuit 21. That is, when the drive signal of the signal line 5 is at the H level, the first trigger circuit so that the signal line 5 is maintained at the H level by the feedback loop configured via the first trigger circuit 20 and the buffer circuit 21. 20 acts.

  After the time set by the time constant τ2 of the second trigger circuit 22 has elapsed, the supply of the trigger signal from the second trigger circuit 22 to the buffer circuit 21 is completed. Thereby, the supply of the drive signal from the buffer circuit 21 to the signal line 5 is completed, and the shunt circuit 14 is turned off. That is, even if the power supply voltage rises faster than the first time constant τ1, the operation of the shunt circuit 14 ends after the time set by the second time constant τ2. Therefore, when the discharge shunt circuit 14 is turned on by the first trigger circuit 20 and the second trigger circuit 22 responding to the fluctuation of the power supply voltage that rises earlier than the first time constant τ1. However, the ON state of the shunt circuit 14 ends after the time set by the second time constant τ2 has elapsed. Therefore, it is possible to avoid a situation where the shunt circuit 14 is turned on for a long time and the shunt circuit 14 is destroyed.

  According to the present embodiment, the time constant τ1 of the first trigger circuit 20 is set to a value between 2 nS and 10 nS defined as the rise time of the ESD surge in the human body model (HBM) of the ESD test standard, for example. As a result, it is possible to avoid malfunctions due to fluctuations in the power supply voltage having a rise that is slower than the ESD surge. Even if the time constant τ1 is set to a small value, the level of the drive signal supplied to the shunt circuit 14 is maintained for the time set by the time constant τ2 by the positive feedback operation of the feedback circuit 23. Discharging by the shunt circuit 14 can be ensured. In addition, after the time set by the time constant τ2 of the second trigger circuit 22 has elapsed, the on operation of the shunt circuit 14 is completed, so that the shunt circuit 14 is turned on for a long time, leading to destruction. It can be avoided.

(Sixth embodiment)
FIG. 6 is a diagram illustrating a configuration of the electrostatic protection circuit according to the sixth embodiment. Constituent elements corresponding to the above-described embodiment are denoted by the same reference numerals. In the present embodiment, the first trigger circuit 20 is configured by a CR circuit having a series circuit of a resistor 200 and a capacitor 201. The first trigger circuit 20 has a first time constant τ1. The first time constant τ1 is set by the values of the resistor 200 and the capacitor 201. The resistor 200 and the capacitor 201 are connected by the first common connection end 202. The first common connection terminal 202 is connected to the gate of the PMOS transistor 211 constituting the buffer circuit 21.

  The drain of the PMOS transistor 211 is connected to the second common connection terminal 213. A resistor 212 is connected between the second common connection end 213 and the second power supply line 4. The source of the PMOS transistor 211 is connected to the drain of the PMOS transistor 210. The source of the PMOS transistor 210 is connected to the first power supply line 3.

  The second common connection end 213 is connected to the signal line 5. The signal line 5 is connected to the gate of the NMOS transistor 140 constituting the shunt circuit 14. The source of the NMOS transistor 140 is connected to the second power supply line 4, and the drain is connected to the first power supply line 3. That is, the source / drain path which is the main current path of the NMOS transistor 140 is connected between the first power supply line 3 and the second power supply line 4.

A second trigger circuit 22 is connected between the first power supply line 3 and the second power supply line 4. The second trigger circuit 22 is configured by a CR circuit having a series circuit of a resistor 220 and a capacitor 221. The resistor 220 and the capacitor 221 are connected at the third common connection end 222.
The second trigger circuit 22 has a second time constant τ2. The second time constant is set by the values of the resistor 220 and the capacitor 221. The second time constant τ2 is set to a value larger than the first time constant τ1. The second time constant τ2 is set to 1 μS, which is a value 6 to 7 times 150 nS, for example, considering the time constant 150 nS that is an ESD test standard. The second time constant τ 2 is set by the resistor 220 and the capacitor 221. The second trigger circuit 22 responds to the fluctuation of the power supply voltage having a rise earlier than the second time constant τ 2, and supplies the second trigger signal to the buffer circuit 21. The third common connection end 222 is connected to the gate of the PMOS transistor 210 constituting the buffer circuit 21.

  The second common connection end 213 of the buffer circuit 21 is connected to the gate of the NMOS transistor 230 constituting the feedback circuit 23. The source of the NMOS transistor 230 is connected to the second power supply line 4, and the drain is connected to the first common connection terminal 202 of the first trigger circuit 20.

  The ESD protection operation of this embodiment is as follows. When a positive surge is applied to the first power supply line 3 with respect to the second power supply line 4 and the rise time of the ESD surge is shorter than the first time constant τ1, the first trigger circuit 20 responds. Thus, a current flows transiently through the first trigger circuit 20. The voltage at the first common connection terminal 202 decreases due to the voltage drop at the resistor 200 of the first trigger circuit 20.

  Since the time constant τ2 of the second trigger circuit 22 is set to a value larger than the first time constant τ1, the second trigger circuit 22 also responds to the second trigger circuit 22 in a transient manner. Current flows. When the voltage at the third common connection end 222 drops below the threshold value of the PMOS transistor 210 due to the voltage drop at the resistor 220 of the second trigger circuit 22, the PMOS transistor 210 is turned on. At this time, if the voltage of the first common connection end 202 of the first trigger circuit 20 is lowered to a voltage for turning on the PMOS transistor 211, the PMOS transistor 211 is also turned on, and the PMOS transistor 211 and the PMOS transistor 211 are connected. Current flows through the resistor 212.

  When the voltage drop generated in the resistor 212 due to the current flowing through the resistor 212 exceeds the threshold value of the NMOS transistor 230, the NMOS transistor 230 is turned on. When the NMOS transistor 230 is turned on, the voltage of the first common connection terminal 202 of the first trigger circuit 20 is higher than the voltage of the second power supply line 4 by the voltage drop between the source and drain of the NMOS transistor 230. Pulled down. By reducing the voltage of the first common connection end 202, a low voltage, that is, a voltage that maintains the PMOS transistor 211 in the on state is applied to the gate of the PMOS transistor 211. That is, a positive feedback loop that maintains the ON state of the buffer circuit 21 is formed by a feedback loop from the buffer circuit 21 via the feedback circuit 23. Thereby, since the voltage of the signal line 5 is maintained at the H level, the NMOS transistor 140 is maintained in the ON state, and the surge discharge by the NMOS transistor 140 is performed. That is, even when the time constant τ1 of the first trigger circuit 20 is set to a small value, the surge discharge operation by the NMOS transistor 140 constituting the shunt circuit 14 can be ensured.

  When the time set by the second time constant τ2 elapses, the supply of the trigger signal from the second trigger circuit 22 to the PMOS transistor 210 ends. Thereby, the buffer circuit 21 is turned off, and the feedback operation to the first trigger circuit 20 via the feedback circuit 23 is also completed. When the buffer circuit 21 is turned off, the voltage of the signal line 5 becomes L level, and the NMOS transistor 140 constituting the shunt circuit 14 is turned off. That is, the supply of the drive signal to the shunt circuit 14 by the buffer circuit 21 is maintained for a fixed time by the feedback operation of the feedback circuit 23, but is terminated after the time set by the second time constant τ2. For this reason, it is possible to avoid a situation in which the NMOS transistor 140 constituting the shunt circuit 14 is turned on for a long time and is destroyed. Further, by setting the first time constant τ1 set to a small value with respect to the second time constant τ2 to 2 nS to 10 nS which is the rise time of the ESD surge determined by the ESD test standard, it is slower than the ESD surge. It can be configured not to respond to the rise of the power supply voltage.

  According to the present embodiment, it is possible to provide an electrostatic protection circuit that does not malfunction due to fluctuations in the power supply voltage that rises later than the ESD surge by setting the first time constant τ1. In addition, since the shunt circuit 14 can be turned off after the elapse of the time constant τ2 by setting the second time constant τ2, it is possible to avoid a situation in which the shunt circuit 14 is turned on for a long time and is destroyed. I can do it.

  The conductivity type of the NMOS transistor 140 constituting the shunt circuit 14 can be changed to a PMOS transistor. The electrostatic protection circuit can be similarly configured by changing the conductivity type and connection relationship of each trigger circuit (20, 22) and the PMOS transistor constituting the buffer circuit 21 in accordance with the change of the conductivity type. Further, the NMOS transistor 140 can be changed to a bipolar transistor. When a bipolar transistor is used, an NPN bipolar transistor can be used in place of the NMOS transistor because of the bias.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  3 First power line, 4 Second power line, 5 Signal line, 10 First trigger circuit, 11 Buffer circuit, 12 Second trigger circuit, 13 Switch circuit, 14 Shunt circuit

Claims (7)

A first trigger circuit connected between the first power supply line and the second power supply line, including a capacitor and a resistor constituting a first CR circuit having a first time constant, and outputting a first trigger signal When,
A buffer circuit for outputting a drive signal to a signal line in response to the first trigger signal;
A shunt circuit connected to a main current path between the first power supply line and the second power supply line and responsive to the drive signal;
A second CR circuit connected between the signal line and the first power supply line or between the signal line and the second power supply line and having a second time constant smaller than the first time constant. A second trigger circuit that outputs a second trigger signal, including a capacitor and a resistor,
The electrostatic discharge protection circuit, wherein the second trigger signal cuts off a main current path of the shunt circuit.   The electrostatic protection circuit according to claim 1, wherein the drive signal conducts a main current path of the shunt circuit. A switch circuit connected between the signal line and the first power supply line or between the signal line and the second power supply line;
The electrostatic protection circuit according to claim 1, wherein the switch circuit is responsive to the second trigger signal.   The switch circuit has a main current path connected between the signal line and the first power supply line, or between the signal line and the second power supply line, and the gate is supplied with the second trigger signal. The electrostatic protection circuit according to claim 3, further comprising a first MOS transistor.   The shunt circuit includes a second MOS transistor having a main current path connected between the first power supply line and the second power supply line and a gate connected to the signal line. The electrostatic protection circuit according to any one of 1 to 4.   The first time constant is set to a value 6 to 7 times the time constant of the human body charging model of the ESD test standard, and the second time constant is set to a value of 2 nS to 10 nS. The electrostatic protection circuit according to claim 1. A first CR circuit having a first time constant, connected between the first power supply line and the second power supply line and including a capacitor and a resistor;
A main current path is disposed between the first power supply line and the second power supply line, a gate has a MOS transistor to which the output signal of the first CR circuit is input, and a drive signal is output to the signal line A buffer circuit to
A shunt circuit having a MOS transistor in which a main current path is connected between the first power supply line and the second power supply line, and a gate is connected to the signal line;
A capacitor having a second time constant smaller than the first time constant and connected between the signal line and the first power supply line or between the signal line and the second power supply line; A second CR circuit including:
A switch circuit connected between the signal line and the first power supply line, or between the signal line and the second power supply line, and an output signal of the second CR circuit is input to a control terminal;
An electrostatic protection circuit comprising:

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